arch: Add imx7d m4 soc support
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7 core and Single Cortex M4 core. Zephyr was ported to run on the M4 core. In a later release, it will also communicate with the A7 core (running Linux) via RPmsg. The low level drivers come from NXP FreeRTOS BSP and are located at ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README The A7 core is responsible to load the M4 binary application into the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at bootloader level after the Linux system has booted. The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: +---------------+-----------------+---------------------------+ | Memory Name | Start Address | Size | +===============+=================+===========================+ | TCML | 0x007F8000 | 32KB | +---------------+-----------------+---------------------------+ | TCMU | 0x20000000 | 32KB | +---------------+-----------------+---------------------------+ | OCRAM_S | 0x20180000 | 32KB | +---------------+-----------------+---------------------------+ | OCRAM | 0x00900000 | 128KB | +---------------+-----------------+---------------------------+ | DDR | 0x10000000 | 256MB | +---------------+-----------------+---------------------------+ Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
This commit is contained in:
Diego Sueiro
Maureen Helm
parent
346165b2e8
commit
816330239e
7
arch/arm/soc/nxp_imx/mcimx7_m4/CMakeLists.txt
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7
arch/arm/soc/nxp_imx/mcimx7_m4/CMakeLists.txt
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@ -0,0 +1,7 @@
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#
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# Copyright (c) 2017, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_sources(soc.c)
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40
arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4
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40
arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4
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# Kconfig - iMX7 M4 core series
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#
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# Copyright (c) 2017, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_MCIMX7_M4
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config SOC
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string
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default mcimx7d
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config SYS_CLOCK_TICKS_PER_SEC
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int
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default 1000
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 200000000
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if CLOCK_CONTROL
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config CLOCK_CONTROL_IMX_CCM
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def_bool y
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endif # CLOCK_CONTROL
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if SERIAL
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config UART_IMX
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def_bool y
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endif # SERIAL
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config DOMAIN_ID
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int
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default 1
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endif # SOC_MCIMX7_M4
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20
arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.defconfig.series
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20
arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.defconfig.series
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@ -0,0 +1,20 @@
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# Kconfig - iMX7 M4 core series
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#
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# Copyright (c) 2017, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_IMX7_M4
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config SOC_SERIES
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default mcimx7_m4
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config NUM_IRQS
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int
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# must be >= the highest interrupt number used
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default 127
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source "arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4"
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endif # SOC_SERIES_IMX7_M4
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17
arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.series
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arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.series
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# Kconfig - iMX7 M4 core series
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#
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# Copyright (c) 2017, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SERIES_IMX7_M4
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bool "i.MX7 M4 Core Series"
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select CPU_CORTEX_M
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select CPU_CORTEX_M4
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select SOC_FAMILY_IMX
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select CPU_HAS_SYSTICK
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select CLOCK_CONTROL
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select CPU_HAS_FPU
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help
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Enable support for i.MX7 M4 MCU series
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31
arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.soc
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arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.soc
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# Kconfig - iMX7 M4 core series
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#
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# Copyright (c) 2017, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "i.MX7 M4 Selection"
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depends on SOC_SERIES_IMX7_M4
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config SOC_MCIMX7_M4
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bool "SOC_MCIMX7_M4"
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select HAS_IMX_HAL
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endchoice
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if SOC_MCIMX7_M4
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config SOC_PART_NUMBER_MCIMX7D5EVM10SC
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bool
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config SOC_PART_NUMBER_IMX7_M4
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string
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default "MCIMX7D5EVM10SC" if SOC_PART_NUMBER_MCIMX7D5EVM10SC
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help
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This string holds the full part number of the SoC. It is a hidden option
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that you should not set directly. The part number selection choice defines
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the default value for this string.
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endif # SOC_SERIES_IMX7_M4
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60
arch/arm/soc/nxp_imx/mcimx7_m4/dts.fixup
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60
arch/arm/soc/nxp_imx/mcimx7_m4/dts.fixup
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/*
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* Copyright (c) 2018, Diego Sueiro <diego.sueiro@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define CONFIG_UART_IMX_UART_1_NAME NXP_IMX_UART_30860000_LABEL
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#define CONFIG_UART_IMX_UART_1_BASE_ADDRESS NXP_IMX_UART_30860000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_1_BAUD_RATE NXP_IMX_UART_30860000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_1_IRQ_NUM NXP_IMX_UART_30860000_IRQ_0
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#define CONFIG_UART_IMX_UART_1_IRQ_PRI NXP_IMX_UART_30860000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_1_MODEM_MODE NXP_IMX_UART_30860000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_2_NAME NXP_IMX_UART_30890000_LABEL
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#define CONFIG_UART_IMX_UART_2_BASE_ADDRESS NXP_IMX_UART_30890000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_2_BAUD_RATE NXP_IMX_UART_30890000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_2_IRQ_NUM NXP_IMX_UART_30890000_IRQ_0
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#define CONFIG_UART_IMX_UART_2_IRQ_PRI NXP_IMX_UART_30890000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_2_MODEM_MODE NXP_IMX_UART_30890000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_3_NAME NXP_IMX_UART_30880000_LABEL
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#define CONFIG_UART_IMX_UART_3_BASE_ADDRESS NXP_IMX_UART_30880000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_3_BAUD_RATE NXP_IMX_UART_30880000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_3_IRQ_NUM NXP_IMX_UART_30880000_IRQ_0
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#define CONFIG_UART_IMX_UART_3_IRQ_PRI NXP_IMX_UART_30880000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_3_MODEM_MODE NXP_IMX_UART_30880000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_4_NAME NXP_IMX_UART_30A60000_LABEL
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#define CONFIG_UART_IMX_UART_4_BASE_ADDRESS NXP_IMX_UART_30A60000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_4_BAUD_RATE NXP_IMX_UART_30A60000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_4_IRQ_NUM NXP_IMX_UART_30A60000_IRQ_0
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#define CONFIG_UART_IMX_UART_4_IRQ_PRI NXP_IMX_UART_30A60000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_4_MODEM_MODE NXP_IMX_UART_30A60000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_5_NAME NXP_IMX_UART_30A70000_LABEL
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#define CONFIG_UART_IMX_UART_5_BASE_ADDRESS NXP_IMX_UART_30A70000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_5_BAUD_RATE NXP_IMX_UART_30A70000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_5_IRQ_NUM NXP_IMX_UART_30A70000_IRQ_0
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#define CONFIG_UART_IMX_UART_5_IRQ_PRI NXP_IMX_UART_30A70000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_5_MODEM_MODE NXP_IMX_UART_30A70000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_6_NAME NXP_IMX_UART_30A80000_LABEL
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#define CONFIG_UART_IMX_UART_6_BASE_ADDRESS NXP_IMX_UART_30A80000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_6_BAUD_RATE NXP_IMX_UART_30A80000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_6_IRQ_NUM NXP_IMX_UART_30A80000_IRQ_0
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#define CONFIG_UART_IMX_UART_6_IRQ_PRI NXP_IMX_UART_30A80000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_6_MODEM_MODE NXP_IMX_UART_30A80000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_7_NAME NXP_IMX_UART_30A90000_LABEL
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#define CONFIG_UART_IMX_UART_7_BASE_ADDRESS NXP_IMX_UART_30A90000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_7_BAUD_RATE NXP_IMX_UART_30A90000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_7_IRQ_NUM NXP_IMX_UART_30A90000_IRQ_0
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#define CONFIG_UART_IMX_UART_7_IRQ_PRI NXP_IMX_UART_30A90000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_7_MODEM_MODE NXP_IMX_UART_30A90000_MODEM_MODE
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/* End of SoC Level DTS fixup file */
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7
arch/arm/soc/nxp_imx/mcimx7_m4/linker.ld
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7
arch/arm/soc/nxp_imx/mcimx7_m4/linker.ld
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/arm/cortex_m/scripts/linker.ld>
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95
arch/arm/soc/nxp_imx/mcimx7_m4/soc.c
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95
arch/arm/soc/nxp_imx/mcimx7_m4/soc.c
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/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <soc.h>
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#include "wdog_imx.h"
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/* Initialize clock. */
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void SOC_ClockInit(void)
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{
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/* OSC/PLL is already initialized by Cortex-A7 (u-boot) */
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/*
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* Disable WDOG3
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* Note : The WDOG clock Root is shared by all the 4 WDOGs,
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* so Zephyr code should avoid closing it
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*/
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CCM_UpdateRoot(CCM, ccmRootWdog, ccmRootmuxWdogOsc24m, 0, 0);
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CCM_EnableRoot(CCM, ccmRootWdog);
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CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNeededRun);
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RDC_SetPdapAccess(RDC, rdcPdapWdog3,
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RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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WDOG_DisablePowerdown(WDOG3);
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CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNotNeeded);
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/* We need system PLL Div2 to run M4 core */
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CCM_ControlGate(CCM, ccmPllGateSys, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmPllGateSysDiv2, ccmClockNeededRun);
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/* Enable clock gate for IP bridge and IO mux */
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CCM_ControlGate(CCM, ccmCcgrGateIpmux1, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIpmux2, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIpmux3, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIomux, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIomuxLpsr, ccmClockNeededRun);
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/* Enable clock gate for RDC */
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CCM_ControlGate(CCM, ccmCcgrGateRdc, ccmClockNeededRun);
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}
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void SOC_RdcInit(void)
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{
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/* Move M4 core to specific RDC domain */
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RDC_SetDomainID(RDC, rdcMdaM4, CONFIG_DOMAIN_ID, false);
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}
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#ifdef CONFIG_UART_IMX
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static void nxp_mcimx7_uart_config(void)
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{
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#ifdef CONFIG_UART_IMX_UART_2
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/* We need to grasp board uart exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapUart2,
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RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootUart2, ccmRootmuxUartOsc24m, 0, 0);
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/* Enable uart clock */
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CCM_EnableRoot(CCM, ccmRootUart2);
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/*
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* IC Limitation
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* M4 stop will cause A7 UART lose functionality
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* So we need UART clock all the time
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*/
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CCM_ControlGate(CCM, ccmCcgrGateUart2, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_UART_IMX_UART_2 */
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}
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#endif /* CONFIG_UART_IMX */
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static int nxp_mcimx7_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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/* SoC specific RDC settings */
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SOC_RdcInit();
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/* BoC specific clock settings */
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SOC_ClockInit();
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#ifdef CONFIG_UART_IMX
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nxp_mcimx7_uart_config();
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#endif /* CONFIG_UART_IMX */
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return 0;
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}
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SYS_INIT(nxp_mcimx7_init, PRE_KERNEL_1, 0);
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34
arch/arm/soc/nxp_imx/mcimx7_m4/soc.h
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34
arch/arm/soc/nxp_imx/mcimx7_m4/soc.h
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/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#include "rdc.h"
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#include "rdc_defs_imx7d.h"
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#include "ccm_imx7d.h"
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#include "clock_freq.h"
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#define RDC_DOMAIN_PERM_NONE (0x0)
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#define RDC_DOMAIN_PERM_W (0x1)
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#define RDC_DOMAIN_PERM_R (0x2)
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#define RDC_DOMAIN_PERM_RW (RDC_DOMAIN_PERM_W|RDC_DOMAIN_PERM_R)
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#define RDC_DOMAIN_PERM(domain, perm) (perm << (domain * 2))
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#endif /* !_ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC__H_ */
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145
dts/arm/nxp/nxp_imx7d_m4.dtsi
Normal file
145
dts/arm/nxp/nxp_imx7d_m4.dtsi
Normal file
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/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4";
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reg = <0>;
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};
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};
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soc {
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ddr_code: code@10000000 {
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compatible = "nxp,imx-code-bus";
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reg = <0x10000000 0xfff0000>;
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label = "DDR CODE";
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};
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ddr_sys: memory@80000000 {
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device_type = "memory";
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compatible = "nxp,imx-sys-bus";
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reg = <0x80000000 0x60000000>;
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label = "DDR SYSTEM";
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};
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tcml_code: code@1fff8000 {
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compatible = "nxp,imx-code-bus";
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reg = <0x1fff8000 0x8000>;
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label = "TCML CODE";
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};
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tcmu_sys: memory@20000000 {
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device_type = "memory";
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compatible = "nxp,imx-sys-bus";
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reg = <0x20000000 0x8000>;
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label = "TCMU SYSTEM";
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};
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ocram_code: code@00900000 {
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compatible = "nxp,imx-code-bus";
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reg = <0x00900000 0x20000>;
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label = "OCRAM CODE";
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};
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ocram_sys: memory@20200000 {
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device_type = "memory";
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compatible = "nxp,imx-sys-bus";
|
||||
reg = <0x20200000 0x20000>;
|
||||
label = "OCRAM SYSTEM";
|
||||
};
|
||||
|
||||
ocram_s_code: code@20180000 {
|
||||
compatible = "nxp,imx-code-bus";
|
||||
reg = <0x20180000 0x8000>;
|
||||
label = "OCRAM_S CODE";
|
||||
};
|
||||
|
||||
ocram_s_sys: memory@00180000 {
|
||||
device_type = "memory";
|
||||
compatible = "nxp,imx-sys-bus";
|
||||
reg = <0x00180000 0x8000>;
|
||||
label = "OCRAM_S SYSTEM";
|
||||
};
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "nxp,imx-gpio";
|
||||
reg = <0x30200000 0x10000>;
|
||||
interrupts = <62 0>, <63 0>;
|
||||
label = "GPIO_1";
|
||||
};
|
||||
|
||||
/* For now only uart2 is supported and
|
||||
* tested with the serial driver
|
||||
*/
|
||||
uart1: uart@30860000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
interrupts = <26 3>;
|
||||
label = "UART_1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@30890000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
interrupts = <27 3>;
|
||||
label = "UART_2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: uart@30880000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
interrupts = <28 3>;
|
||||
label = "UART_3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: uart@30A60000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x30A60000 0x10000>;
|
||||
interrupts = <29 3>;
|
||||
label = "UART_4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: uart@30A70000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x30A70000 0x10000>;
|
||||
interrupts = <30 3>;
|
||||
label = "UART_5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: uart@30A80000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x30A80000 0x10000>;
|
||||
interrupts = <16 3>;
|
||||
label = "UART_6";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: uart@30A90000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x30A90000 0x10000>;
|
||||
interrupts = <126 3>;
|
||||
label = "UART_7";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <4>;
|
||||
};
|
||||
Loading…
Reference in a new issue