board: riscv: add qemu_riscv32_xip board to test XIP mode

Add a variant riscv build target that only is run for tests tagged
with "xip".

Signed-off-by: Jim Shu <cwshu@andestech.com>

boards/riscv/qemu_riscv32/Kconfig.board

@@ -5,3 +5,9 @@ config BOARD_QEMU_RISCV32
 	depends on SOC_RISCV_VIRT
 	select QEMU_TARGET
 	select CPU_HAS_FPU
+
+config BOARD_QEMU_RISCV32_XIP
+	bool "QEMU RISCV32 XIP target"
+	depends on SOC_RISCV_SIFIVE_FREEDOM
+	select QEMU_TARGET
+	select CPU_HAS_FPU

boards/riscv/qemu_riscv32/Kconfig.defconfig

@@ -1,14 +1,11 @@
 # SPDX-License-Identifier: Apache-2.0
 
-if BOARD_QEMU_RISCV32
-
 config BUILD_OUTPUT_BIN
 	default n
 
 config BOARD
-	default "qemu_riscv32"
+	default "qemu_riscv32" if BOARD_QEMU_RISCV32
+	default "qemu_riscv32_xip" if BOARD_QEMU_RISCV32_XIP
 
 config COMPRESSED_ISA
 	default y
-
-endif

boards/riscv/qemu_riscv32/board.cmake

@@ -5,10 +5,19 @@ set(EMU_PLATFORM qemu)
 set(QEMU_binary_suffix riscv32)
 set(QEMU_CPU_TYPE_${ARCH} riscv32)
 
-set(QEMU_FLAGS_${ARCH}
-  -nographic
-  -machine virt
-  -bios none
-  -m 256
-  )
+if(CONFIG_BOARD_QEMU_RISCV32)
+  set(QEMU_FLAGS_${ARCH}
+    -nographic
+    -machine virt
+    -bios none
+    -m 256
+    )
+else()
+  set(QEMU_FLAGS_${ARCH}
+    -nographic
+    -machine sifive_e
+    )
+endif()
+
+
 board_set_debugger_ifnset(qemu)

boards/riscv/qemu_riscv32/qemu_riscv32_xip.dts

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2021 Jim Shu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <riscv32-fe310.dtsi>
+
+/ {
+	model = "SiFive HiFive 1";
+	compatible = "sifive,hifive1";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &dtim;
+		zephyr,flash = &flash0;
+	};
+
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <16000000>;
+};
+
+&uart1 {
+	clock-frequency = <16000000>;
+};
+
+&spi0 {
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0x10014000 0x1000 0x20400000 0xc00000>;
+	flash0: flash@0 {
+		compatible = "issi,is25lp128", "jedec,spi-nor";
+		size = <134217728>;
+		label = "FLASH0";
+		jedec-id = [96 60 18];
+		reg = <0>;
+		// Dummy entry
+		spi-max-frequency = <0>;
+	};
+};

boards/riscv/qemu_riscv32/qemu_riscv32_xip.yaml

@@ -0,0 +1,13 @@
+identifier: qemu_riscv32_xip
+name: QEMU Emulation for RISC-V 32-bit in XIP mode
+type: qemu
+simulation: qemu
+arch: riscv32
+ram: 16
+toolchain:
+  - zephyr
+  - xtools
+testing:
+  default: true
+  only_tags:
+     - xip

boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig

@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM=y
+CONFIG_SOC_RISCV_SIFIVE_FREEDOM=y
+CONFIG_BOARD_QEMU_RISCV32_XIP=y
+CONFIG_CONSOLE=y
+CONFIG_PRINTK=y
+CONFIG_SERIAL=y
+CONFIG_UART_SIFIVE=y
+CONFIG_UART_SIFIVE_PORT_0=y
+CONFIG_UART_CONSOLE=y
+CONFIG_PLIC=y
+CONFIG_PINMUX=y
+CONFIG_PINMUX_SIFIVE=y
+CONFIG_RISCV_MACHINE_TIMER=y
+CONFIG_GPIO=y
+CONFIG_GPIO_SIFIVE=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000
+CONFIG_QEMU_ICOUNT_SHIFT=6
+CONFIG_CORE_E31=y