dts: arm: introduce support for NXP S32K146
Add minimal support for S32K146 devices including clocks, MPU, pin control, GPIO and UART. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles
Anas Nashif
parent
91293187d8
commit
81de2af68f
51
dts/arm/nxp/nxp_s32k146.dtsi
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51
dts/arm/nxp/nxp_s32k146.dtsi
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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <dt-bindings/clock/nxp_s32k146_clock.h>
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#include <nxp/nxp_s32k1xx.dtsi>
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/ {
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cpus {
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cpu@0 {
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compatible = "arm,cortex-m4f";
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};
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};
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soc {
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/*
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* SRAM_L and SRAM_U ranges form a contiguous block but misaligned
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* and burst accesses cannot occur across the 0x20000000 boundary
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* that separates the two SRAM arrays. Hence, treat the two arrays
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* as separate memory ranges.
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*/
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sram_l: sram@1fff0000 {
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compatible = "mmio-sram";
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reg = <0x1fff0000 DT_SIZE_K(64)>;
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};
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sram_u: sram@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(60)>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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&ftfc {
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 DT_SIZE_M(1)>;
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erase-block-size = <DT_SIZE_K(4)>;
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write-block-size = <8>;
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};
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};
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&lpuart2 {
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clocks = <&clock NXP_S32_LPUART2_CLK>;
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};
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156
dts/arm/nxp/nxp_s32k1xx.dtsi
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156
dts/arm/nxp/nxp_s32k1xx.dtsi
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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-m.dtsi>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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};
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};
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/* Dummy pinctrl node, filled with pin mux options at board level */
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pinctrl: pinctrl {
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compatible = "nxp,kinetis-pinctrl";
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status = "okay";
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};
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soc {
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interrupt-parent = <&nvic>;
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mpu: mpu@4000d000 {
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compatible = "nxp,kinetis-mpu";
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reg = <0x4000d000 0x1000>;
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status = "disabled";
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};
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ftfc: flash-controller@40020000 {
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compatible = "nxp,kinetis-ftfc";
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reg = <0x40020000 0x1000>;
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interrupts = <18 0>, <19 0>, <21 0>;
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interrupt-names = "command-complete", "read-collision", "double-bit";
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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porta: pinmux@40049000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x40049000 0x1000>;
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clocks = <&clock NXP_S32_PORTA_CLK>;
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};
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portb: pinmux@4004a000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004a000 0x1000>;
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clocks = <&clock NXP_S32_PORTB_CLK>;
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};
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portc: pinmux@4004b000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004b000 0x1000>;
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clocks = <&clock NXP_S32_PORTC_CLK>;
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};
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portd: pinmux@4004c000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004c000 0x1000>;
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clocks = <&clock NXP_S32_PORTD_CLK>;
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};
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porte: pinmux@4004d000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004d000 0x1000>;
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clocks = <&clock NXP_S32_PORTE_CLK>;
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};
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clock: clock-controller@40064000 {
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compatible = "nxp,s32-clock";
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reg = <0x40064000 0x1000>, <0x40065000 0x1000>;
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#clock-cells = <1>;
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status = "okay";
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};
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lpuart0: uart@4006a000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x4006a000 0x1000>;
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interrupts = <31 0>;
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clocks = <&clock NXP_S32_LPUART0_CLK>;
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status = "disabled";
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};
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lpuart1: uart@4006b000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x4006b000 0x1000>;
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interrupts = <33 0>;
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clocks = <&clock NXP_S32_LPUART1_CLK>;
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status = "disabled";
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};
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lpuart2: uart@4006c000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x4006c000 0x1000>;
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interrupts = <35 0>;
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status = "disabled";
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};
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gpioa: gpio@400ff000 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x400ff000 0x40>;
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interrupts = <59 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porta>;
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status = "disabled";
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};
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gpiob: gpio@400ff040 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x400ff040 0x40>;
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interrupts = <60 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portb>;
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status = "disabled";
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};
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gpioc: gpio@400ff080 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x400ff080 0x40>;
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interrupts = <61 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portc>;
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status = "disabled";
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};
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gpiod: gpio@400ff0c0 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x400ff0c0 0x40>;
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interrupts = <62 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portd>;
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status = "disabled";
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};
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gpioe: gpio@400ff100 {
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compatible = "nxp,kinetis-gpio";
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reg = <0x400ff100 0x40>;
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interrupts = <63 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porte>;
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status = "disabled";
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};
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};
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};
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99
include/zephyr/dt-bindings/clock/nxp_s32k146_clock.h
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99
include/zephyr/dt-bindings/clock/nxp_s32k146_clock.h
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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_
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#define NXP_S32_LPO_128K_CLK 1U
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#define NXP_S32_SIRC_CLK 2U
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#define NXP_S32_SIRC_VLP_CLK 3U
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#define NXP_S32_SIRC_STOP_CLK 4U
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#define NXP_S32_FIRC_CLK 5U
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#define NXP_S32_FIRC_VLP_CLK 6U
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#define NXP_S32_FIRC_STOP_CLK 7U
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#define NXP_S32_SOSC_CLK 8U
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#define NXP_S32_SPLL_CLK 9U
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#define NXP_S32_SIRCDIV1_CLK 10U
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#define NXP_S32_SIRCDIV2_CLK 11U
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#define NXP_S32_FIRCDIV1_CLK 12U
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#define NXP_S32_FIRCDIV2_CLK 13U
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#define NXP_S32_SOSCDIV1_CLK 14U
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#define NXP_S32_SOSCDIV2_CLK 15U
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#define NXP_S32_SPLLDIV1_CLK 16U
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#define NXP_S32_SPLLDIV2_CLK 17U
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#define NXP_S32_LPO_32K_CLK 18U
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#define NXP_S32_LPO_1K_CLK 19U
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#define NXP_S32_TCLK0_REF_CLK 20U
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#define NXP_S32_TCLK1_REF_CLK 21U
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#define NXP_S32_TCLK2_REF_CLK 22U
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#define NXP_S32_SCS_CLK 24U
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#define NXP_S32_SCS_RUN_CLK 25U
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#define NXP_S32_SCS_VLPR_CLK 26U
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#define NXP_S32_SCS_HSRUN_CLK 27U
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#define NXP_S32_CORE_CLK 28U
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#define NXP_S32_CORE_RUN_CLK 29U
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#define NXP_S32_CORE_VLPR_CLK 30U
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#define NXP_S32_CORE_HSRUN_CLK 31U
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#define NXP_S32_BUS_CLK 32U
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#define NXP_S32_BUS_RUN_CLK 33U
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#define NXP_S32_BUS_VLPR_CLK 34U
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#define NXP_S32_BUS_HSRUN_CLK 35U
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#define NXP_S32_SLOW_CLK 36U
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#define NXP_S32_SLOW_RUN_CLK 37U
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#define NXP_S32_SLOW_VLPR_CLK 38U
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#define NXP_S32_SLOW_HSRUN_CLK 39U
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#define NXP_S32_RTC_CLK 40U
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#define NXP_S32_LPO_CLK 41U
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#define NXP_S32_SCG_CLKOUT_CLK 42U
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#define NXP_S32_FTM0_EXT_CLK 43U
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#define NXP_S32_FTM1_EXT_CLK 44U
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#define NXP_S32_FTM2_EXT_CLK 45U
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#define NXP_S32_FTM3_EXT_CLK 46U
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#define NXP_S32_FTM4_EXT_CLK 47U
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#define NXP_S32_FTM5_EXT_CLK 48U
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#define NXP_S32_ADC0_CLK 50U
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#define NXP_S32_ADC1_CLK 51U
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#define NXP_S32_CLKOUT0_CLK 52U
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#define NXP_S32_CMP0_CLK 53U
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#define NXP_S32_CRC0_CLK 54U
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#define NXP_S32_DMA0_CLK 55U
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#define NXP_S32_DMAMUX0_CLK 56U
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#define NXP_S32_EIM0_CLK 57U
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#define NXP_S32_ERM0_CLK 58U
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#define NXP_S32_EWM0_CLK 59U
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#define NXP_S32_FLEXCAN0_CLK 60U
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#define NXP_S32_FLEXCAN1_CLK 61U
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#define NXP_S32_FLEXCAN2_CLK 62U
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#define NXP_S32_FLEXIO_CLK 63U
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#define NXP_S32_FTFC_CLK 64U
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#define NXP_S32_FTM0_CLK 65U
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#define NXP_S32_FTM1_CLK 66U
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#define NXP_S32_FTM2_CLK 67U
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#define NXP_S32_FTM3_CLK 68U
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#define NXP_S32_FTM4_CLK 69U
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#define NXP_S32_FTM5_CLK 70U
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#define NXP_S32_LPI2C0_CLK 71U
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#define NXP_S32_LPIT0_CLK 72U
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#define NXP_S32_LPSPI0_CLK 73U
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#define NXP_S32_LPSPI1_CLK 74U
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#define NXP_S32_LPSPI2_CLK 75U
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#define NXP_S32_LPTMR0_CLK 76U
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#define NXP_S32_LPUART0_CLK 77U
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#define NXP_S32_LPUART1_CLK 78U
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#define NXP_S32_LPUART2_CLK 79U
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#define NXP_S32_MPU0_CLK 80U
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#define NXP_S32_MSCM0_CLK 81U
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#define NXP_S32_PDB0_CLK 82U
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#define NXP_S32_PDB1_CLK 83U
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#define NXP_S32_PORTA_CLK 84U
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#define NXP_S32_PORTB_CLK 85U
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#define NXP_S32_PORTC_CLK 86U
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#define NXP_S32_PORTD_CLK 87U
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#define NXP_S32_PORTE_CLK 88U
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#define NXP_S32_RTC0_CLK 89U
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#define NXP_S32_TRACE_CLK 90U
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_ */
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