drivers: clock_control: clock_control_mcux_syscon: make clock IDs unique
Syscon clock driver previously used a sequence where clock IDs increased sequentially. This had a few disadvantages: - if a new SOC was introduced with more instances of a given IP, the clock ID could not be sequential with the remaining IDs - chance of collisions between clock IDs was relatively high To resolve this, define LPC clock IDs using a bitmask macro. Note that the CTIMER clock IDs are used within SOC clock files to perform clock init, and the macro requires that the clock ID expand to an integer rather than a expression with bitshifts (hence why the macro is not used for these IDs) Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse
Fabio Baltieri
parent
dadbe105f2
commit
81ec61c085
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@ -197,19 +197,19 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(
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#endif /* defined(CONFIG_CAN_MCUX_MCAN) */
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#if defined(CONFIG_COUNTER_MCUX_CTIMER) || defined(CONFIG_PWM_MCUX_CTIMER)
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case (MCUX_CTIMER0_CLK + MCUX_CTIMER_CLK_OFFSET):
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case MCUX_CTIMER0_CLK:
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*rate = CLOCK_GetCTimerClkFreq(0);
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break;
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case (MCUX_CTIMER1_CLK + MCUX_CTIMER_CLK_OFFSET):
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case MCUX_CTIMER1_CLK:
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*rate = CLOCK_GetCTimerClkFreq(1);
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break;
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case (MCUX_CTIMER2_CLK + MCUX_CTIMER_CLK_OFFSET):
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case MCUX_CTIMER2_CLK:
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*rate = CLOCK_GetCTimerClkFreq(2);
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break;
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case (MCUX_CTIMER3_CLK + MCUX_CTIMER_CLK_OFFSET):
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case MCUX_CTIMER3_CLK:
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*rate = CLOCK_GetCTimerClkFreq(3);
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break;
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case (MCUX_CTIMER4_CLK + MCUX_CTIMER_CLK_OFFSET):
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case MCUX_CTIMER4_CLK:
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*rate = CLOCK_GetCTimerClkFreq(4);
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break;
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#endif
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@ -300,7 +300,7 @@ static const struct counter_driver_api mcux_ctimer_driver_api = {
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.base = (CTIMER_Type *)DT_INST_REG_ADDR(id), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
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.clock_subsys = \
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(clock_control_subsys_t)(DT_INST_CLOCKS_CELL(id, name) + MCUX_CTIMER_CLK_OFFSET),\
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(clock_control_subsys_t)(DT_INST_CLOCKS_CELL(id, name)),\
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.mode = DT_INST_PROP(id, mode), \
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.input = DT_INST_PROP(id, input), \
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.prescale = DT_INST_PROP(id, prescale), \
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@ -7,63 +7,70 @@
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_
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#define MCUX_FLEXCOMM0_CLK 0
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#define MCUX_FLEXCOMM1_CLK 1
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#define MCUX_FLEXCOMM2_CLK 2
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#define MCUX_FLEXCOMM3_CLK 3
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#define MCUX_FLEXCOMM4_CLK 4
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#define MCUX_FLEXCOMM5_CLK 5
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#define MCUX_FLEXCOMM6_CLK 6
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#define MCUX_FLEXCOMM7_CLK 7
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#define MCUX_FLEXCOMM8_CLK 8
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#define MCUX_FLEXCOMM9_CLK 9
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#define MCUX_FLEXCOMM10_CLK 10
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#define MCUX_FLEXCOMM11_CLK 11
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#define MCUX_FLEXCOMM12_CLK 12
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#define MCUX_FLEXCOMM13_CLK 13
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#define MCUX_HS_SPI_CLK 14
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#define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK
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#define MCUX_PMIC_I2C_CLK 15
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#define MCUX_HS_SPI1_CLK 16
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/* Note- clock identifiers in this file must be unique,
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* as the driver uses them in a switch case
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*/
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#define MCUX_USDHC1_CLK 20
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#define MCUX_USDHC2_CLK 21
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#define MCUX_CTIMER_CLK_OFFSET 22
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#define MCUX_LPC_CLK_ID(high, low) ((high << 8) | (low))
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/* These IDs are used within SOC macros, and thus cannot be defined
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* using the standard MCUX_LPC_CLK_ID form
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*/
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#define MCUX_CTIMER0_CLK 0
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#define MCUX_CTIMER1_CLK 1
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#define MCUX_CTIMER2_CLK 2
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#define MCUX_CTIMER3_CLK 3
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#define MCUX_CTIMER4_CLK 4
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#define MCUX_MCAN_CLK 27
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#define MCUX_FLEXCOMM0_CLK MCUX_LPC_CLK_ID(0x01, 0x00)
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#define MCUX_FLEXCOMM1_CLK MCUX_LPC_CLK_ID(0x01, 0x01)
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#define MCUX_FLEXCOMM2_CLK MCUX_LPC_CLK_ID(0x01, 0x02)
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#define MCUX_FLEXCOMM3_CLK MCUX_LPC_CLK_ID(0x01, 0x03)
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#define MCUX_FLEXCOMM4_CLK MCUX_LPC_CLK_ID(0x01, 0x04)
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#define MCUX_FLEXCOMM5_CLK MCUX_LPC_CLK_ID(0x01, 0x05)
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#define MCUX_FLEXCOMM6_CLK MCUX_LPC_CLK_ID(0x01, 0x06)
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#define MCUX_FLEXCOMM7_CLK MCUX_LPC_CLK_ID(0x01, 0x07)
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#define MCUX_FLEXCOMM8_CLK MCUX_LPC_CLK_ID(0x01, 0x08)
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#define MCUX_FLEXCOMM9_CLK MCUX_LPC_CLK_ID(0x01, 0x09)
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#define MCUX_FLEXCOMM10_CLK MCUX_LPC_CLK_ID(0x01, 0x0A)
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#define MCUX_FLEXCOMM11_CLK MCUX_LPC_CLK_ID(0x01, 0x0B)
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#define MCUX_FLEXCOMM12_CLK MCUX_LPC_CLK_ID(0x01, 0x0C)
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#define MCUX_FLEXCOMM13_CLK MCUX_LPC_CLK_ID(0x01, 0x0D)
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#define MCUX_HS_SPI_CLK MCUX_LPC_CLK_ID(0x01, 0x0E)
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#define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK
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#define MCUX_PMIC_I2C_CLK MCUX_LPC_CLK_ID(0x01, 0x0F)
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#define MCUX_HS_SPI1_CLK MCUX_LPC_CLK_ID(0x01, 0x10)
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#define MCUX_BUS_CLK 28
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#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00)
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#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01)
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#define MCUX_SDIF_CLK 29
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#define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00)
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#define MCUX_I3C_CLK 30
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#define MCUX_BUS_CLK MCUX_LPC_CLK_ID(0x04, 0x00)
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#define MCUX_MIPI_DSI_DPHY_CLK 31
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#define MCUX_MIPI_DSI_ESC_CLK 32
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#define MCUX_SDIF_CLK MCUX_LPC_CLK_ID(0x05, 0x00)
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#define MCUX_LCDIF_PIXEL_CLK 33
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#define MCUX_I3C_CLK MCUX_LPC_CLK_ID(0x06, 0x00)
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#define MCUX_SCTIMER_CLK 34
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#define MCUX_MIPI_DSI_DPHY_CLK MCUX_LPC_CLK_ID(0x07, 0x00)
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#define MCUX_MIPI_DSI_ESC_CLK MCUX_LPC_CLK_ID(0x07, 0x01)
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#define MCUX_DMIC_CLK 35
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#define MCUX_LCDIF_PIXEL_CLK MCUX_LPC_CLK_ID(0x08, 0x00)
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#define MCUX_FLEXSPI_CLK 36
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#define MCUX_FLEXSPI2_CLK 37
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#define MCUX_SCTIMER_CLK MCUX_LPC_CLK_ID(0x09, 0x00)
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#define MCUX_MRT_CLK 40
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#define MCUX_DMIC_CLK MCUX_LPC_CLK_ID(0x0A, 0x00)
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#define MCUX_PORT0_CLK 41
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#define MCUX_PORT1_CLK 42
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#define MCUX_PORT2_CLK 43
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#define MCUX_PORT3_CLK 44
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#define MCUX_PORT4_CLK 45
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#define MCUX_PORT5_CLK 46
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#define MCUX_FLEXSPI_CLK MCUX_LPC_CLK_ID(0x0A, 0x00)
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#define MCUX_FLEXSPI2_CLK MCUX_LPC_CLK_ID(0x0A, 0x01)
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#define MCUX_MRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x00)
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#define MCUX_PORT0_CLK MCUX_LPC_CLK_ID(0x0C, 0x00)
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#define MCUX_PORT1_CLK MCUX_LPC_CLK_ID(0x0C, 0x01)
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#define MCUX_PORT2_CLK MCUX_LPC_CLK_ID(0x0C, 0x02)
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#define MCUX_PORT3_CLK MCUX_LPC_CLK_ID(0x0C, 0x03)
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#define MCUX_PORT4_CLK MCUX_LPC_CLK_ID(0x0C, 0x04)
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#define MCUX_PORT5_CLK MCUX_LPC_CLK_ID(0x0C, 0x05)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */
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