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clock: mcux_ccm: support uart1/2/3

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Add UART1/2/3 clock support, also update uart4 to read clock root
mux to get clock rate.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2021-02-26 17:07:56 +08:00 committed by David Leach
parent 06b8dc6790
commit 827f472560
1 changed files with 48 additions and 4 deletions
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52
drivers/clock_control/clock_control_mcux_ccm.c
View file

@ -7,6 +7,7 @@
#define DT_DRV_COMPAT nxp_imx_ccm
#include <errno.h>
#include <soc.h>
#include <sys/util.h>
#include <drivers/clock_control.h>
#include <dt-bindings/clock/imx_ccm.h>
#include <fsl_clock.h>
@ -41,6 +42,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
uint32_t *rate)
{
uint32_t clock_name = (uint32_t) sub_system;
uint32_t mux __unused;
switch (clock_name) {
@ -109,11 +111,53 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
#endif
#ifdef CONFIG_UART_MCUX_IUART
case IMX_CCM_UART4_CLK:
*rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
(CLOCK_GetRootPreDivider(kCLOCK_RootUart4)) /
(CLOCK_GetRootPostDivider(kCLOCK_RootUart4)) /
case IMX_CCM_UART1_CLK:
mux = CLOCK_GetRootMux(kCLOCK_RootUart1);
if (mux == 0) {
*rate = MHZ(24);
} else if (mux == 1) {
*rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
(CLOCK_GetRootPreDivider(kCLOCK_RootUart1)) /
(CLOCK_GetRootPostDivider(kCLOCK_RootUart1)) /
10;
}
break;
case IMX_CCM_UART2_CLK:
mux = CLOCK_GetRootMux(kCLOCK_RootUart2);
if (mux == 0) {
*rate = MHZ(24);
} else if (mux == 1) {
*rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
(CLOCK_GetRootPreDivider(kCLOCK_RootUart2)) /
(CLOCK_GetRootPostDivider(kCLOCK_RootUart2)) /
10;
}
break;
case IMX_CCM_UART3_CLK:
mux = CLOCK_GetRootMux(kCLOCK_RootUart3);
if (mux == 0) {
*rate = MHZ(24);
} else if (mux == 1) {
*rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
(CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) /
(CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) /
10;
}
break;
case IMX_CCM_UART4_CLK:
mux = CLOCK_GetRootMux(kCLOCK_RootUart4);
if (mux == 0) {
*rate = MHZ(24);
} else if (mux == 1) {
*rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
(CLOCK_GetRootPreDivider(kCLOCK_RootUart4)) /
(CLOCK_GetRootPostDivider(kCLOCK_RootUart4)) /
10;
}
break;
#endif