drivers: intc: Update drivers to use devicetree Kconfig symbol

Update intc drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.

We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.

Signed-off-by: Kumar Gala <galak@kernel.org>
This commit is contained in:
Kumar Gala 2022-07-22 01:46:51 -05:00 committed by Carles Cufí
parent 611326b667
commit 8423f23b9c
15 changed files with 32 additions and 23 deletions

View file

@ -18,19 +18,22 @@ config ARCV2_INTERRUPT_UNIT
config SWERV_PIC
bool "SweRV EH1 Programmable Interrupt Controller (PIC)"
default y
depends on DT_HAS_SWERV_PIC_ENABLED
help
Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU.
config VEXRISCV_LITEX_IRQ
bool "VexRiscv LiteX Interrupt controller"
depends on SOC_RISCV32_LITEX_VEXRISCV
default y
depends on DT_HAS_VEXRISCV_INTC0_ENABLED
help
IRQ implementation for LiteX VexRiscv
config LEON_IRQMP
bool "GRLIB IRQMP interrupt controller"
default y
depends on SOC_SPARC_LEON
depends on DT_HAS_GAISLER_IRQMP_ENABLED
help
GRLIB IRQMP and IRQAMP

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@ -5,6 +5,8 @@
config CAVS_ICTL
bool "CAVS Interrupt Logic"
default y
depends on DT_HAS_INTEL_CAVS_INTC_ENABLED
depends on MULTI_LEVEL_INTERRUPTS
help
These are 4 in number supporting a max of 32 interrupts each.

View file

@ -1,11 +1,9 @@
# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
# SPDX-License-Identifier: Apache-2.0
DT_COMPAT_NUCLEI_ECLIC = nuclei,eclic
config NUCLEI_ECLIC
bool "Enhanced Core Local Interrupt Controller (ECLIC)"
default $(dt_compat_enabled,$(DT_COMPAT_NUCLEI_ECLIC))
depends on RISCV_HAS_CLIC
default y
depends on DT_HAS_NUCLEI_ECLIC_ENABLED
help
Interrupt controller for Nuclei SoC core.

View file

@ -3,12 +3,16 @@
config DW_ICTL_ACE_V1X
bool "Designware Interrupt Controller for ACE V1X"
default y
depends on DT_HAS_INTEL_ACE_INTC_ENABLED
depends on MULTI_LEVEL_INTERRUPTS
help
Designware Interrupt Controller used by ACE V1X.
menuconfig DW_ICTL
bool "Designware Interrupt Controller"
default y
depends on DT_HAS_SNPS_DESIGNWARE_INTC_ENABLED
depends on MULTI_LEVEL_INTERRUPTS
help
Designware Interrupt Controller can be used as a 2nd level interrupt

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@ -1,12 +1,10 @@
# Copyright (c) 2021 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
DT_COMPAT_GD_GD32_EXTI := gd,gd32-exti
config GD32_EXTI
bool "GD32 Extended Interrupts and Events (EXTI) Controller"
depends on (SOC_FAMILY_GD32 || SOC_SERIES_GD32VF103)
default $(dt_compat_enabled,$(DT_COMPAT_GD_GD32_EXTI))
default y
depends on DT_HAS_GD_GD32_EXTI_ENABLED
help
Enable the GigaDevice GD32 Extended Interrupts and Events (EXTI)
controller driver.

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@ -6,6 +6,7 @@
menuconfig INTEL_VTD_ICTL
bool "Intel VT-D interrupt remapping controller"
default y
depends on DT_HAS_INTEL_VT_D_ENABLED
depends on !BOARD_QEMU_X86_64 && ACPI && X86 && 64BIT && PCIE_MSI_MULTI_VECTOR
select CACHE_MANAGEMENT
help

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@ -2,21 +2,18 @@
# SPDX-License-Identifier: Apache-2.0
config ITE_IT8XXX2_INTC
def_bool $(dt_nodelabel_enabled_with_compat,intc,it8xxx2-intc)
depends on (SOC_IT8XXX2)
def_bool DT_HAS_ITE_IT8XXX2_INTC_ENABLED
depends on DT_HAS_ITE_IT8XXX2_INTC_ENABLED
help
Configures the maximum number of clients allowed per shared
instance of the shared interrupt driver. To conserve RAM set
this value to the lowest practical value.
this software interrupt default set on by device tree.
# Workaround for not being able to have commas in macro arguments
DT_COMPAT_ITE_IT8XXX2_WUC := ite,it8xxx2-wuc
config ITE_IT8XXX2_WUC
bool "ITE it8xxx2 Wakeup controller (WUC) interface"
depends on SOC_IT8XXX2
default $(dt_compat_enabled,$(DT_COMPAT_ITE_IT8XXX2_WUC))
default y
depends on DT_HAS_ITE_IT8XXX2_WUC_ENABLED
help
This option enables the wakeup controller interface for IT8XXX2
family.

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@ -45,6 +45,7 @@ config LOAPIC_SPURIOUS_VECTOR_ID
config IOAPIC
bool "IO-APIC"
default y
depends on DT_HAS_INTEL_IOAPIC_ENABLED
help
This option signifies that the target has an IO-APIC device. This
capability allows IO-APIC-dependent code to be included.

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@ -6,7 +6,7 @@
config NPCX_MIWU
bool "Nuvoton NPCX embedded controller (EC) miwu driver"
default y
depends on SOC_FAMILY_NPCX
depends on DT_HAS_NUVOTON_NPCX_MIWU_ENABLED
help
This option enables the Multi-Input Wake-Up Unit (MIWU) driver
for NPCX family of processors.

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@ -4,7 +4,7 @@
config PLIC
bool "Platform Level Interrupt Controller (PLIC)"
default y
depends on RISCV_HAS_PLIC
depends on DT_HAS_SIFIVE_PLIC_1_0_0_ENABLED
select MULTI_LEVEL_INTERRUPTS
select 2ND_LEVEL_INTERRUPTS
help

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@ -5,7 +5,9 @@
config RV32M1_INTMUX
bool "OpenISA RV32M1 INTMUX interrupt controller support"
depends on SOC_OPENISA_RV32M1_RISCV32 && MULTI_LEVEL_INTERRUPTS
default y
depends on DT_HAS_OPENISA_RV32M1_INTMUX_ENABLED
depends on MULTI_LEVEL_INTERRUPTS
help
Select this option to enable support for the RV32M1 INTMUX
driver. This provides a level 2 interrupt controller for the SoC.

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@ -6,7 +6,7 @@
config SAM0_EIC
bool "External Interrupt Controller (EIC) Driver for SAM0 series devices"
default y
depends on SOC_FAMILY_SAM0
depends on DT_HAS_ATMEL_SAM0_EIC_ENABLED
help
Enable EIC driver for SAM0 series of devices. This is required for
GPIO interrupt support.

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@ -5,6 +5,8 @@
menuconfig SHARED_IRQ
bool "Shared interrupt driver"
default y
depends on DT_HAS_SHARED_IRQ_ENABLED
help
Include shared interrupt support in system. Shared interrupt
support is NOT required in most systems. If in doubt answer no.

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@ -7,7 +7,8 @@ if SOC_FAMILY_STM32
config EXTI_STM32
bool "External Interrupt/Event Controller (EXTI) Driver for STM32 family of MCUs"
default y if SOC_FAMILY_STM32
default y
depends on DT_HAS_ST_STM32_EXTI_ENABLED
help
Enable EXTI driver for STM32 line of MCUs

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@ -6,6 +6,6 @@
config MCHP_ECIA_XEC
bool "External EC Interrupt Aggregator (ECIA) Driver for MCHP MEC family of MCUs"
default y
depends on SOC_SERIES_MEC172X
depends on DT_HAS_MICROCHIP_XEC_ECIA_ENABLED
help
Enable XEC ECIA driver for Microchip MEC line of MCUs