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dts: arm: st: Factorize STM32L4 series soc dtsi files

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In order to simplify maintenance of dts files for
stm32f4 series, introduce a stm32l4.dtsi file which
represent the smallest common denominator of IPs in
the family.
This allows to fix usart4 availability on stm32l432
which was not correct.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-07-24 15:44:26 +02:00 committed by Kumar Gala
parent 9f88663079
commit 84fce262f9
3 changed files with 86 additions and 150 deletions
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84
dts/arm/st/stm32l4.dtsi Normal file
View file

@ -0,0 +1,84 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
#include <dt-bindings/clock/stm32_clock.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
flash0: flash@8000000 {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
rcc: rcc@40021000 {
compatible = "st,stm32-rcc";
clocks-controller;
#clocks-cells = <2>;
reg = <0x40021000 0x400>;
label = "STM32_CLK_RCC";
};
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
interrupts = <37 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <38 0>;
status = "disabled";
label = "UART_2";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_1";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};

77
dts/arm/st/stm32l432.dtsi
View file

@ -4,79 +4,4 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
#include <dt-bindings/clock/stm32_clock.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
flash0: flash@8000000 {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
rcc: rcc@40021000 {
compatible = "st,stm32-rcc";
clocks-controller;
#clocks-cells = <2>;
reg = <0x40021000 0x400>;
label = "STM32_CLK_RCC";
};
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
interrupts = <37 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <38 0>;
status = "disabled";
label = "UART_2";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
uart4: serial@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
#include <st/stm32l4.dtsi>

75
dts/arm/st/stm32l475.dtsi
View file

@ -4,68 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
#include <dt-bindings/clock/stm32_clock.h>
#include <st/stm32l4.dtsi>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
flash0: flash@8000000 {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
rcc: rcc@40021000 {
compatible = "st,stm32-rcc";
clocks-controller;
#clocks-cells = <2>;
reg = <0x40021000 0x400>;
label = "STM32_CLK_RCC";
};
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
interrupts = <37 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <38 0>;
status = "disabled";
label = "UART_2";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
uart4: serial@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
@ -84,17 +26,6 @@
label = "UART_5";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v2";
#address-cells = <1>;
@ -118,7 +49,3 @@
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};