clock_control: stm32: Add support for MSI PLL MODE
Add support for Low Speed External 32.768 kHz oscillator (LSE ). Add support for MSI PLL-Mode offering an automatic calibration feature in combination with the LSE. This allows the MSI to reach an accurate +/-0,25% clock perfectly suitable for USB full-speed clock. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
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@ -366,6 +366,20 @@ config CLOCK_STM32_PLL_R_DIVISOR
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help
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PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.
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config CLOCK_STM32_LSE
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bool "Low-speed external clock"
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default n
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help
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Enable the low-speed external (LSE) clock supplied with a 32.768 kHz
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crystal resonator oscillator.
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config CLOCK_STM32_MSI_PLL_MODE
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bool "MSI PLL MODE"
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depends on CLOCK_STM32_LSE
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default n
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help
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Enable hardware auto-calibration with LSE.
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endif # SOC_SERIES_STM32L4X
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config CLOCK_STM32_AHB_PRESCALER
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@ -363,6 +363,10 @@ static int stm32_clock_control_init(struct device *dev)
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while (LL_RCC_MSI_IsReady() != 1) {
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/* Wait for HSI ready */
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}
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#ifdef CONFIG_CLOCK_STM32_MSI_PLL_MODE
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/* Enable MSI hardware auto calibration */
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LL_RCC_MSI_EnablePLLMode();
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#endif
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}
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/* Set MSI as SYSCLCK source */
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@ -39,5 +39,24 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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*/
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void config_enable_default_clocks(void)
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{
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/* Nothing for now */
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#ifdef CONFIG_CLOCK_STM32_LSE
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/* LSE belongs to the back-up domain, enable access.*/
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/* Enable the power interface clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
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LL_PWR_EnableBkUpAccess();
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while (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Wait for Backup domain access */
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}
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/* Enable LSE Oscillator (32.768 kHz) */
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LL_RCC_LSE_Enable();
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while (!LL_RCC_LSE_IsReady()) {
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/* Wait for LSE ready */
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}
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LL_PWR_DisableBkUpAccess();
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#endif
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}
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@ -44,6 +44,7 @@
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#include <stm32l4xx_ll_bus.h>
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#include <stm32l4xx_ll_rcc.h>
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#include <stm32l4xx_ll_system.h>
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#include <stm32l4xx_ll_pwr.h>
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#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
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#ifdef CONFIG_SPI_STM32
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