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drivers: spi: spi_ll_stm32: Add support for STM32H7xx SoC

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Add SPI driver support for STM32H7xx SoC.

Signed-off-by: Harry Jiang <explora26@gmail.com>
This commit is contained in:
Harry Jiang 2020-07-31 09:28:36 +08:00 committed by Carles Cufí
parent d0058d92db
commit 85e0e21390
3 changed files with 35 additions and 16 deletions
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11
drivers/spi/spi_ll_stm32.c
View file

@ -37,7 +37,8 @@ LOG_MODULE_REGISTER(spi_ll_stm32);
* error flag, because STM32F1 SoCs do not support it and STM32CUBE
* for F1 family defines an unused LL_SPI_SR_FRE.
*/
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
#define SPI_STM32_ERR_MSK (LL_SPI_SR_UDR | LL_SPI_SR_CRCE | LL_SPI_SR_MODF | \
LL_SPI_SR_OVR | LL_SPI_SR_TIFRE)
#else
@ -262,9 +263,11 @@ static void spi_stm32_shift_m(SPI_TypeDef *spi, struct spi_stm32_data *data)
/* NOP */
}
#ifdef CONFIG_SOC_SERIES_STM32MP1X
/* With the STM32MP1, if the device is the SPI master, we need to enable
* the start of the transfer with LL_SPI_StartMasterTransfer(spi)
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
/* With the STM32MP1 and the STM32H7, if the device is the SPI master,
* we need to enable the start of the transfer with
* LL_SPI_StartMasterTransfer(spi)
*/
if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
LL_SPI_StartMasterTransfer(spi);

36
drivers/spi/spi_ll_stm32.h
View file

@ -54,7 +54,8 @@ struct spi_stm32_data {
static inline uint32_t ll_func_tx_is_empty(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
return LL_SPI_IsActiveFlag_TXP(spi);
#else
return LL_SPI_IsActiveFlag_TXE(spi);
@ -63,7 +64,8 @@ static inline uint32_t ll_func_tx_is_empty(SPI_TypeDef *spi)
static inline uint32_t ll_func_rx_is_not_empty(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
return LL_SPI_IsActiveFlag_RXP(spi);
#else
return LL_SPI_IsActiveFlag_RXNE(spi);
@ -72,7 +74,8 @@ static inline uint32_t ll_func_rx_is_not_empty(SPI_TypeDef *spi)
static inline void ll_func_enable_int_tx_empty(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
LL_SPI_EnableIT_TXP(spi);
#else
LL_SPI_EnableIT_TXE(spi);
@ -81,7 +84,8 @@ static inline void ll_func_enable_int_tx_empty(SPI_TypeDef *spi)
static inline void ll_func_enable_int_rx_not_empty(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
LL_SPI_EnableIT_RXP(spi);
#else
LL_SPI_EnableIT_RXNE(spi);
@ -90,7 +94,8 @@ static inline void ll_func_enable_int_rx_not_empty(SPI_TypeDef *spi)
static inline void ll_func_enable_int_errors(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
LL_SPI_EnableIT_UDR(spi);
LL_SPI_EnableIT_OVR(spi);
LL_SPI_EnableIT_CRCERR(spi);
@ -103,7 +108,8 @@ static inline void ll_func_enable_int_errors(SPI_TypeDef *spi)
static inline void ll_func_disable_int_tx_empty(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
LL_SPI_DisableIT_TXP(spi);
#else
LL_SPI_DisableIT_TXE(spi);
@ -112,7 +118,8 @@ static inline void ll_func_disable_int_tx_empty(SPI_TypeDef *spi)
static inline void ll_func_disable_int_rx_not_empty(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
LL_SPI_DisableIT_RXP(spi);
#else
LL_SPI_DisableIT_RXNE(spi);
@ -121,7 +128,8 @@ static inline void ll_func_disable_int_rx_not_empty(SPI_TypeDef *spi)
static inline void ll_func_disable_int_errors(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
LL_SPI_DisableIT_UDR(spi);
LL_SPI_DisableIT_OVR(spi);
LL_SPI_DisableIT_CRCERR(spi);
@ -134,7 +142,8 @@ static inline void ll_func_disable_int_errors(SPI_TypeDef *spi)
static inline uint32_t ll_func_spi_is_busy(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
return (!LL_SPI_IsActiveFlag_MODF(spi) &&
!LL_SPI_IsActiveFlag_TXC(spi));
#else
@ -148,7 +157,8 @@ static inline uint32_t ll_func_spi_is_busy(SPI_TypeDef *spi)
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_spi_fifo)
static inline void ll_func_set_fifo_threshold_8bit(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
LL_SPI_SetFIFOThreshold(spi, LL_SPI_FIFO_TH_01DATA);
#else
LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER);
@ -157,7 +167,8 @@ static inline void ll_func_set_fifo_threshold_8bit(SPI_TypeDef *spi)
static inline void ll_func_set_fifo_threshold_16bit(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
LL_SPI_SetFIFOThreshold(spi, LL_SPI_FIFO_TH_02DATA);
#else
LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_HALF);
@ -167,7 +178,8 @@ static inline void ll_func_set_fifo_threshold_16bit(SPI_TypeDef *spi)
static inline void ll_func_disable_spi(SPI_TypeDef *spi)
{
#ifdef CONFIG_SOC_SERIES_STM32MP1X
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
if (LL_SPI_IsActiveMasterTransfer(spi)) {
LL_SPI_SuspendMasterTransfer(spi);
while (LL_SPI_IsActiveMasterTransfer(spi)) {

4
soc/arm/st_stm32/stm32h7/soc.h
View file

@ -68,6 +68,10 @@
#include <stm32h7xx_ll_i2c.h>
#endif /* CONFIG_I2C_STM32 */
#ifdef CONFIG_SPI_STM32
#include <stm32h7xx_ll_spi.h>
#endif /* CONFIG_SPI_STM32 */
#ifdef CONFIG_ADC_STM32
#include <stm32h7xx_ll_adc.h>
#endif /* CONFIG_ADC_STM32 */