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drivers: ethernet: xlnx_gem: fix PHY_MRVL_MODE_CONFIG_MASK

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According to the datasheet for Marvell PHY [1], the mode field of the
General Control Register 1 Page 18 occupies bits [2:0]. However, the macro
PHY_MRVL_MODE_CONFIG_MASK specifies the mask as 0x3, which would
correspond only to [1:0]. The code in phy_xlnx_gem_marvell_alaska_cfg()
uses the mask to set the mode field to 0 to set "RGMII (System mode) to
Copper" mode. Unfortunately, different chips have different reset values
(111 or 000) and in first case, the code would set the field to 100,
instead of 000.

Without this change, ethernet on Avnet MicroZed (Marvel Alaska 88E1512 PHY)
does not work.

Signed-off-by: Marek Vedral <vedrama5@fel.cvut.cz>

[1]: https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-ethernet-phys-alaska-88e151x-datasheet.pdf
This commit is contained in:
Marek Vedral 2023-03-30 12:38:34 +02:00 committed by Carles Cufí
parent 1bcffb2a45
commit 86842dbab5
1 changed files with 1 additions and 1 deletions
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2
drivers/ethernet/phy_xlnx_gem.h
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@ -59,7 +59,7 @@
#define PHY_MRVL_MDIX_CONFIG_MASK 0x0003
#define PHY_MRVL_MDIX_CONFIG_SHIFT 5
#define PHY_MRVL_MDIX_AUTO_CROSSOVER_ENABLE 0x0003
#define PHY_MRVL_MODE_CONFIG_MASK 0x0003
#define PHY_MRVL_MODE_CONFIG_MASK 0x0007
#define PHY_MRVL_MODE_CONFIG_SHIFT 0
#define PHY_MRVL_COPPER_SPEED_CHANGED_INT_BIT (1 << 14)