drivers: pwm_nrf5_sw: Rename to pwm_nrf_sw
Since the driver can now be also used on nRF91 Series, its name need to be updated to not cause confusion. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
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8c1c666bab
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88ab153ac4
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@ -8,7 +8,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_TELINK_B91 pwm_b91.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_CC13XX_CC26XX_TIMER pwm_cc13xx_cc26xx_timer.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_CC13XX_CC26XX_TIMER pwm_cc13xx_cc26xx_timer.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_STM32 pwm_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_STM32 pwm_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SIFIVE pwm_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SIFIVE pwm_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NRF5_SW pwm_nrf5_sw.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NRF_SW pwm_nrf_sw.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NRFX pwm_nrfx.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NRFX pwm_nrfx.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_FTM pwm_mcux_ftm.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_FTM pwm_mcux_ftm.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_IMX pwm_imx.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_IMX pwm_imx.c)
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@ -41,7 +41,7 @@ source "drivers/pwm/Kconfig.stm32"
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source "drivers/pwm/Kconfig.sifive"
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source "drivers/pwm/Kconfig.sifive"
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source "drivers/pwm/Kconfig.nrf5_sw"
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source "drivers/pwm/Kconfig.nrf_sw"
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source "drivers/pwm/Kconfig.nrfx"
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source "drivers/pwm/Kconfig.nrfx"
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@ -1,20 +0,0 @@
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# Nordic Semiconductor nRF5x s/w PWM configuration options
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# Copyright (c) 2017 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config PWM_NRF5_SW
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bool "Nordic Semiconductor nRF5x series S/W PWM"
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default y if !PWM_NRFX
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depends on DT_HAS_NORDIC_NRF_SW_PWM_ENABLED
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select NRFX_GPIOTE
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select NRFX_PPI if HAS_HW_NRF_PPI
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select NRFX_DPPI if HAS_HW_NRF_DPPIC
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help
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Enable driver to utilize PWM on the Nordic Semiconductor nRF5x series.
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When used with HF timer it provides up to 3 pins, utilizing two PPI
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channels per pin and one GPIOTE config per pin.
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When used with RTC it provides up to 3 pins, utilizing three PPI
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channels per pin and one GPIOTE config per pin.
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21
drivers/pwm/Kconfig.nrf_sw
Normal file
21
drivers/pwm/Kconfig.nrf_sw
Normal file
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@ -0,0 +1,21 @@
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# Nordic Semiconductor nRF5x s/w PWM configuration options
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# Copyright (c) 2017 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config PWM_NRF_SW
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bool "Nordic Semiconductor nRF family S/W PWM"
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default y if !PWM_NRFX
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depends on DT_HAS_NORDIC_NRF_SW_PWM_ENABLED
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select NRFX_GPIOTE
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select NRFX_PPI if HAS_HW_NRF_PPI
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select NRFX_DPPI if HAS_HW_NRF_DPPIC
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help
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Enable driver to utilize PWM on the Nordic Semiconductor nRF SoCs.
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When used with HF timer, it provides up to 5 pins, utilizing one
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GPIOTE channel and two PPI/DPPI channels and per pin.
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When used with RTC, it provides up to 3 pins, utilizing one GPIOTE
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channel and two or three (when the fork feature is not available)
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PPI/DPPI channels per pin.
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@ -17,7 +17,7 @@
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#include <zephyr/logging/log.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(pwm_nrf5_sw, CONFIG_PWM_LOG_LEVEL);
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LOG_MODULE_REGISTER(pwm_nrf_sw, CONFIG_PWM_LOG_LEVEL);
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#define GENERATOR_NODE DT_INST_PHANDLE(0, generator)
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#define GENERATOR_NODE DT_INST_PHANDLE(0, generator)
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#define GENERATOR_CC_NUM DT_PROP(GENERATOR_NODE, cc_num)
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#define GENERATOR_CC_NUM DT_PROP(GENERATOR_NODE, cc_num)
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@ -116,9 +116,9 @@ static uint32_t pwm_period_check(struct pwm_data *data, uint8_t map_size,
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return 0;
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return 0;
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}
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}
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static int pwm_nrf5_sw_set_cycles(const struct device *dev, uint32_t channel,
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static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel,
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uint32_t period_cycles, uint32_t pulse_cycles,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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pwm_flags_t flags)
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{
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{
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const struct pwm_config *config = dev->config;
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const struct pwm_config *config = dev->config;
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NRF_TIMER_Type *timer = pwm_config_timer(config);
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NRF_TIMER_Type *timer = pwm_config_timer(config);
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@ -273,7 +273,7 @@ static int pwm_nrf5_sw_set_cycles(const struct device *dev, uint32_t channel,
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#if PPI_FORK_AVAILABLE
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#if PPI_FORK_AVAILABLE
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nrfx_gppi_fork_endpoint_setup(ppi_chs[1],
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nrfx_gppi_fork_endpoint_setup(ppi_chs[1],
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clear_task_addr);
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clear_task_address);
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#else
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#else
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nrfx_gppi_channel_endpoints_setup(ppi_chs[2],
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nrfx_gppi_channel_endpoints_setup(ppi_chs[2],
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period_end_event_address,
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period_end_event_address,
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@ -310,8 +310,8 @@ static int pwm_nrf5_sw_set_cycles(const struct device *dev, uint32_t channel,
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return 0;
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return 0;
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}
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}
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static int pwm_nrf5_sw_get_cycles_per_sec(const struct device *dev,
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static int pwm_nrf_sw_get_cycles_per_sec(const struct device *dev,
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uint32_t channel, uint64_t *cycles)
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uint32_t channel, uint64_t *cycles)
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{
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{
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const struct pwm_config *config = dev->config;
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const struct pwm_config *config = dev->config;
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@ -332,12 +332,12 @@ static int pwm_nrf5_sw_get_cycles_per_sec(const struct device *dev,
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return 0;
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return 0;
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}
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}
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static const struct pwm_driver_api pwm_nrf5_sw_drv_api_funcs = {
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static const struct pwm_driver_api pwm_nrf_sw_drv_api_funcs = {
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.set_cycles = pwm_nrf5_sw_set_cycles,
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.set_cycles = pwm_nrf_sw_set_cycles,
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.get_cycles_per_sec = pwm_nrf5_sw_get_cycles_per_sec,
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.get_cycles_per_sec = pwm_nrf_sw_get_cycles_per_sec,
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};
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};
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static int pwm_nrf5_sw_init(const struct device *dev)
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static int pwm_nrf_sw_init(const struct device *dev)
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{
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{
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const struct pwm_config *config = dev->config;
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const struct pwm_config *config = dev->config;
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struct pwm_data *data = dev->data;
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struct pwm_data *data = dev->data;
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@ -402,7 +402,7 @@ static int pwm_nrf5_sw_init(const struct device *dev)
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((DT_GPIO_FLAGS_BY_IDX(_node_id, _prop, _idx) & GPIO_ACTIVE_LOW) \
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((DT_GPIO_FLAGS_BY_IDX(_node_id, _prop, _idx) & GPIO_ACTIVE_LOW) \
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? BIT(_idx) : 0) |
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? BIT(_idx) : 0) |
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static const struct pwm_config pwm_nrf5_sw_0_config = {
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static const struct pwm_config pwm_nrf_sw_0_config = {
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COND_CODE_1(USE_RTC, (.rtc), (.timer)) = GENERATOR_ADDR,
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COND_CODE_1(USE_RTC, (.rtc), (.timer)) = GENERATOR_ADDR,
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.psel_ch = {
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.psel_ch = {
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DT_INST_FOREACH_PROP_ELEM(0, channel_gpios, PSEL_AND_COMMA)
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DT_INST_FOREACH_PROP_ELEM(0, channel_gpios, PSEL_AND_COMMA)
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@ -413,13 +413,13 @@ static const struct pwm_config pwm_nrf5_sw_0_config = {
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.prescaler = DT_INST_PROP(0, clock_prescaler),
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.prescaler = DT_INST_PROP(0, clock_prescaler),
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};
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};
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static struct pwm_data pwm_nrf5_sw_0_data;
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static struct pwm_data pwm_nrf_sw_0_data;
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DEVICE_DT_INST_DEFINE(0,
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DEVICE_DT_INST_DEFINE(0,
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pwm_nrf5_sw_init,
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pwm_nrf_sw_init,
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NULL,
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NULL,
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&pwm_nrf5_sw_0_data,
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&pwm_nrf_sw_0_data,
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&pwm_nrf5_sw_0_config,
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&pwm_nrf_sw_0_config,
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POST_KERNEL,
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POST_KERNEL,
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CONFIG_PWM_INIT_PRIORITY,
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CONFIG_PWM_INIT_PRIORITY,
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&pwm_nrf5_sw_drv_api_funcs);
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&pwm_nrf_sw_drv_api_funcs);
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@ -5,7 +5,7 @@ CONFIG_GPIO=y
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CONFIG_DISPLAY=y
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CONFIG_DISPLAY=y
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CONFIG_MICROBIT_DISPLAY=y
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CONFIG_MICROBIT_DISPLAY=y
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CONFIG_PWM=y
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CONFIG_PWM=y
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CONFIG_PWM_NRF5_SW=y
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CONFIG_PWM_NRF_SW=y
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CONFIG_BT_RX_STACK_SIZE=1280
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CONFIG_BT_RX_STACK_SIZE=1280
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CONFIG_BT_CTLR_DUP_FILTER_LEN=0
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CONFIG_BT_CTLR_DUP_FILTER_LEN=0
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@ -8,7 +8,7 @@ CONFIG_GPIO=y
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CONFIG_DISPLAY=y
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CONFIG_DISPLAY=y
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CONFIG_MICROBIT_DISPLAY=y
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CONFIG_MICROBIT_DISPLAY=y
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CONFIG_PWM=y
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CONFIG_PWM=y
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CONFIG_PWM_NRF5_SW=y
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CONFIG_PWM_NRF_SW=y
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# This feature isn't needed as this sample is intended to be used
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# This feature isn't needed as this sample is intended to be used
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# between zephyr devices only.
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# between zephyr devices only.
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@ -2,4 +2,4 @@ CONFIG_GPIO=y
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CONFIG_DISPLAY=y
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CONFIG_DISPLAY=y
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CONFIG_MICROBIT_DISPLAY=y
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CONFIG_MICROBIT_DISPLAY=y
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CONFIG_PWM=y
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CONFIG_PWM=y
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CONFIG_PWM_NRF5_SW=y
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CONFIG_PWM_NRF_SW=y
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