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drivers: interrupt_controller: Add gicv3 SGI api

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Add api to raise SGI to target cores in affinity level identified
by MPIDR. Currently only EL1S is supported.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
This commit is contained in:
Sandeep Tripathy 2020-06-12 17:31:09 +05:30 committed by Anas Nashif
parent 500451ad67
commit 8aa0248acd
3 changed files with 61 additions and 0 deletions
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21
drivers/interrupt_controller/intc_gicv3.c
View file

@ -123,6 +123,27 @@ void arm_gic_eoi(unsigned int intid)
write_sysreg(intid, ICC_EOIR1_EL1);
}
void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
uint16_t target_list)
{
uint32_t aff3, aff2, aff1;
uint64_t sgi_val;
assert(GIC_IS_SGI(sgi_id));
/* Extract affinity fields from target */
aff1 = MPIDR_AFFLVL(target_aff, 1);
aff2 = MPIDR_AFFLVL(target_aff, 2);
aff3 = MPIDR_AFFLVL(target_aff, 3);
sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id,
SGIR_IRM_TO_AFF, target_list);
__DSB();
write_sysreg(sgi_val, ICC_SGI1R);
__ISB();
}
/*
* Wake up GIC redistributor.
* clear ProcessorSleep and wait till ChildAsleep is cleared.

21
include/arch/arm/aarch64/cpu.h
View file

@ -92,6 +92,27 @@
#define ICC_SRE_ELx_DIB BIT(2)
#define ICC_SRE_EL3_EN BIT(3)
/* ICC SGI macros */
#define SGIR_TGT_MASK 0xffff
#define SGIR_AFF1_SHIFT 16
#define SGIR_INTID_SHIFT 24
#define SGIR_INTID_MASK 0xf
#define SGIR_AFF2_SHIFT 32
#define SGIR_IRM_SHIFT 40
#define SGIR_IRM_MASK 0x1
#define SGIR_AFF3_SHIFT 48
#define SGIR_AFF_MASK 0xf
#define SGIR_IRM_TO_AFF 0
#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
(((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
(((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
(((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
(((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
((_tgt) & SGIR_TGT_MASK))
/* Implementation defined register definations */
#if defined(CONFIG_CPU_CORTEX_A72)

19
include/drivers/interrupt_controller/gic.h
View file

@ -210,6 +210,19 @@
#endif /* CONFIG_GIC_VER <= 2 */
#if defined(CONFIG_GIC_V3)
/**
* @brief raise SGI to target cores
*
* @param sgi_id SGI ID 0 to 15
* @param target_aff target affinity in mpidr form.
* Aff level 1 2 3 will be extracted by api.
* @param target_list bitmask of target cores
*/
void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
uint16_t target_list);
#endif
/* GICD_ICFGR */
#define GICD_ICFGR_MASK BIT_MASK(2)
#define GICD_ICFGR_TYPE BIT(1)
@ -220,6 +233,12 @@
/*
* Common Helper Constants
*/
#define GIC_SGI_INT_BASE 0
#define GIC_PPI_INT_BASE 16
#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \
((intid) < GIC_PPI_INT_BASE))
#define GIC_SPI_INT_BASE 32