patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 8 Packages Projects Releases Wiki Activity

clock_control: stm32: code optimization

Browse source 
This commit brings code size optimization as suggested by Christer
Weinigel review during review of initial commit for this driver.
It also cleans up useless definition in header file.

Change-Id: Ibeaa2e51570dff21825c60c30ba83d939b31d938
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-01-30 15:38:13 +01:00 committed by Maureen Helm
parent 726d4dc437
commit 8ab42c92ce
3 changed files with 14 additions and 104 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

70
drivers/clock_control/stm32_ll_clock.c
View file

@ -12,71 +12,15 @@
#include <clock_control/stm32_clock_control.h>
#include "stm32_ll_clock.h"
/**
* @brief helper for mapping a setting to register value
*/
uint32_t map_reg_val(const struct regval_map *map, size_t cnt, int val)
{
for (int i = 0; i < cnt; i++) {
if (map[i].val == val) {
return map[i].reg;
}
}
/* Macros to fill up prescaler values */
#define _ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
#define ahb_prescaler(v) _ahb_prescaler(v)
return 0;
}
#define _apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
#define apb1_prescaler(v) _apb1_prescaler(v)
/**
* @brief map AHB prescaler setting to register value
*/
static uint32_t ahb_prescaler(int prescaler)
{
const struct regval_map ahb_map[] = {
{1, LL_RCC_SYSCLK_DIV_1},
{2, LL_RCC_SYSCLK_DIV_2},
{4, LL_RCC_SYSCLK_DIV_4},
{8, LL_RCC_SYSCLK_DIV_8},
{16, LL_RCC_SYSCLK_DIV_16},
{64, LL_RCC_SYSCLK_DIV_64},
{128, LL_RCC_SYSCLK_DIV_128},
{256, LL_RCC_SYSCLK_DIV_256},
{512, LL_RCC_SYSCLK_DIV_512},
};
return map_reg_val(ahb_map, ARRAY_SIZE(ahb_map), prescaler);
}
/**
* @brief map APB1 prescaler setting to register value
*/
static uint32_t apb1_prescaler(int prescaler)
{
const struct regval_map apb1_map[] = {
{1, LL_RCC_APB1_DIV_1},
{2, LL_RCC_APB1_DIV_2},
{4, LL_RCC_APB1_DIV_4},
{8, LL_RCC_APB1_DIV_8},
{16, LL_RCC_APB1_DIV_16},
};
return map_reg_val(apb1_map, ARRAY_SIZE(apb1_map), prescaler);
}
/**
* @brief map APB2 prescaler setting to register value
*/
static uint32_t apb2_prescaler(int prescaler)
{
const struct regval_map apb2_map[] = {
{1, LL_RCC_APB2_DIV_1},
{2, LL_RCC_APB2_DIV_2},
{4, LL_RCC_APB2_DIV_4},
{8, LL_RCC_APB2_DIV_8},
{16, LL_RCC_APB2_DIV_16},
};
return map_reg_val(apb2_map, ARRAY_SIZE(apb2_map), prescaler);
}
#define _apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
#define apb2_prescaler(v) _apb2_prescaler(v)
/**
* @brief fill in AHB/APB buses configuration structure

11
drivers/clock_control/stm32_ll_clock.h
View file

@ -10,14 +10,7 @@
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit);
struct regval_map {
int val;
uint32_t reg;
};
uint32_t map_reg_val(const struct regval_map *map, size_t cnt, int val);
/* */
void LL_AHB2_GRP1_EnableClock(uint32_t Periphs);
/* Section for functions not available in every Cube packages */
void LL_RCC_MSI_Disable(void);
#endif /* _STM32_LL_CLOCK_H_ */

37
drivers/clock_control/stm32l4x_ll_clock.c
View file

@ -16,39 +16,12 @@
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
/**
* @brief map PLLM setting to register value
*/
static uint32_t pllm(int prescaler)
{
const struct regval_map map[] = {
{1, LL_RCC_PLLM_DIV_1},
{2, LL_RCC_PLLM_DIV_2},
{3, LL_RCC_PLLM_DIV_3},
{4, LL_RCC_PLLM_DIV_4},
{5, LL_RCC_PLLM_DIV_5},
{6, LL_RCC_PLLM_DIV_6},
{7, LL_RCC_PLLM_DIV_7},
{8, LL_RCC_PLLM_DIV_8},
};
/* Macros to fill up division factors values */
#define _pllm(v) LL_RCC_PLLM_DIV_ ## v
#define pllm(v) _pllm(v)
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
}
/**
* @brief map PLLR setting to register value
*/
static uint32_t pllr(int prescaler)
{
const struct regval_map map[] = {
{2, LL_RCC_PLLR_DIV_2},
{4, LL_RCC_PLLR_DIV_4},
{6, LL_RCC_PLLR_DIV_6},
{8, LL_RCC_PLLR_DIV_8},
};
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
}
#define _pllr(v) LL_RCC_PLLR_DIV_ ## v
#define pllr(v) _pllr(v)
/**
* @brief fill in pll configuration structure