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soc: arm: aspeed: enable cache for AST10x0 series SOC

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Enable cache for AST10x0 series SOC in platform initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
This commit is contained in:
Dylan Hung 2022-05-13 15:29:38 +08:00 committed by Carles Cufí
parent 1c3810ded2
commit 8b7ec919c8
1 changed files with 2 additions and 0 deletions
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2
soc/arm/aspeed/ast10x0/soc.c
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@ -98,6 +98,8 @@ void z_arm_platform_init(void)
if (CONFIG_SRAM_NC_SIZE > 0) {
(void)memset(__bss_nc_start__, 0, __bss_nc_end__ - __bss_nc_start__);
}
cache_instr_enable();
}
void aspeed_print_abr_wdt_mode(void)