drivers: flash: stm32: add a weak flash_stm32_valid_range()
Most implementations have the same logic, with only a different write block size. Now that we are using write-block-size from the device tree, it is possible to use a default implementation that can be overridden if necessary. Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
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@ -45,6 +45,15 @@ static const struct flash_parameters flash_stm32_parameters = {
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static int flash_stm32_write_protection(const struct device *dev, bool enable);
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bool __weak flash_stm32_valid_range(const struct device *dev, off_t offset,
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uint32_t len, bool write)
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{
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if (write && !flash_stm32_valid_write(offset, len)) {
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return false;
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}
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return flash_stm32_range_exists(dev, offset, len);
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}
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int __weak flash_stm32_check_configuration(void)
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{
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return 0;
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@ -163,17 +163,6 @@ static int write_value(const struct device *dev, off_t offset,
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return rc;
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}
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/* offset and len must be aligned on 2 for write
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* positive and not beyond end of flash
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*/
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bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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uint32_t len,
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bool write)
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{
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return (!write || (offset % 2 == 0 && len % 2 == 0U)) &&
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flash_stm32_range_exists(dev, offset, len);
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}
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int flash_stm32_block_erase_loop(const struct device *dev,
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unsigned int offset,
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unsigned int len)
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@ -40,20 +40,6 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
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#define STM32G0_PAGES_PER_BANK \
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((STM32G0_FLASH_SIZE / STM32G0_FLASH_PAGE_SIZE) / STM32G0_BANK_COUNT)
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/*
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* offset and len must be aligned on 8 for write,
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* positive and not beyond end of flash
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* On dual-bank SoCs memory accesses starting on the first bank and continuing
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* beyond the first bank into the second bank are allowed.
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*/
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bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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uint32_t len,
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bool write)
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{
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return (!write || (offset % 8 == 0 && len % 8 == 0)) &&
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flash_stm32_range_exists(dev, offset, len);
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}
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static inline void flush_cache(FLASH_TypeDef *regs)
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{
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if (regs->ACR & FLASH_ACR_ICEN) {
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@ -42,8 +42,10 @@ bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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}
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#endif
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return (!write || (offset % 8 == 0 && len % 8 == 0U)) &&
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flash_stm32_range_exists(dev, offset, len);
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if (write && !flash_stm32_valid_write(offset, len)) {
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return false;
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}
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return flash_stm32_range_exists(dev, offset, len);
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}
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static inline void flush_cache(FLASH_TypeDef *regs)
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@ -32,16 +32,6 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
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#define CONTROL_DCACHE
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#endif
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/* offset and len must be aligned on 8 for write
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* , positive and not beyond end of flash */
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bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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uint32_t len,
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bool write)
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{
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return (!write || (offset % 8 == 0 && len % 8 == 0U)) &&
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flash_stm32_range_exists(dev, offset, len);
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}
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static inline void flush_cache(FLASH_TypeDef *regs)
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{
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if (regs->ACR & FLASH_ACR_DCEN) {
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@ -105,18 +105,6 @@ static int icache_wait_for_invalidate_complete(void)
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return status;
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}
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/*
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* offset and len must be aligned on 16 for write,
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* positive and not beyond end of flash
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*/
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bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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uint32_t len,
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bool write)
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{
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return (!write || (offset % 16 == 0 && len % 16 == 0U)) &&
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flash_stm32_range_exists(dev, offset, len);
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}
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static int write_qword(const struct device *dev, off_t offset, const uint32_t *buff)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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@ -26,17 +26,6 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
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#define STM32WBX_PAGE_SHIFT 12
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/* offset and len must be aligned on 8 for write,
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* positive and not beyond end of flash
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*/
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bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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uint32_t len,
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bool write)
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{
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return (!write || (offset % 8 == 0 && len % 8 == 0U)) &&
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flash_stm32_range_exists(dev, offset, len);
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}
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/*
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* Up to 255 4K pages
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*/
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