dts: infineon: Add DTSI files for PSoC6_04 and PSoC6_03 series
Adding DTSI files for MPN's based on the PSoC6_03 and PSoC6_04 Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This commit is contained in:
Sreeram Tatapudi
Anas Nashif
parent
224a72427f
commit
8d8e90b28f
21
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F12.dtsi
Normal file
21
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F12.dtsi
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_04/psoc6_04.64-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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/delete-node/ &adc1;
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/delete-node/ &scb3;
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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21
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F62.dtsi
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21
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F62.dtsi
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_04/psoc6_04.64-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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/delete-node/ &adc1;
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/delete-node/ &scb3;
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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19
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F82.dtsi
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19
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F82.dtsi
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_04/psoc6_04.64-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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/delete-node/ &scb3;
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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19
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F83.dtsi
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19
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F83.dtsi
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_04/psoc6_04.80-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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/delete-node/ &scb3;
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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19
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F92.dtsi
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19
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F92.dtsi
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_04/psoc6_04.64-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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/delete-node/ &scb3;
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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19
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F93.dtsi
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19
dts/arm/infineon/psoc6/mpns/CY8C6144AZI_S4F93.dtsi
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_04/psoc6_04.80-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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/delete-node/ &scb3;
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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21
dts/arm/infineon/psoc6/mpns/CY8C6144LQI_S4F12.dtsi
Normal file
21
dts/arm/infineon/psoc6/mpns/CY8C6144LQI_S4F12.dtsi
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_04/psoc6_04.68-qfn.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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/delete-node/ &adc1;
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/delete-node/ &scb3;
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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21
dts/arm/infineon/psoc6/mpns/CY8C6144LQI_S4F62.dtsi
Normal file
21
dts/arm/infineon/psoc6/mpns/CY8C6144LQI_S4F62.dtsi
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_04/psoc6_04.68-qfn.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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/delete-node/ &adc1;
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/delete-node/ &scb3;
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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19
dts/arm/infineon/psoc6/mpns/CY8C6144LQI_S4F82.dtsi
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19
dts/arm/infineon/psoc6/mpns/CY8C6144LQI_S4F82.dtsi
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_04/psoc6_04.68-qfn.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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/delete-node/ &scb3;
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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19
dts/arm/infineon/psoc6/mpns/CY8C6144LQI_S4F92.dtsi
Normal file
19
dts/arm/infineon/psoc6/mpns/CY8C6144LQI_S4F92.dtsi
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_04/psoc6_04.68-qfn.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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/delete-node/ &scb3;
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145AZI_S3F02.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145AZI_S3F02.dtsi
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_03/psoc6_03.100-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145AZI_S3F12.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145AZI_S3F12.dtsi
Normal file
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_03/psoc6_03.100-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145AZI_S3F42.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145AZI_S3F42.dtsi
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_03/psoc6_03.100-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145AZI_S3F62.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145AZI_S3F62.dtsi
Normal file
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_03/psoc6_03.100-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145AZI_S3F72.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145AZI_S3F72.dtsi
Normal file
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_03/psoc6_03.100-tqfp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145FNI_S3F11.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145FNI_S3F11.dtsi
Normal file
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_03/psoc6_03.49-wlcsp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145FNI_S3F41.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145FNI_S3F41.dtsi
Normal file
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_03/psoc6_03.49-wlcsp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145FNI_S3F71.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145FNI_S3F71.dtsi
Normal file
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_03/psoc6_03.49-wlcsp.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145LQI_S3F02.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145LQI_S3F02.dtsi
Normal file
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145LQI_S3F12.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145LQI_S3F12.dtsi
Normal file
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
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cpus {
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/delete-node/ cpu@0;
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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17
dts/arm/infineon/psoc6/mpns/CY8C6145LQI_S3F42.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145LQI_S3F42.dtsi
Normal file
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
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* an affiliate of Cypress Semiconductor Corporation
|
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C6145LQI_S3F62.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145LQI_S3F62.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C6145LQI_S3F72.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6145LQI_S3F72.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
25
dts/arm/infineon/psoc6/mpns/CY8C6148AZI_S2F44.dtsi
Normal file
25
dts/arm/infineon/psoc6/mpns/CY8C6148AZI_S2F44.dtsi
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.128-tqfp.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x100000>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x8000000 0x80000>;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
25
dts/arm/infineon/psoc6/mpns/CY8C6148BZI_S2F44.dtsi
Normal file
25
dts/arm/infineon/psoc6/mpns/CY8C6148BZI_S2F44.dtsi
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.124-bga.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x100000>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x8000000 0x80000>;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
25
dts/arm/infineon/psoc6/mpns/CY8C6148FNI_S2F43.dtsi
Normal file
25
dts/arm/infineon/psoc6/mpns/CY8C6148FNI_S2F43.dtsi
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.100-wlcsp.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x100000>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x8000000 0x80000>;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
35
dts/arm/infineon/psoc6/mpns/CY8C6148LQI_S2F02.dtsi
Normal file
35
dts/arm/infineon/psoc6/mpns/CY8C6148LQI_S2F02.dtsi
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.68-qfn.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x100000>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x8000000 0x80000>;
|
||||
};
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
/delete-node/ &scb7;
|
||||
|
||||
/delete-node/ &scb10;
|
||||
|
||||
/delete-node/ &scb11;
|
||||
|
||||
/delete-node/ &scb12;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
35
dts/arm/infineon/psoc6/mpns/CY8C6148LQI_S2F42.dtsi
Normal file
35
dts/arm/infineon/psoc6/mpns/CY8C6148LQI_S2F42.dtsi
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.68-qfn.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x100000>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x8000000 0x80000>;
|
||||
};
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
/delete-node/ &scb7;
|
||||
|
||||
/delete-node/ &scb10;
|
||||
|
||||
/delete-node/ &scb11;
|
||||
|
||||
/delete-node/ &scb12;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C614AAZI_S2F04.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C614AAZI_S2F04.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.128-tqfp.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C614AAZI_S2F14.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C614AAZI_S2F14.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.128-tqfp.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C614AAZI_S2F44.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C614AAZI_S2F44.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.128-tqfp.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C614ABZI_S2F04.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C614ABZI_S2F04.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.124-bga.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C614ABZI_S2F44.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C614ABZI_S2F44.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.124-bga.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C614AFNI_S2F03.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C614AFNI_S2F03.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.100-wlcsp.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C614AFNI_S2F43.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C614AFNI_S2F43.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.100-wlcsp.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
27
dts/arm/infineon/psoc6/mpns/CY8C614ALQI_S2F02.dtsi
Normal file
27
dts/arm/infineon/psoc6/mpns/CY8C614ALQI_S2F02.dtsi
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.68-qfn.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
/delete-node/ &scb7;
|
||||
|
||||
/delete-node/ &scb10;
|
||||
|
||||
/delete-node/ &scb11;
|
||||
|
||||
/delete-node/ &scb12;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
27
dts/arm/infineon/psoc6/mpns/CY8C614ALQI_S2F42.dtsi
Normal file
27
dts/arm/infineon/psoc6/mpns/CY8C614ALQI_S2F42.dtsi
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.68-qfn.dtsi"
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@0;
|
||||
};
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
/delete-node/ &scb7;
|
||||
|
||||
/delete-node/ &scb10;
|
||||
|
||||
/delete-node/ &scb11;
|
||||
|
||||
/delete-node/ &scb12;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D12.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D12.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_04/psoc6_04.64-tqfp.dtsi"
|
||||
|
||||
/delete-node/ &adc1;
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D62.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D62.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_04/psoc6_04.64-tqfp.dtsi"
|
||||
|
||||
/delete-node/ &adc1;
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
15
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D82.dtsi
Normal file
15
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D82.dtsi
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_04/psoc6_04.64-tqfp.dtsi"
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
15
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D83.dtsi
Normal file
15
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D83.dtsi
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_04/psoc6_04.80-tqfp.dtsi"
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
15
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D92.dtsi
Normal file
15
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D92.dtsi
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_04/psoc6_04.64-tqfp.dtsi"
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
15
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D93.dtsi
Normal file
15
dts/arm/infineon/psoc6/mpns/CY8C6244AZI_S4D93.dtsi
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_04/psoc6_04.80-tqfp.dtsi"
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C6244LQI_S4D12.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6244LQI_S4D12.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_04/psoc6_04.68-qfn.dtsi"
|
||||
|
||||
/delete-node/ &adc1;
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CY8C6244LQI_S4D62.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CY8C6244LQI_S4D62.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_04/psoc6_04.68-qfn.dtsi"
|
||||
|
||||
/delete-node/ &adc1;
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
15
dts/arm/infineon/psoc6/mpns/CY8C6244LQI_S4D82.dtsi
Normal file
15
dts/arm/infineon/psoc6/mpns/CY8C6244LQI_S4D82.dtsi
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_04/psoc6_04.68-qfn.dtsi"
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
15
dts/arm/infineon/psoc6/mpns/CY8C6244LQI_S4D92.dtsi
Normal file
15
dts/arm/infineon/psoc6/mpns/CY8C6244LQI_S4D92.dtsi
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_04/psoc6_04.68-qfn.dtsi"
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245AZI_S3D02.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245AZI_S3D02.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.100-tqfp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245AZI_S3D12.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245AZI_S3D12.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.100-tqfp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245AZI_S3D42.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245AZI_S3D42.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.100-tqfp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245AZI_S3D62.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245AZI_S3D62.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.100-tqfp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245AZI_S3D72.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245AZI_S3D72.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.100-tqfp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245FNI_S3D11.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245FNI_S3D11.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.49-wlcsp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245FNI_S3D41.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245FNI_S3D41.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.49-wlcsp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245FNI_S3D71.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245FNI_S3D71.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.49-wlcsp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245LQI_S3D02.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245LQI_S3D02.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245LQI_S3D12.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245LQI_S3D12.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245LQI_S3D42.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245LQI_S3D42.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245LQI_S3D62.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245LQI_S3D62.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6245LQI_S3D72.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6245LQI_S3D72.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C6248AZI_S2D14.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C6248AZI_S2D14.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.128-tqfp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
21
dts/arm/infineon/psoc6/mpns/CY8C6248AZI_S2D44.dtsi
Normal file
21
dts/arm/infineon/psoc6/mpns/CY8C6248AZI_S2D44.dtsi
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.128-tqfp.dtsi"
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x100000>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x8000000 0x80000>;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
21
dts/arm/infineon/psoc6/mpns/CY8C6248BZI_S2D44.dtsi
Normal file
21
dts/arm/infineon/psoc6/mpns/CY8C6248BZI_S2D44.dtsi
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.124-bga.dtsi"
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x100000>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x8000000 0x80000>;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
21
dts/arm/infineon/psoc6/mpns/CY8C6248FNI_S2D43.dtsi
Normal file
21
dts/arm/infineon/psoc6/mpns/CY8C6248FNI_S2D43.dtsi
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.100-wlcsp.dtsi"
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x100000>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x8000000 0x80000>;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
31
dts/arm/infineon/psoc6/mpns/CY8C6248LQI_S2D02.dtsi
Normal file
31
dts/arm/infineon/psoc6/mpns/CY8C6248LQI_S2D02.dtsi
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.68-qfn.dtsi"
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x100000>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x8000000 0x80000>;
|
||||
};
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
/delete-node/ &scb7;
|
||||
|
||||
/delete-node/ &scb10;
|
||||
|
||||
/delete-node/ &scb11;
|
||||
|
||||
/delete-node/ &scb12;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
31
dts/arm/infineon/psoc6/mpns/CY8C6248LQI_S2D42.dtsi
Normal file
31
dts/arm/infineon/psoc6/mpns/CY8C6248LQI_S2D42.dtsi
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.68-qfn.dtsi"
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x100000>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x8000000 0x80000>;
|
||||
};
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
/delete-node/ &scb7;
|
||||
|
||||
/delete-node/ &scb10;
|
||||
|
||||
/delete-node/ &scb11;
|
||||
|
||||
/delete-node/ &scb12;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C624AAZI_S2D14.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C624AAZI_S2D14.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.128-tqfp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C624AAZI_S2D44.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C624AAZI_S2D44.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.128-tqfp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C624ABZI_D44.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C624ABZI_D44.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.124-bga.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C624ABZI_S2D04.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C624ABZI_S2D04.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.124-bga.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C624ABZI_S2D14.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C624ABZI_S2D14.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.124-bga.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C624ABZI_S2D44A0.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C624ABZI_S2D44A0.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.124-bga.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
13
dts/arm/infineon/psoc6/mpns/CY8C624AFNI_S2D43.dtsi
Normal file
13
dts/arm/infineon/psoc6/mpns/CY8C624AFNI_S2D43.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.100-wlcsp.dtsi"
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
23
dts/arm/infineon/psoc6/mpns/CY8C624ALQI_S2D02.dtsi
Normal file
23
dts/arm/infineon/psoc6/mpns/CY8C624ALQI_S2D02.dtsi
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.68-qfn.dtsi"
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
/delete-node/ &scb7;
|
||||
|
||||
/delete-node/ &scb10;
|
||||
|
||||
/delete-node/ &scb11;
|
||||
|
||||
/delete-node/ &scb12;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
23
dts/arm/infineon/psoc6/mpns/CY8C624ALQI_S2D42.dtsi
Normal file
23
dts/arm/infineon/psoc6/mpns/CY8C624ALQI_S2D42.dtsi
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.68-qfn.dtsi"
|
||||
|
||||
/delete-node/ &scb3;
|
||||
|
||||
/delete-node/ &scb7;
|
||||
|
||||
/delete-node/ &scb10;
|
||||
|
||||
/delete-node/ &scb11;
|
||||
|
||||
/delete-node/ &scb12;
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CYB06445LQI_S3D42.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CYB06445LQI_S3D42.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_03/psoc6_03.68-qfn.dtsi"
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x70000>;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CYB0644ABZI_S2D44.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CYB0644ABZI_S2D44.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.124-bga.dtsi"
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x1d0000>;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
17
dts/arm/infineon/psoc6/mpns/CYS0644ABZI_S2D44.dtsi
Normal file
17
dts/arm/infineon/psoc6/mpns/CYS0644ABZI_S2D44.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include "../psoc6_02/psoc6_02.124-bga.dtsi"
|
||||
|
||||
&flash0 {
|
||||
reg = <0x10000000 0x1d0000>;
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
332
dts/arm/infineon/psoc6/psoc6_02/psoc6_02.100-wlcsp.dtsi
Normal file
332
dts/arm/infineon/psoc6/psoc6_02/psoc6_02.100-wlcsp.dtsi
Normal file
|
|
@ -0,0 +1,332 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
|
||||
#include "psoc6_02.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ gpio@40310180; // gpio_prt3
|
||||
/delete-node/ gpio@40310200; // gpio_prt4
|
||||
|
||||
pinctrl: pinctrl@40300000 {
|
||||
/* scb_i2c_scl */
|
||||
/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p1_0_scb7_i2c_scl: p1_0_scb7_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_4_scb9_i2c_scl: p2_4_scb9_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_4_scb10_i2c_scl: p5_4_scb10_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_0_scb8_i2c_scl: p6_0_scb8_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_4_scb11_i2c_scl: p8_4_scb11_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_0_scb6_i2c_scl: p12_0_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_0_scb6_i2c_scl: p13_0_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_4_scb12_i2c_scl: p13_4_scb12_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_i2c_sda */
|
||||
/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p1_1_scb7_i2c_sda: p1_1_scb7_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_5_scb9_i2c_sda: p2_5_scb9_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_5_scb10_i2c_sda: p5_5_scb10_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_1_scb8_i2c_sda: p6_1_scb8_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_1_scb6_i2c_sda: p12_1_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_1_scb6_i2c_sda: p13_1_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_5_scb12_i2c_sda: p13_5_scb12_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_uart_cts */
|
||||
/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_7_scb9_uart_cts: p2_7_scb9_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_3_scb5_uart_cts: p5_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_7_scb10_uart_cts: p5_7_scb10_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_3_scb4_uart_cts: p8_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_3_scb6_uart_cts: p12_3_scb6_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_3_scb6_uart_cts: p13_3_scb6_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_7_scb12_uart_cts: p13_7_scb12_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rts */
|
||||
/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_6_scb9_uart_rts: p2_6_scb9_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_2_scb5_uart_rts: p5_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_6_scb10_uart_rts: p5_6_scb10_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_2_scb6_uart_rts: p12_2_scb6_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_2_scb6_uart_rts: p13_2_scb6_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_6_scb12_uart_rts: p13_6_scb12_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rx */
|
||||
/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p1_0_scb7_uart_rx: p1_0_scb7_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_4_scb9_uart_rx: p2_4_scb9_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_4_scb10_uart_rx: p5_4_scb10_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_4_scb11_uart_rx: p8_4_scb11_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_0_scb6_uart_rx: p12_0_scb6_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_0_scb6_uart_rx: p13_0_scb6_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_4_scb12_uart_rx: p13_4_scb12_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_tx */
|
||||
/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p1_1_scb7_uart_tx: p1_1_scb7_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_5_scb9_uart_tx: p2_5_scb9_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_5_scb10_uart_tx: p5_5_scb10_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_1_scb6_uart_tx: p12_1_scb6_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_5_scb12_uart_tx: p13_5_scb12_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
384
dts/arm/infineon/psoc6/psoc6_02/psoc6_02.128-tqfp.dtsi
Normal file
384
dts/arm/infineon/psoc6/psoc6_02/psoc6_02.128-tqfp.dtsi
Normal file
|
|
@ -0,0 +1,384 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
|
||||
#include "psoc6_02.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
|
||||
pinctrl: pinctrl@40300000 {
|
||||
/* scb_i2c_scl */
|
||||
/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p1_0_scb7_i2c_scl: p1_0_scb7_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_4_scb9_i2c_scl: p2_4_scb9_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p4_0_scb7_i2c_scl: p4_0_scb7_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_4_scb10_i2c_scl: p5_4_scb10_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_0_scb8_i2c_scl: p6_0_scb8_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_4_scb11_i2c_scl: p8_4_scb11_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_0_scb6_i2c_scl: p12_0_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_0_scb6_i2c_scl: p13_0_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_4_scb12_i2c_scl: p13_4_scb12_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_i2c_sda */
|
||||
/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p1_1_scb7_i2c_sda: p1_1_scb7_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_5_scb9_i2c_sda: p2_5_scb9_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p4_1_scb7_i2c_sda: p4_1_scb7_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_5_scb10_i2c_sda: p5_5_scb10_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_1_scb8_i2c_sda: p6_1_scb8_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_5_scb11_i2c_sda: p8_5_scb11_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_1_scb6_i2c_sda: p12_1_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_1_scb6_i2c_sda: p13_1_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_5_scb12_i2c_sda: p13_5_scb12_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_uart_cts */
|
||||
/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p1_3_scb7_uart_cts: p1_3_scb7_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_7_scb9_uart_cts: p2_7_scb9_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_3_scb2_uart_cts: p3_3_scb2_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p4_3_scb7_uart_cts: p4_3_scb7_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(4, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_3_scb5_uart_cts: p5_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_7_scb10_uart_cts: p5_7_scb10_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_3_scb4_uart_cts: p8_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_7_scb11_uart_cts: p8_7_scb11_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_3_scb6_uart_cts: p12_3_scb6_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_3_scb6_uart_cts: p13_3_scb6_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_7_scb12_uart_cts: p13_7_scb12_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rts */
|
||||
/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p1_2_scb7_uart_rts: p1_2_scb7_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_6_scb9_uart_rts: p2_6_scb9_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_2_scb2_uart_rts: p3_2_scb2_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p4_2_scb7_uart_rts: p4_2_scb7_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(4, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_2_scb5_uart_rts: p5_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_6_scb10_uart_rts: p5_6_scb10_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_6_scb11_uart_rts: p8_6_scb11_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_2_scb6_uart_rts: p12_2_scb6_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_2_scb6_uart_rts: p13_2_scb6_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_6_scb12_uart_rts: p13_6_scb12_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rx */
|
||||
/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p1_0_scb7_uart_rx: p1_0_scb7_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_4_scb9_uart_rx: p2_4_scb9_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p4_0_scb7_uart_rx: p4_0_scb7_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_4_scb10_uart_rx: p5_4_scb10_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_4_scb11_uart_rx: p8_4_scb11_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_0_scb6_uart_rx: p12_0_scb6_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_0_scb6_uart_rx: p13_0_scb6_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_4_scb12_uart_rx: p13_4_scb12_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_tx */
|
||||
/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p1_1_scb7_uart_tx: p1_1_scb7_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_5_scb9_uart_tx: p2_5_scb9_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p4_1_scb7_uart_tx: p4_1_scb7_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_5_scb10_uart_tx: p5_5_scb10_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_5_scb11_uart_tx: p8_5_scb11_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_1_scb6_uart_tx: p12_1_scb6_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p13_5_scb12_uart_tx: p13_5_scb12_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
231
dts/arm/infineon/psoc6/psoc6_02/psoc6_02.68-qfn.dtsi
Normal file
231
dts/arm/infineon/psoc6/psoc6_02/psoc6_02.68-qfn.dtsi
Normal file
|
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
|
||||
#include "psoc6_02.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ gpio@40310080; // gpio_prt1
|
||||
/delete-node/ gpio@40310200; // gpio_prt4
|
||||
/delete-node/ gpio@40310680; // gpio_prt13
|
||||
|
||||
pinctrl: pinctrl@40300000 {
|
||||
/* scb_i2c_scl */
|
||||
/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_4_scb9_i2c_scl: p2_4_scb9_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_i2c_sda */
|
||||
/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_5_scb9_i2c_sda: p2_5_scb9_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_uart_cts */
|
||||
/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_7_scb9_uart_cts: p2_7_scb9_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_7_scb10_uart_cts: p5_7_scb10_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rts */
|
||||
/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_6_scb9_uart_rts: p2_6_scb9_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_6_scb10_uart_rts: p5_6_scb10_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rx */
|
||||
/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_4_scb9_uart_rx: p2_4_scb9_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_tx */
|
||||
/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_5_scb9_uart_tx: p2_5_scb9_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
213
dts/arm/infineon/psoc6/psoc6_03/psoc6_03.100-tqfp.dtsi
Normal file
213
dts/arm/infineon/psoc6/psoc6_03/psoc6_03.100-tqfp.dtsi
Normal file
|
|
@ -0,0 +1,213 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
|
||||
#include "psoc6_03.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ gpio@40310080; // gpio_prt1
|
||||
/delete-node/ gpio@40310200; // gpio_prt4
|
||||
/delete-node/ gpio@40310680; // gpio_prt13
|
||||
|
||||
pinctrl: pinctrl@40300000 {
|
||||
/* scb_i2c_scl */
|
||||
/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_0_scb6_i2c_scl: p12_0_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
|
||||
/* scb_i2c_sda */
|
||||
/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p12_1_scb6_i2c_sda: p12_1_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
|
||||
/* scb_uart_cts */
|
||||
/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_3_scb4_uart_cts: p8_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rts */
|
||||
/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rx */
|
||||
/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_tx */
|
||||
/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
142
dts/arm/infineon/psoc6/psoc6_03/psoc6_03.49-wlcsp.dtsi
Normal file
142
dts/arm/infineon/psoc6/psoc6_03/psoc6_03.49-wlcsp.dtsi
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
|
||||
#include "psoc6_03.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ gpio@40310080; // gpio_prt1
|
||||
/delete-node/ gpio@40310180; // gpio_prt3
|
||||
/delete-node/ gpio@40310200; // gpio_prt4
|
||||
/delete-node/ gpio@40310400; // gpio_prt8
|
||||
/delete-node/ gpio@40310600; // gpio_prt12
|
||||
/delete-node/ gpio@40310680; // gpio_prt13
|
||||
/delete-node/ gpio@40310700; // gpio_prt14
|
||||
|
||||
pinctrl: pinctrl@40300000 {
|
||||
/* scb_i2c_scl */
|
||||
/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_i2c_sda */
|
||||
/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_uart_cts */
|
||||
/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rts */
|
||||
/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rx */
|
||||
/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_tx */
|
||||
/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
189
dts/arm/infineon/psoc6/psoc6_03/psoc6_03.68-qfn.dtsi
Normal file
189
dts/arm/infineon/psoc6/psoc6_03/psoc6_03.68-qfn.dtsi
Normal file
|
|
@ -0,0 +1,189 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
|
||||
#include "psoc6_03.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ gpio@40310080; // gpio_prt1
|
||||
/delete-node/ gpio@40310200; // gpio_prt4
|
||||
/delete-node/ gpio@40310680; // gpio_prt13
|
||||
|
||||
pinctrl: pinctrl@40300000 {
|
||||
/* scb_i2c_scl */
|
||||
/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_i2c_sda */
|
||||
/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_uart_cts */
|
||||
/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rts */
|
||||
/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rx */
|
||||
/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_tx */
|
||||
/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
246
dts/arm/infineon/psoc6/psoc6_03/psoc6_03.dtsi
Normal file
246
dts/arm/infineon/psoc6/psoc6_03/psoc6_03.dtsi
Normal file
|
|
@ -0,0 +1,246 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m0+";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m4f";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
flash-controller@40240000 {
|
||||
compatible = "infineon,cat1-flash-controller";
|
||||
reg = < 0x40240000 0x10000 >;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0: flash@10000000 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0x10000000 0x80000>;
|
||||
write-block-size = <512>;
|
||||
erase-block-size = <512>;
|
||||
};
|
||||
flash1: flash@14000000 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0x14000000 0x8000>;
|
||||
write-block-size = <512>;
|
||||
erase-block-size = <512>;
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory@8000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x8000000 0x40000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl: pinctrl@40300000 {
|
||||
compatible = "infineon,cat1-pinctrl";
|
||||
reg = <0x40300000 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hsiom: hsiom@40300000 {
|
||||
compatible = "infineon,cat1-hsiom";
|
||||
reg = <0x40300000 0x4000>;
|
||||
interrupts = <15 6>, <16 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio_prt0: gpio@40310000 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310000 0x80>;
|
||||
interrupts = <0 6>;
|
||||
gpio-controller;
|
||||
ngpios = <6>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt2: gpio@40310100 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310100 0x80>;
|
||||
interrupts = <2 6>;
|
||||
gpio-controller;
|
||||
ngpios = <8>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt3: gpio@40310180 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310180 0x80>;
|
||||
interrupts = <3 6>;
|
||||
gpio-controller;
|
||||
ngpios = <2>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt5: gpio@40310280 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310280 0x80>;
|
||||
interrupts = <5 6>;
|
||||
gpio-controller;
|
||||
ngpios = <4>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt6: gpio@40310300 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310300 0x80>;
|
||||
interrupts = <6 6>;
|
||||
gpio-controller;
|
||||
ngpios = <8>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt7: gpio@40310380 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310380 0x80>;
|
||||
interrupts = <7 6>;
|
||||
gpio-controller;
|
||||
ngpios = <8>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt8: gpio@40310400 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310400 0x80>;
|
||||
interrupts = <8 6>;
|
||||
gpio-controller;
|
||||
ngpios = <4>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt9: gpio@40310480 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310480 0x80>;
|
||||
interrupts = <9 6>;
|
||||
gpio-controller;
|
||||
ngpios = <4>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt10: gpio@40310500 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310500 0x80>;
|
||||
interrupts = <10 6>;
|
||||
gpio-controller;
|
||||
ngpios = <8>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt11: gpio@40310580 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310580 0x80>;
|
||||
interrupts = <11 6>;
|
||||
gpio-controller;
|
||||
ngpios = <8>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt12: gpio@40310600 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310600 0x80>;
|
||||
interrupts = <12 6>;
|
||||
gpio-controller;
|
||||
ngpios = <4>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt14: gpio@40310700 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310700 0x80>;
|
||||
interrupts = <14 6>;
|
||||
gpio-controller;
|
||||
ngpios = <2>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
uid: device_uid@16000600 {
|
||||
compatible = "infineon,cat1-uid";
|
||||
reg = <0x16000600 0xb>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc0: adc@409f0000 {
|
||||
compatible = "infineon,cat1-adc";
|
||||
reg = <0x409f0000 0x10000>;
|
||||
interrupts = <155 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scb0: scb@40600000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40600000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <39 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb1: scb@40610000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40610000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <40 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb2: scb@40620000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40620000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <41 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb3: scb@40630000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40630000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <42 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb4: scb@40640000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40640000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <43 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb5: scb@40650000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40650000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <44 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb6: scb@40660000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40660000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <18 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
172
dts/arm/infineon/psoc6/psoc6_04/psoc6_04.64-tqfp-epad.dtsi
Normal file
172
dts/arm/infineon/psoc6/psoc6_04/psoc6_04.64-tqfp-epad.dtsi
Normal file
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
|
||||
#include "psoc6_04.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ gpio@40310080; // gpio_prt1
|
||||
/delete-node/ gpio@40310200; // gpio_prt4
|
||||
/delete-node/ gpio@40310680; // gpio_prt13
|
||||
/delete-node/ gpio@40310700; // gpio_prt14
|
||||
|
||||
pinctrl: pinctrl@40300000 {
|
||||
/* scb_i2c_scl */
|
||||
/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_i2c_sda */
|
||||
/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_uart_cts */
|
||||
/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rts */
|
||||
/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rx */
|
||||
/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_tx */
|
||||
/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
171
dts/arm/infineon/psoc6/psoc6_04/psoc6_04.68-qfn.dtsi
Normal file
171
dts/arm/infineon/psoc6/psoc6_04/psoc6_04.68-qfn.dtsi
Normal file
|
|
@ -0,0 +1,171 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
|
||||
#include "psoc6_04.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ gpio@40310080; // gpio_prt1
|
||||
/delete-node/ gpio@40310200; // gpio_prt4
|
||||
/delete-node/ gpio@40310680; // gpio_prt13
|
||||
|
||||
pinctrl: pinctrl@40300000 {
|
||||
/* scb_i2c_scl */
|
||||
/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_i2c_sda */
|
||||
/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_uart_cts */
|
||||
/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rts */
|
||||
/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rx */
|
||||
/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_tx */
|
||||
/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
171
dts/arm/infineon/psoc6/psoc6_04/psoc6_04.80-tqfp.dtsi
Normal file
171
dts/arm/infineon/psoc6/psoc6_04/psoc6_04.80-tqfp.dtsi
Normal file
|
|
@ -0,0 +1,171 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
|
||||
#include "psoc6_04.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ gpio@40310200; // gpio_prt4
|
||||
/delete-node/ gpio@40310680; // gpio_prt13
|
||||
/delete-node/ gpio@40310700; // gpio_prt14
|
||||
|
||||
pinctrl: pinctrl@40300000 {
|
||||
/* scb_i2c_scl */
|
||||
/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_i2c_sda */
|
||||
/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
|
||||
};
|
||||
|
||||
/* scb_uart_cts */
|
||||
/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rts */
|
||||
/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
|
||||
pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_rx */
|
||||
/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
/* scb_uart_tx */
|
||||
/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
252
dts/arm/infineon/psoc6/psoc6_04/psoc6_04.dtsi
Normal file
252
dts/arm/infineon/psoc6/psoc6_04/psoc6_04.dtsi
Normal file
|
|
@ -0,0 +1,252 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m0+";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m4f";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
flash-controller@40240000 {
|
||||
compatible = "infineon,cat1-flash-controller";
|
||||
reg = < 0x40240000 0x10000 >;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0: flash@10000000 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0x10000000 0x40000>;
|
||||
write-block-size = <512>;
|
||||
erase-block-size = <512>;
|
||||
};
|
||||
flash1: flash@14000000 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0x14000000 0x0>;
|
||||
write-block-size = <512>;
|
||||
erase-block-size = <512>;
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory@8000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x8000000 0x20000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl: pinctrl@40300000 {
|
||||
compatible = "infineon,cat1-pinctrl";
|
||||
reg = <0x40300000 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hsiom: hsiom@40300000 {
|
||||
compatible = "infineon,cat1-hsiom";
|
||||
reg = <0x40300000 0x4000>;
|
||||
interrupts = <15 6>, <16 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio_prt0: gpio@40310000 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310000 0x80>;
|
||||
interrupts = <0 6>;
|
||||
gpio-controller;
|
||||
ngpios = <6>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt1: gpio@40310080 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310080 0x80>;
|
||||
gpio-controller;
|
||||
ngpios = <3>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt2: gpio@40310100 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310100 0x80>;
|
||||
interrupts = <2 6>;
|
||||
gpio-controller;
|
||||
ngpios = <8>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt3: gpio@40310180 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310180 0x80>;
|
||||
interrupts = <3 6>;
|
||||
gpio-controller;
|
||||
ngpios = <2>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt5: gpio@40310280 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310280 0x80>;
|
||||
interrupts = <5 6>;
|
||||
gpio-controller;
|
||||
ngpios = <5>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt6: gpio@40310300 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310300 0x80>;
|
||||
interrupts = <6 6>;
|
||||
gpio-controller;
|
||||
ngpios = <6>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt7: gpio@40310380 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310380 0x80>;
|
||||
interrupts = <7 6>;
|
||||
gpio-controller;
|
||||
ngpios = <7>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt8: gpio@40310400 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310400 0x80>;
|
||||
interrupts = <8 6>;
|
||||
gpio-controller;
|
||||
ngpios = <2>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt9: gpio@40310480 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310480 0x80>;
|
||||
interrupts = <9 6>;
|
||||
gpio-controller;
|
||||
ngpios = <6>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt10: gpio@40310500 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310500 0x80>;
|
||||
interrupts = <10 6>;
|
||||
gpio-controller;
|
||||
ngpios = <8>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt11: gpio@40310580 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310580 0x80>;
|
||||
interrupts = <11 6>;
|
||||
gpio-controller;
|
||||
ngpios = <7>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt12: gpio@40310600 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310600 0x80>;
|
||||
interrupts = <12 6>;
|
||||
gpio-controller;
|
||||
ngpios = <2>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpio_prt14: gpio@40310700 {
|
||||
compatible = "infineon,cat1-gpio";
|
||||
reg = <0x40310700 0x80>;
|
||||
interrupts = <14 6>;
|
||||
gpio-controller;
|
||||
ngpios = <2>;
|
||||
status = "disabled";
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
uid: device_uid@16000600 {
|
||||
compatible = "infineon,cat1-uid";
|
||||
reg = <0x16000600 0xb>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc0: adc@409f0000 {
|
||||
compatible = "infineon,cat1-adc";
|
||||
reg = <0x409f0000 0x10000>;
|
||||
interrupts = <39 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
adc1: adc@409f0000 {
|
||||
compatible = "infineon,cat1-adc";
|
||||
reg = <0x409f0000 0x10000>;
|
||||
interrupts = <40 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scb0: scb@40600000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40600000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <45 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb1: scb@40610000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40610000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <46 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb2: scb@40620000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40620000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <47 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb4: scb@40640000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40640000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <49 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb5: scb@40650000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40650000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <50 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
scb6: scb@40660000 {
|
||||
compatible = "infineon,cat1-scb";
|
||||
reg = <0x40660000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <18 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
Loading…
Reference in a new issue