drivers: mcux: flexio: Added MCUX FlexIO SPI driver
Added SPI driver using FlexIO. Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
This commit is contained in:
Mikhail Siomin
Alberto Escolar
parent
877b10bef1
commit
8dbfdd6f9f
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@ -11,6 +11,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_EMUL spi_emul.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_FLEXCOMM spi_mcux_flexcomm.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_FLEXIO spi_mcux_flexio.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI spi_mcux_lpspi.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_SAM spi_sam.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_SAM0 spi_sam0.c)
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@ -75,6 +75,8 @@ source "drivers/spi/Kconfig.mcux_dspi"
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source "drivers/spi/Kconfig.mcux_flexcomm"
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source "drivers/spi/Kconfig.mcux_flexio"
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source "drivers/spi/Kconfig.mcux_lpspi"
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source "drivers/spi/Kconfig.rv32m1_lpspi"
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11
drivers/spi/Kconfig.mcux_flexio
Normal file
11
drivers/spi/Kconfig.mcux_flexio
Normal file
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@ -0,0 +1,11 @@
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# Copyright (c) 2024, STRIM, ALC
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# SPDX-License-Identifier: Apache-2.0
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config SPI_MCUX_FLEXIO
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bool "MCUX FlexIO SPI driver"
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default y
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depends on DT_HAS_NXP_FLEXIO_SPI_ENABLED
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depends on CLOCK_CONTROL
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select MCUX_FLEXIO
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help
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Enable support for MCUX FlexIO SPI driver.
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438
drivers/spi/spi_mcux_flexio.c
Normal file
438
drivers/spi/spi_mcux_flexio.c
Normal file
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@ -0,0 +1,438 @@
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/*
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* Copyright (c) 2024, STRIM, ALC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_flexio_spi
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#include <errno.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/clock_control.h>
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#include <fsl_flexio_spi.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/misc/nxp_flexio/nxp_flexio.h>
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LOG_MODULE_REGISTER(spi_mcux_flexio_spi, CONFIG_SPI_LOG_LEVEL);
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#include "spi_context.h"
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struct spi_mcux_flexio_config {
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FLEXIO_SPI_Type *flexio_spi;
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const struct device *flexio_dev;
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const struct pinctrl_dev_config *pincfg;
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const struct nxp_flexio_child *child;
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};
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struct spi_mcux_flexio_data {
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const struct device *dev;
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flexio_spi_master_handle_t handle;
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struct spi_context ctx;
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size_t transfer_len;
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uint8_t transfer_flags;
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};
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static void spi_mcux_transfer_next_packet(const struct device *dev)
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{
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const struct spi_mcux_flexio_config *config = dev->config;
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struct spi_mcux_flexio_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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flexio_spi_transfer_t transfer;
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status_t status;
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if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) {
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/* nothing left to rx or tx, we're done! */
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spi_context_cs_control(&data->ctx, false);
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spi_context_complete(&data->ctx, dev, 0);
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return;
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}
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transfer.flags = kFLEXIO_SPI_csContinuous | data->transfer_flags;
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if (ctx->tx_len == 0) {
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/* rx only, nothing to tx */
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transfer.txData = NULL;
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transfer.rxData = ctx->rx_buf;
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transfer.dataSize = ctx->rx_len;
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} else if (ctx->rx_len == 0) {
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/* tx only, nothing to rx */
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transfer.txData = (uint8_t *) ctx->tx_buf;
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transfer.rxData = NULL;
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transfer.dataSize = ctx->tx_len;
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} else if (ctx->tx_len == ctx->rx_len) {
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/* rx and tx are the same length */
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transfer.txData = (uint8_t *) ctx->tx_buf;
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transfer.rxData = ctx->rx_buf;
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transfer.dataSize = ctx->tx_len;
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} else if (ctx->tx_len > ctx->rx_len) {
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/* Break up the tx into multiple transfers so we don't have to
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* rx into a longer intermediate buffer. Leave chip select
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* active between transfers.
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*/
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transfer.txData = (uint8_t *) ctx->tx_buf;
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transfer.rxData = ctx->rx_buf;
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transfer.dataSize = ctx->rx_len;
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} else {
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/* Break up the rx into multiple transfers so we don't have to
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* tx from a longer intermediate buffer. Leave chip select
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* active between transfers.
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*/
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transfer.txData = (uint8_t *) ctx->tx_buf;
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transfer.rxData = ctx->rx_buf;
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transfer.dataSize = ctx->tx_len;
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}
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data->transfer_len = transfer.dataSize;
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status = FLEXIO_SPI_MasterTransferNonBlocking(config->flexio_spi, &data->handle,
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&transfer);
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if (status != kStatus_Success) {
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LOG_ERR("Transfer could not start");
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}
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}
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static int spi_mcux_flexio_isr(void *user_data)
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{
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const struct device *dev = (const struct device *)user_data;
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const struct spi_mcux_flexio_config *config = dev->config;
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struct spi_mcux_flexio_data *data = dev->data;
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FLEXIO_SPI_MasterTransferHandleIRQ(config->flexio_spi, &data->handle);
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return 0;
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}
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static void spi_mcux_master_transfer_callback(FLEXIO_SPI_Type *flexio_spi,
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flexio_spi_master_handle_t *handle, status_t status, void *userData)
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{
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struct spi_mcux_flexio_data *data = userData;
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spi_context_update_tx(&data->ctx, 1, data->transfer_len);
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spi_context_update_rx(&data->ctx, 1, data->transfer_len);
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spi_mcux_transfer_next_packet(data->dev);
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}
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static void spi_flexio_master_init(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig,
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uint8_t pol, uint32_t srcClock_Hz)
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{
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assert(base != NULL);
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assert(masterConfig != NULL);
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flexio_shifter_config_t shifterConfig;
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flexio_timer_config_t timerConfig;
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uint32_t ctrlReg = 0;
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uint16_t timerDiv = 0;
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uint16_t timerCmp = 0;
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/* Clear the shifterConfig & timerConfig struct. */
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(void)memset(&shifterConfig, 0, sizeof(shifterConfig));
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(void)memset(&timerConfig, 0, sizeof(timerConfig));
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/* Configure FLEXIO SPI Master */
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ctrlReg = base->flexioBase->CTRL;
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ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK |
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FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
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ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) |
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FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) |
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FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
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if (!masterConfig->enableInDoze) {
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ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
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}
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base->flexioBase->CTRL = ctrlReg;
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/* Do hardware configuration. */
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/* 1. Configure the shifter 0 for tx. */
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shifterConfig.timerSelect = base->timerIndex[0];
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
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shifterConfig.pinSelect = base->SDOPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) {
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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} else {
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
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}
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
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/* 2. Configure the shifter 1 for rx. */
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shifterConfig.timerSelect = base->timerIndex[0];
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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shifterConfig.pinSelect = base->SDIPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) {
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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} else {
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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}
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
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/*3. Configure the timer 0 for SCK. */
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
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timerConfig.pinSelect = base->SCKPinIndex;
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timerConfig.pinPolarity = pol ? kFLEXIO_PinActiveLow : kFLEXIO_PinActiveHigh;
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timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
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timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
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timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
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/* Low 8-bits are used to configure baudrate. */
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timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps);
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timerDiv = timerDiv / 2U - 1U;
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/* High 8-bits are used to configure shift clock edges(transfer width). */
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timerCmp = ((uint16_t)masterConfig->dataMode * 2U - 1U) << 8U;
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timerCmp |= timerDiv;
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timerConfig.timerCompare = timerCmp;
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FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
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}
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static int spi_mcux_flexio_configure(const struct device *dev,
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const struct spi_config *spi_cfg)
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{
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const struct spi_mcux_flexio_config *config = dev->config;
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struct spi_mcux_flexio_data *data = dev->data;
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flexio_spi_master_config_t master_config;
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uint32_t clock_freq;
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uint32_t word_size;
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if (spi_context_configured(&data->ctx, spi_cfg)) {
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/* This configuration is already in use */
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return 0;
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}
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if (spi_cfg->operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half-duplex not supported");
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return -ENOTSUP;
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}
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if (SPI_OP_MODE_GET(spi_cfg->operation) != SPI_OP_MODE_MASTER) {
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LOG_ERR("Mode Slave not supported");
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return -ENOTSUP;
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}
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FLEXIO_SPI_MasterGetDefaultConfig(&master_config);
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word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
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if ((word_size != 8) && (word_size != 16) && (word_size != 32)) {
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LOG_ERR("Word size %d must be 8, 16 or 32", word_size);
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return -EINVAL;
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}
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master_config.dataMode = word_size;
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if (spi_cfg->operation & SPI_TRANSFER_LSB) {
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if (word_size == 8) {
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data->transfer_flags = kFLEXIO_SPI_8bitLsb;
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} else if (word_size == 16) {
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data->transfer_flags = kFLEXIO_SPI_16bitLsb;
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} else {
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data->transfer_flags = kFLEXIO_SPI_32bitLsb;
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}
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} else {
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if (word_size == 8) {
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data->transfer_flags = kFLEXIO_SPI_8bitMsb;
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} else if (word_size == 16) {
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data->transfer_flags = kFLEXIO_SPI_16bitMsb;
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} else {
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data->transfer_flags = kFLEXIO_SPI_32bitMsb;
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}
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}
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if (nxp_flexio_get_rate(config->flexio_dev, &clock_freq)) {
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return -EINVAL;
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}
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master_config.phase =
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(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
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? kFLEXIO_SPI_ClockPhaseSecondEdge
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: kFLEXIO_SPI_ClockPhaseFirstEdge;
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master_config.baudRate_Bps = spi_cfg->frequency;
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spi_flexio_master_init(config->flexio_spi, &master_config,
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(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL), clock_freq);
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FLEXIO_SPI_MasterTransferCreateHandle(config->flexio_spi, &data->handle,
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spi_mcux_master_transfer_callback,
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data);
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/* No SetDummyData() for FlexIO_SPI */
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data->ctx.config = spi_cfg;
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return 0;
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}
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static int transceive(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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bool asynchronous,
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spi_callback_t cb,
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void *userdata)
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{
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const struct spi_mcux_flexio_config *config = dev->config;
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struct spi_mcux_flexio_data *data = dev->data;
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int ret;
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spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
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nxp_flexio_lock(config->flexio_dev);
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ret = spi_mcux_flexio_configure(dev, spi_cfg);
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nxp_flexio_unlock(config->flexio_dev);
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if (ret) {
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goto out;
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}
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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spi_context_cs_control(&data->ctx, true);
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nxp_flexio_lock(config->flexio_dev);
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nxp_flexio_irq_disable(config->flexio_dev);
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spi_mcux_transfer_next_packet(dev);
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nxp_flexio_irq_enable(config->flexio_dev);
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nxp_flexio_unlock(config->flexio_dev);
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ret = spi_context_wait_for_completion(&data->ctx);
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out:
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spi_context_release(&data->ctx, ret);
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return ret;
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}
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static int spi_mcux_transceive(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
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}
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#ifdef CONFIG_SPI_ASYNC
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static int spi_mcux_transceive_async(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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spi_callback_t cb,
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void *userdata)
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{
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
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}
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#endif /* CONFIG_SPI_ASYNC */
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static int spi_mcux_release(const struct device *dev,
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const struct spi_config *spi_cfg)
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{
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struct spi_mcux_flexio_data *data = dev->data;
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static int spi_mcux_init(const struct device *dev)
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{
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const struct spi_mcux_flexio_config *config = dev->config;
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struct spi_mcux_flexio_data *data = dev->data;
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int err;
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err = nxp_flexio_child_attach(config->flexio_dev, config->child);
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if (err < 0) {
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return err;
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}
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err = spi_context_cs_configure_all(&data->ctx);
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if (err < 0) {
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return err;
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}
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spi_context_unlock_unconditionally(&data->ctx);
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data->dev = dev;
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/* TODO: DMA */
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err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
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if (err) {
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return err;
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}
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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|
||||
static const struct spi_driver_api spi_mcux_driver_api = {
|
||||
.transceive = spi_mcux_transceive,
|
||||
#ifdef CONFIG_SPI_ASYNC
|
||||
.transceive_async = spi_mcux_transceive_async,
|
||||
#endif
|
||||
.release = spi_mcux_release,
|
||||
};
|
||||
|
||||
#define SPI_MCUX_FLEXIO_SPI_INIT(n) \
|
||||
PINCTRL_DT_INST_DEFINE(n); \
|
||||
\
|
||||
static FLEXIO_SPI_Type flexio_spi_##n = { \
|
||||
.flexioBase = (FLEXIO_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \
|
||||
.SDOPinIndex = DT_INST_PROP(n, sdo_pin), \
|
||||
.SDIPinIndex = DT_INST_PROP(n, sdi_pin), \
|
||||
.SCKPinIndex = DT_INST_PROP(n, sck_pin), \
|
||||
}; \
|
||||
\
|
||||
static const struct nxp_flexio_child nxp_flexio_spi_child_##n = { \
|
||||
.isr = spi_mcux_flexio_isr, \
|
||||
.user_data = (void *)DEVICE_DT_INST_GET(n), \
|
||||
.res = { \
|
||||
.shifter_index = flexio_spi_##n.shifterIndex, \
|
||||
.shifter_count = ARRAY_SIZE(flexio_spi_##n.shifterIndex), \
|
||||
.timer_index = flexio_spi_##n.timerIndex, \
|
||||
.timer_count = ARRAY_SIZE(flexio_spi_##n.timerIndex) \
|
||||
} \
|
||||
}; \
|
||||
\
|
||||
static const struct spi_mcux_flexio_config spi_mcux_flexio_config_##n = { \
|
||||
.flexio_spi = &flexio_spi_##n, \
|
||||
.flexio_dev = DEVICE_DT_GET(DT_INST_PARENT(n)), \
|
||||
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
|
||||
.child = &nxp_flexio_spi_child_##n, \
|
||||
}; \
|
||||
\
|
||||
static struct spi_mcux_flexio_data spi_mcux_flexio_data_##n = { \
|
||||
SPI_CONTEXT_INIT_LOCK(spi_mcux_flexio_data_##n, ctx), \
|
||||
SPI_CONTEXT_INIT_SYNC(spi_mcux_flexio_data_##n, ctx), \
|
||||
SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
|
||||
}; \
|
||||
\
|
||||
DEVICE_DT_INST_DEFINE(n, &spi_mcux_init, NULL, \
|
||||
&spi_mcux_flexio_data_##n, \
|
||||
&spi_mcux_flexio_config_##n, POST_KERNEL, \
|
||||
CONFIG_SPI_INIT_PRIORITY, \
|
||||
&spi_mcux_driver_api); \
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(SPI_MCUX_FLEXIO_SPI_INIT)
|
||||
27
dts/bindings/spi/nxp,flexio-spi.yaml
Normal file
27
dts/bindings/spi/nxp,flexio-spi.yaml
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# Copyright (c) 2024, STRIM, ALC
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP FlexIO SPI controller
|
||||
|
||||
compatible: "nxp,flexio-spi"
|
||||
|
||||
include: [spi-controller.yaml, "pinctrl-device.yaml"]
|
||||
|
||||
properties:
|
||||
sdo-pin:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Pin select for data output.
|
||||
|
||||
sdi-pin:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Pin select for data input.
|
||||
|
||||
sck-pin:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Pin select for clock.
|
||||
Loading…
Reference in a new issue