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kconfig: untangle ordering and dependencies

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There are two major issues with the kconfig:

() Some of the config options have incorrect dependencies inside help
   under menuconfig. For example, CONFIG_GPIO depends on BOARD_GALILEO.

() Since the SoC and board specific kconfig files are parsed first,
   the help screen would say, for example, CONFIG_SPI is defined at
   arch/arm/soc/fsl_frdm_k64f/Kconfig. This is incorrect because
   the actual config is defined in drivers/spi/Kconfig.

These cause great confusion to users of menuconfig/xconfig.

To fix these, the SoC and board defaults are now to be parsed last.

Note that the position swapping of defaults in this patch is due to
the fact the the default parsed last will be used.

And, spi_test is broken due to the fact that it requires
CONFIG_SPI_INTEL_PORT_1, but never enables it anywhere. This is
bypassed for now.

Origin: refactored and edited from existing files
Change-Id: I2a4b1ae5be4d27e68c960aa47d91ef350f2d500f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2016-03-25 14:30:50 -07:00 committed by Anas Nashif
parent c6390d559f
commit 8df10d4584
42 changed files with 1287 additions and 934 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
Kconfig.zephyr
View file

@ -2,6 +2,7 @@
#
# Copyright (c) 2014-2015 Wind River Systems, Inc.
# Copyright (c) 2016 Intel Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@ -29,3 +30,12 @@ source "net/Kconfig"
source "misc/Kconfig"
#
# The following are for Kconfig files for default values only.
# These should be parsed at the end.
#
# Board defaults should be parsed before SoC defaults
# because board usually overrides them.
#
source "boards/*/Kconfig.defconfig"
source "arch/*/soc/*/Kconfig.defconfig"

47
arch/arc/soc/quark_se_ss/Kconfig → arch/arc/soc/quark_se_ss/Kconfig.defconfig
View file

@ -1,5 +1,6 @@
#
# Copyright (c) 2014 Wind River Systems, Inc.
# Copyright (c) 2015-2016 Intel Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@ -45,13 +46,20 @@ config RAM_SIZE
default 24
if GPIO
config GPIO_DW
def_bool y
if GPIO_DW
config GPIO_DW_BOTHEDGES_SUPPORT
default n
config GPIO_DW_0
def_bool y
if GPIO_DW_0
config GPIO_DW_0_BASE_ADDR
default 0x80017800
config GPIO_DW_0_IRQ
@ -61,8 +69,13 @@ config GPIO_DW_0_PRI
config GPIO_DW_0_BITS
default 8
endif # GPIO_DW_0
config GPIO_DW_1
def_bool y
if GPIO_DW_1
config GPIO_DW_1_BASE_ADDR
default 0x80017900
config GPIO_DW_1_IRQ
@ -71,13 +84,20 @@ config GPIO_DW_1_PRI
default 2
config GPIO_DW_1_BITS
default 8
endif
endif # GPIO_DW_1
endif # GPIO_DW
endif # GPIO
if I2C
config I2C_QUARK_SE_SS
def_bool y
if I2C_QUARK_SE_SS
config I2C_QUARK_SE_SS_0
def_bool y
@ -92,7 +112,7 @@ config I2C_QUARK_SE_SS_0_NAME
config I2C_QUARK_SE_SS_0_DEFAULT_CFG
default 0x12
endif
endif # I2C_QUARK_SE_SS_0
if I2C_QUARK_SE_SS_1
@ -105,7 +125,9 @@ config I2C_QUARK_SE_SS_1_NAME
config I2C_QUARK_SE_SS_1_DEFAULT_CFG
default 0x12
endif
endif # I2C_QUARK_SE_SS_1
endif # I2C_QUARK_SE_SS
endif # I2C
@ -165,13 +187,20 @@ config UART_CONSOLE_ON_DEV_NAME
endif
if SPI
config SPI_DW
def_bool y
if SPI_DW
config SPI_DW_CLOCK_GATE
def_bool n
config SPI_DW_PORT_0
def_bool y
if SPI_DW_PORT_0
config SPI_DW_PORT_0_PRI
default 1
config SPI_DW_PORT_0_REGS
@ -183,8 +212,13 @@ config SPI_DW_PORT_0_RX_IRQ
config SPI_DW_PORT_0_TX_IRQ
default 32
endif # SPI_DW_PORT_0
config SPI_DW_PORT_1
def_bool y
if SPI_DW_PORT_1
config SPI_DW_PORT_1_PRI
default 1
config SPI_DW_PORT_1_REGS
@ -195,7 +229,12 @@ config SPI_DW_PORT_1_RX_IRQ
default 34
config SPI_DW_PORT_1_TX_IRQ
default 35
endif
endif # SPI_DW_PORT_1
endif # SPI_DW
endif # SPI
config KERNEL_INIT_PRIORITY_DEFAULT
default 40

101
arch/arm/soc/atmel_sam3/Kconfig
View file

@ -19,55 +19,10 @@
config SOC_ATMEL_SAM3
bool
depends on ARM
default n
if SOC_ATMEL_SAM3
config SOC
default atmel_sam3
config NUM_IRQ_PRIO_BITS
int
default 3
#
# SAM3X8E has total 45 peripherals capable of
# generating interrupts.
#
config NUM_IRQS
int
default 45
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 84000000
#
# SRAM address depends on the processor.
#
# SAM3X8E has two SRAM banks:
# 64K @ 0x20000000
# 32K @ 0x20080000
# The first 64K is mirrored at 0x20070000
# to provide one continuous 96K block.
#
config SRAM_SIZE
default 96 if SOC_ATMEL_SAM3X8E
config SRAM_BASE_ADDRESS
default 0x20000000 if !SOC_ATMEL_SAM3X8E
default 0x20070000 if SOC_ATMEL_SAM3X8E
#
# Atmel SAM3 family has flash starting @ 0x00080000.
#
# SAM3X8E has 512K of flash.
#
config FLASH_SIZE
default 512 if SOC_ATMEL_SAM3X8E
config FLASH_BASE_ADDRESS
default 0x00080000
if ARM && SOC_ATMEL_SAM3
config SOC_ATMEL_SAM3_EXT_SLCK
bool "Atmel SAM3 to use external crystal oscillator for slow clock"
@ -125,56 +80,4 @@ config SOC_ATMEL_SAM3_PLLA_DIVA
With default of MULA == 6, and DIVA == 1,
PLL is running at 7 times of main clock.
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
if UART_ATMEL_SAM3
config UART_ATMEL_SAM3_BAUD_RATE
default 115200
config UART_ATMEL_SAM3_CLK_FREQ
default 84000000
endif # UART_ATMEL_SAM3
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME
default "UART_0"
endif # UART_CONSOLE
if GPIO_ATMEL_SAM3
config GPIO_ATMEL_SAM3_PORTA
default y
config GPIO_ATMEL_SAM3_PORTB
default y
config GPIO_ATMEL_SAM3_PORTC
default y
config GPIO_ATMEL_SAM3_PORTD
default y
endif # GPIO_ATMEL_SAM3
if I2C_ATMEL_SAM3
config I2C_ATMEL_SAM3_0
default y
config I2C_ATMEL_SAM3_1
default y
endif # I2C_ATMEL_SAM3
endif # SOC_ATMEL_SAM3

116
arch/arm/soc/atmel_sam3/Kconfig.defconfig Normal file
View file

@ -0,0 +1,116 @@
# Kconfig - Atmel SAM3 family processor configuration options
#
# Copyright (c) 2016 Intel Corporation.
# Copyright (c) 2014-2015 Wind River Systems, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_ATMEL_SAM3
config SOC
default atmel_sam3
config NUM_IRQ_PRIO_BITS
int
default 3
#
# SAM3X8E has total 45 peripherals capable of
# generating interrupts.
#
config NUM_IRQS
int
default 45
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 84000000
#
# SRAM address depends on the processor.
#
# SAM3X8E has two SRAM banks:
# 64K @ 0x20000000
# 32K @ 0x20080000
# The first 64K is mirrored at 0x20070000
# to provide one continuous 96K block.
#
config SRAM_SIZE
default 96 if SOC_ATMEL_SAM3X8E
config SRAM_BASE_ADDRESS
default 0x20000000 if !SOC_ATMEL_SAM3X8E
default 0x20070000 if SOC_ATMEL_SAM3X8E
#
# Atmel SAM3 family has flash starting @ 0x00080000.
#
# SAM3X8E has 512K of flash.
#
config FLASH_SIZE
default 512 if SOC_ATMEL_SAM3X8E
config FLASH_BASE_ADDRESS
default 0x00080000
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
if UART_ATMEL_SAM3
config UART_ATMEL_SAM3_BAUD_RATE
default 115200
config UART_ATMEL_SAM3_CLK_FREQ
default 84000000
endif # UART_ATMEL_SAM3
config UART_CONSOLE_ON_DEV_NAME
default "UART_0" if UART_CONSOLE
if GPIO_ATMEL_SAM3
config GPIO_ATMEL_SAM3_PORTA
default y
config GPIO_ATMEL_SAM3_PORTB
default y
config GPIO_ATMEL_SAM3_PORTC
default y
config GPIO_ATMEL_SAM3_PORTD
default y
endif # GPIO_ATMEL_SAM3
if I2C_ATMEL_SAM3
config I2C_ATMEL_SAM3_0
default y
config I2C_ATMEL_SAM3_1
default y
endif # I2C_ATMEL_SAM3
endif # SOC_ATMEL_SAM3

270
arch/arm/soc/fsl_frdm_k64f/Kconfig
View file

@ -17,27 +17,6 @@
#
if SOC_FSL_FRDM_K64F
config SOC
default fsl_frdm_k64f
config SRAM_BASE_ADDRESS
default 0x20000000
config FLASH_BASE_ADDRESS
default 0x00000000
config NUM_IRQ_PRIO_BITS
int
default 4
config NUM_IRQS
int
# must be >= the highest interrupt number used
default 86
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 120000000
config K64_CORE_CLOCK_DIVIDER
int
@ -79,214 +58,6 @@ config WDOG_INIT
upon reset. Therefore, this requires that the watchdog be configured
during reset handling.
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
if UART_K20
config UART_K20_PORT_0
def_bool y
if UART_K20_PORT_0
config UART_K20_PORT_0_BASE_ADDR
default 0x4006A000
config UART_K20_PORT_0_IRQ
default 31
config UART_K20_PORT_0_IRQ_PRI
default 3
config UART_K20_PORT_0_BAUD_RATE
default 115200
config UART_K20_PORT_0_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_1
def_bool y
if UART_K20_PORT_1
config UART_K20_PORT_1_BASE_ADDR
default 0x4006B000
config UART_K20_PORT_1_IRQ
default 33
config UART_K20_PORT_1_IRQ_PRI
default 3
config UART_K20_PORT_1_BAUD_RATE
default 115200
config UART_K20_PORT_1_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_2
def_bool y
if UART_K20_PORT_2
config UART_K20_PORT_2_BASE_ADDR
default 0x4006C000
config UART_K20_PORT_2_IRQ
default 35
config UART_K20_PORT_2_IRQ_PRI
default 3
config UART_K20_PORT_2_BAUD_RATE
default 115200
config UART_K20_PORT_2_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_3
def_bool y
if UART_K20_PORT_3
config UART_K20_PORT_3_BASE_ADDR
default 0x4006D000
config UART_K20_PORT_3_IRQ
default 37
config UART_K20_PORT_3_IRQ_PRI
default 3
config UART_K20_PORT_3_BAUD_RATE
default 115200
config UART_K20_PORT_3_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_4
def_bool y
if UART_K20_PORT_4
config UART_K20_PORT_4_BASE_ADDR
default 0x400EA000
config UART_K20_PORT_4_IRQ
default 66
config UART_K20_PORT_4_IRQ_PRI
default 3
config UART_K20_PORT_4_BAUD_RATE
default 115200
config UART_K20_PORT_4_CLK_FREQ
default 120000000
endif
endif # UART_K20
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME
default "UART_0"
endif
if BLUETOOTH_UART
config BLUETOOTH_UART_ON_DEV_NAME
default "UART_1"
endif
config GPIO
def_bool y
config PINMUX
def_bool y
if GPIO
config GPIO_K64
def_bool y
if GPIO_K64
config GPIO_K64_A
def_bool y
config GPIO_K64_B
def_bool y
config GPIO_K64_C
def_bool y
config GPIO_K64_D
def_bool y
config GPIO_K64_E
def_bool y
endif # GPIO_K64
if GPIO_K64_A
config GPIO_K64_A_BASE_ADDR
default 0x400FF000
config PORT_K64_A_BASE_ADDR
default 0x40049000
endif # GPIO_K64_A
if GPIO_K64_B
config GPIO_K64_B_BASE_ADDR
default 0x400FF040
config PORT_K64_B_BASE_ADDR
default 0x4004A000
endif # GPIO_K64_B
if GPIO_K64_C
config GPIO_K64_C_BASE_ADDR
default 0x400FF080
config PORT_K64_C_BASE_ADDR
default 0x4004B000
endif # GPIO_K64_C
if GPIO_K64_D
config GPIO_K64_D_BASE_ADDR
default 0x400FF0C0
config PORT_K64_D_BASE_ADDR
default 0x4004C000
endif # GPIO_K64_D
if GPIO_K64_E
config GPIO_K64_E_BASE_ADDR
default 0x400FF100
config PORT_K64_E_BASE_ADDR
default 0x4004D000
endif # GPIO_K64_E
endif # if GPIO
if PINMUX
config PINMUX_K64
def_bool y
config PINMUX_BASE
default 0x00000000
config PINMUX_NUM_PINS
default 160
if PINMUX_K64
config PINMUX_K64_GPIO_A_NAME
default GPIO_K64_A_DEV_NAME
config PINMUX_K64_GPIO_B_NAME
default GPIO_K64_B_DEV_NAME
config PINMUX_K64_GPIO_C_NAME
default GPIO_K64_C_DEV_NAME
config PINMUX_K64_GPIO_D_NAME
default GPIO_K64_D_DEV_NAME
config PINMUX_K64_GPIO_E_NAME
default GPIO_K64_E_DEV_NAME
config PRESERVE_JTAG_IO_PINS
bool "Freescale FRDM-K64F JTAG pin usage"
depends on PINMUX
@ -297,45 +68,4 @@ config PRESERVE_JTAG_IO_PINS
the Arduino header as D8, D3 and D5, respectively.
Enable this option to preserve these pins for the debug interface.
endif # PINMUX_K64
endif # PINMUX
if PWM
config PWM_K64_FTM
def_bool y
if PWM_K64_FTM
config PWM_K64_FTM_0
def_bool y
endif # PWM_K64_FTM
endif
config SPI
def_bool n
if SPI
config SPI_K64
def_bool y
if SPI_K64
config SPI_K64_0
def_bool y
config SPI_K64_1
def_bool n
config SPI_K64_2
def_bool n
endif # SPI_K64
endif
endif # SOC_FSL_FRDM_K64F

284
arch/arm/soc/fsl_frdm_k64f/Kconfig.defconfig Normal file
View file

@ -0,0 +1,284 @@
# Kconfig - FSL FRDM K64F platform configuration options
#
# Copyright (c) 2014-2016 Wind River Systems, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_FSL_FRDM_K64F
config SOC
default fsl_frdm_k64f
config SRAM_BASE_ADDRESS
default 0x20000000
config FLASH_BASE_ADDRESS
default 0x00000000
config NUM_IRQ_PRIO_BITS
int
default 4
config NUM_IRQS
int
# must be >= the highest interrupt number used
default 86
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 120000000
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
if UART_K20
config UART_K20_PORT_0
def_bool y
if UART_K20_PORT_0
config UART_K20_PORT_0_BASE_ADDR
default 0x4006A000
config UART_K20_PORT_0_IRQ
default 31
config UART_K20_PORT_0_IRQ_PRI
default 3
config UART_K20_PORT_0_BAUD_RATE
default 115200
config UART_K20_PORT_0_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_1
def_bool y
if UART_K20_PORT_1
config UART_K20_PORT_1_BASE_ADDR
default 0x4006B000
config UART_K20_PORT_1_IRQ
default 33
config UART_K20_PORT_1_IRQ_PRI
default 3
config UART_K20_PORT_1_BAUD_RATE
default 115200
config UART_K20_PORT_1_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_2
def_bool y
if UART_K20_PORT_2
config UART_K20_PORT_2_BASE_ADDR
default 0x4006C000
config UART_K20_PORT_2_IRQ
default 35
config UART_K20_PORT_2_IRQ_PRI
default 3
config UART_K20_PORT_2_BAUD_RATE
default 115200
config UART_K20_PORT_2_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_3
def_bool y
if UART_K20_PORT_3
config UART_K20_PORT_3_BASE_ADDR
default 0x4006D000
config UART_K20_PORT_3_IRQ
default 37
config UART_K20_PORT_3_IRQ_PRI
default 3
config UART_K20_PORT_3_BAUD_RATE
default 115200
config UART_K20_PORT_3_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_4
def_bool y
if UART_K20_PORT_4
config UART_K20_PORT_4_BASE_ADDR
default 0x400EA000
config UART_K20_PORT_4_IRQ
default 66
config UART_K20_PORT_4_IRQ_PRI
default 3
config UART_K20_PORT_4_BAUD_RATE
default 115200
config UART_K20_PORT_4_CLK_FREQ
default 120000000
endif
endif # UART_K20
config UART_CONSOLE_ON_DEV_NAME
default "UART_0" if UART_CONSOLE
config BLUETOOTH_UART_ON_DEV_NAME
default "UART_1" if BLUETOOTH_UART
config GPIO
def_bool y
config PINMUX
def_bool y
if GPIO
config GPIO_K64
def_bool y
if GPIO_K64
config GPIO_K64_A
def_bool y
config GPIO_K64_B
def_bool y
config GPIO_K64_C
def_bool y
config GPIO_K64_D
def_bool y
config GPIO_K64_E
def_bool y
if GPIO_K64_A
config GPIO_K64_A_BASE_ADDR
default 0x400FF000
config PORT_K64_A_BASE_ADDR
default 0x40049000
endif # GPIO_K64_A
if GPIO_K64_B
config GPIO_K64_B_BASE_ADDR
default 0x400FF040
config PORT_K64_B_BASE_ADDR
default 0x4004A000
endif # GPIO_K64_B
if GPIO_K64_C
config GPIO_K64_C_BASE_ADDR
default 0x400FF080
config PORT_K64_C_BASE_ADDR
default 0x4004B000
endif # GPIO_K64_C
if GPIO_K64_D
config GPIO_K64_D_BASE_ADDR
default 0x400FF0C0
config PORT_K64_D_BASE_ADDR
default 0x4004C000
endif # GPIO_K64_D
if GPIO_K64_E
config GPIO_K64_E_BASE_ADDR
default 0x400FF100
config PORT_K64_E_BASE_ADDR
default 0x4004D000
endif # GPIO_K64_E
endif # GPIO_K64
endif # GPIO
if PINMUX
config PINMUX_K64
def_bool y
config PINMUX_BASE
default 0x00000000
config PINMUX_NUM_PINS
default 160
if PINMUX_K64
config PINMUX_K64_GPIO_A_NAME
default GPIO_K64_A_DEV_NAME
config PINMUX_K64_GPIO_B_NAME
default GPIO_K64_B_DEV_NAME
config PINMUX_K64_GPIO_C_NAME
default GPIO_K64_C_DEV_NAME
config PINMUX_K64_GPIO_D_NAME
default GPIO_K64_D_DEV_NAME
config PINMUX_K64_GPIO_E_NAME
default GPIO_K64_E_DEV_NAME
endif # PINMUX_K64
endif # PINMUX
if PWM
config PWM_K64_FTM
def_bool y
if PWM_K64_FTM
config PWM_K64_FTM_0
def_bool y
endif # PWM_K64_FTM
endif
config SPI
def_bool n
if SPI
config SPI_K64
def_bool y
if SPI_K64
config SPI_K64_0
def_bool y
config SPI_K64_1
def_bool n
config SPI_K64_2
def_bool n
endif # SPI_K64
endif # SPI
endif # SOC_FSL_FRDM_K64F

1
arch/arm/soc/st_stm32/Kconfig.defconfig Normal file
View file

@ -0,0 +1 @@
source "arch/arm/soc/st_stm32/*/Kconfig.defconfig.family"

51
arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.family Normal file
View file

@ -0,0 +1,51 @@
# Kconfig - ST Microelectronics STM32F1 MCU line
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_STM32F1X
source "arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f1*"
config SOC
default st_stm32/stm32f1
config SRAM_BASE_ADDRESS
default 0x20000000
config FLASH_BASE_ADDRESS
default 0x08000000
config NUM_IRQ_PRIO_BITS
int
default 4
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
if UART_CONSOLE
config UART_CONSOLE_PRIORITY
default 60
config UART_CONSOLE_ON_DEV_NAME
default "UART_0"
endif # UART_CONSOLE
endif # SOC_STM32F1X

0
arch/arm/soc/st_stm32/stm32f1/Kconfig.soc.stm32f103rb → arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103rb
View file

0
arch/arm/soc/st_stm32/stm32f1/Kconfig.soc.stm32f103ve → arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103ve
View file

36
arch/arm/soc/st_stm32/stm32f1/Kconfig.soc.family
View file

@ -26,39 +26,3 @@ config SOC_STM32F103RB
bool "STM32F103RB"
endchoice
if SOC_STM32F1X
source "arch/arm/soc/st_stm32/stm32f1/Kconfig.soc.stm32f1*"
config SOC
default st_stm32/stm32f1
config SRAM_BASE_ADDRESS
default 0x20000000
config FLASH_BASE_ADDRESS
default 0x08000000
config NUM_IRQ_PRIO_BITS
int
default 4
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME
default "UART_0"
endif # UART_CONSOLE
endif # SOC_STM32F1X

108
arch/arm/soc/ti_lm3s6965/Kconfig
View file

@ -17,116 +17,10 @@
#
if SOC_TI_LM3S6965
config SOC
default ti_lm3s6965
config SRAM_BASE_ADDRESS
default 0x20000000
config FLASH_BASE_ADDRESS
default 0x00000000
config NUM_IRQ_PRIO_BITS
int
default 3
config NUM_IRQS
int
# must be >= the highest interrupt number used
# - include the UART interrupts
default 34
config SOC_TI_LM3S6965_QEMU
def_bool y
# Platform has only been tested on QEMU, not on real hardware, so always
# assume it is used for a QEMU target.
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 12000000
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
config IPM_CONSOLE_PRIORITY
default 60
if UART_STELLARIS
config UART_STELLARIS_PORT_0
def_bool y
if UART_STELLARIS_PORT_0
config UART_STELLARIS_PORT_0_BASE_ADDR
default 0x4000C000
config UART_STELLARIS_PORT_0_IRQ
default 5
config UART_STELLARIS_PORT_0_IRQ_PRI
default 3
config UART_STELLARIS_PORT_0_BAUD_RATE
default 115200
config UART_STELLARIS_PORT_0_CLK_FREQ
default 12000000
endif
config UART_STELLARIS_PORT_1
def_bool y
if UART_STELLARIS_PORT_1
config UART_STELLARIS_PORT_1_BASE_ADDR
default 0x4000D000
config UART_STELLARIS_PORT_1_IRQ
default 6
config UART_STELLARIS_PORT_1_IRQ_PRI
default 3
config UART_STELLARIS_PORT_1_BAUD_RATE
default 115200
config UART_STELLARIS_PORT_1_CLK_FREQ
default 12000000
endif
config UART_STELLARIS_PORT_2
def_bool y
if UART_STELLARIS_PORT_2
config UART_STELLARIS_PORT_2_BASE_ADDR
default 0x4000E000
config UART_STELLARIS_PORT_2_IRQ
default 33
config UART_STELLARIS_PORT_2_IRQ_PRI
default 3
config UART_STELLARIS_PORT_2_BAUD_RATE
default 115200
config UART_STELLARIS_PORT_2_CLK_FREQ
default 12000000
endif
endif # UART_STELLARIS
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME
default "UART_0"
endif
if BLUETOOTH_UART
config BLUETOOTH_UART_ON_DEV_NAME
default "UART_1"
endif
if UART_PIPE
config UART_PIPE_ON_DEV_NAME
default "UART_2"
endif
endif
endif # SOC_TI_LM3S6965

113
arch/arm/soc/ti_lm3s6965/Kconfig.defconfig Normal file
View file

@ -0,0 +1,113 @@
# Kconfig - TI LM3S6965 platform configuration options
#
# Copyright (c) 2014-2015 Wind River Systems, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_TI_LM3S6965
config SOC
default ti_lm3s6965
config SRAM_BASE_ADDRESS
default 0x20000000
config FLASH_BASE_ADDRESS
default 0x00000000
config NUM_IRQ_PRIO_BITS
int
default 3
config NUM_IRQS
int
# must be >= the highest interrupt number used
# - include the UART interrupts
default 34
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 12000000
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
if UART_STELLARIS
config UART_STELLARIS_PORT_0
def_bool y
if UART_STELLARIS_PORT_0
config UART_STELLARIS_PORT_0_BASE_ADDR
default 0x4000C000
config UART_STELLARIS_PORT_0_IRQ
default 5
config UART_STELLARIS_PORT_0_IRQ_PRI
default 3
config UART_STELLARIS_PORT_0_BAUD_RATE
default 115200
config UART_STELLARIS_PORT_0_CLK_FREQ
default 12000000
endif
config UART_STELLARIS_PORT_1
def_bool y
if UART_STELLARIS_PORT_1
config UART_STELLARIS_PORT_1_BASE_ADDR
default 0x4000D000
config UART_STELLARIS_PORT_1_IRQ
default 6
config UART_STELLARIS_PORT_1_IRQ_PRI
default 3
config UART_STELLARIS_PORT_1_BAUD_RATE
default 115200
config UART_STELLARIS_PORT_1_CLK_FREQ
default 12000000
endif
config UART_STELLARIS_PORT_2
def_bool y
if UART_STELLARIS_PORT_2
config UART_STELLARIS_PORT_2_BASE_ADDR
default 0x4000E000
config UART_STELLARIS_PORT_2_IRQ
default 33
config UART_STELLARIS_PORT_2_IRQ_PRI
default 3
config UART_STELLARIS_PORT_2_BAUD_RATE
default 115200
config UART_STELLARIS_PORT_2_CLK_FREQ
default 12000000
endif
endif # UART_STELLARIS
config UART_CONSOLE_ON_DEV_NAME
default "UART_0" if UART_CONSOLE
config BLUETOOTH_UART_ON_DEV_NAME
default "UART_1" if BLUETOOTH_UART
config UART_PIPE_ON_DEV_NAME
default "UART_2" if UART_PIPE
endif

2
arch/x86/Kconfig
View file

@ -277,7 +277,7 @@ config IRQ_OFFLOAD
config IRQ_OFFLOAD_VECTOR
int "IDT vector to use for IRQ offload"
default 63 if MVIC
default 32
default 32 if !MVIC
range 32 255
depends on IRQ_OFFLOAD
help

0
arch/x86/soc/atom/Kconfig → arch/x86/soc/atom/Kconfig.defconfig
View file

0
arch/x86/soc/ia32/Kconfig → arch/x86/soc/ia32/Kconfig.defconfig
View file

13
arch/x86/soc/quark_d2000/Kconfig → arch/x86/soc/quark_d2000/Kconfig.defconfig
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2015 Intel Corp.
# Copyright (c) 2015-2016 Intel Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@ -15,6 +15,7 @@
#
if SOC_QUARK_D2000
config SOC
default quark_d2000
@ -61,11 +62,13 @@ config UART_CONSOLE_PRIORITY
default 60
if PINMUX
config PINMUX_BASE
default 0xb0800900
config PINMUX_NUM_PINS
default 25
endif # PINMUX
if UART_NS16550
@ -195,13 +198,17 @@ endif # RTC_DW
endif # RTC
if I2C
config I2C_DW
def_bool y
if I2C_DW
config I2C_DW_0
def_bool y
if I2C_DW_0
config I2C_DW_0_BASE
default 0xb0002800
@ -220,7 +227,9 @@ config I2C_DW_0_DEFAULT_CFG
config I2C_CLOCK_SPEED
default 32
endif
endif # I2C_DW_0
endif # I2C_DW
if I2C_QMSI
config I2C_QMSI_0

381
arch/x86/soc/quark_se/Kconfig
View file

@ -1,7 +1,7 @@
# Kconfig - Quark SE configuration options
#
# Copyright (c) 2015 Intel Corp.
# Copyright (c) 2016 Intel Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@ -16,30 +16,7 @@
# limitations under the License.
#
if SOC_QUARK_SE
config SOC
default quark_se
config PHYS_RAM_ADDR
default 0xA8006400
config PHYS_LOAD_ADDR
default 0x40030000 if XIP
config RAM_SIZE
default 55
config ROM_SIZE
default 144
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32000000
config IOAPIC_NUM_RTES
default 64
config LOAPIC_TIMER_IRQ
default 64
if X86 && SOC_QUARK_SE
config EOI_FORWARDING_BUG
bool
@ -48,21 +25,6 @@ config EOI_FORWARDING_BUG
Quark SE LOAPIC has issues with forwarding EOI to the IOAPIC for level
triggered interrupts, this is a SW workaround.
config TOOLCHAIN_VARIANT
default "iamcu"
if PINMUX
config PINMUX_BASE
default 0xb0800900
endif
config AIO_DW_COMPARATOR_BASE_ADDR
hex
depends on AIO_DW_COMPARATOR
default 0xb0800300
config ARC_INIT
bool "Quark SE ARC Kickoff"
default n
@ -78,345 +40,6 @@ config ARC_INIT_DEBUG
the ARC slave processor. This will allow GDB to halt and
engage the ARC processor to proceed step by step execution.
if GPIO
config GPIO_DW
def_bool y
if GPIO_DW
config GPIO_DW_BOTHEDGES_SUPPORT
def_bool y
config GPIO_DW_CLOCK_GATE
def_bool n
config GPIO_DW_CLOCK_GATE_DRV_NAME
default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
config GPIO_DW_0
def_bool y
config GPIO_DW_0_BASE_ADDR
default 0xb0000C00
config GPIO_DW_0_IRQ
default 8
config GPIO_DW_0_PRI
default 2
config GPIO_DW_0_BITS
default 32
config GPIO_DW_0_CLOCK_GATE_SUBSYS
default 13
depends on GPIO_DW_CLOCK_GATE
config GPIO_DW_1
def_bool y
config GPIO_DW_1_BASE_ADDR
default 0xb0800b00
config GPIO_DW_1_IRQ
default 31
config GPIO_DW_1_PRI
default 2
config GPIO_DW_1_BITS
default 6
endif
if QMSI_DRIVERS
config GPIO_QMSI
def_bool n
if GPIO_QMSI
config GPIO_QMSI_0
def_bool n
config GPIO_QMSI_0_IRQ
default 8
config GPIO_QMSI_0_PRI
default 2
config GPIO_QMSI_AON
def_bool n
config GPIO_QMSI_AON_NAME
default "gpio_aon"
config GPIO_QMSI_AON_IRQ
default 31
config GPIO_QMSI_AON_PRI
default 2
endif
endif
endif
if I2C
config I2C_DW
def_bool y
if I2C_DW
config I2C_DW_0
def_bool y
config I2C_DW_0_BASE
default 0xb0002800
config I2C_DW_0_NAME
default "I2C0"
config I2C_DW_0_IRQ
default 0
config I2C_DW_0_INT_PRIORITY
default 2
config I2C_DW_1
def_bool y
config I2C_DW_1_BASE
default 0xb0002c00
config I2C_DW_1_NAME
default "I2C1"
config I2C_DW_1_IRQ
default 1
config I2C_DW_1_INT_PRIORITY
default 2
endif # I2C_DW
if I2C_QMSI
config I2C_QMSI_0
def_bool y
config I2C_QMSI_0_IRQ
default 0
config I2C_QMSI_0_INT_PRIORITY
default 2
config I2C_QMSI_1
def_bool y
config I2C_QMSI_1_IRQ
default 1
config I2C_QMSI_1_INT_PRIORITY
default 2
endif # I2C_QMSI
endif # I2C
if CLOCK_CONTROL
config CLOCK_CONTROL_QUARK_SE
def_bool y
if CLOCK_CONTROL_QUARK_SE
config CLOCK_CONTROL_QUARK_SE_PERIPHERAL
def_bool y
config CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
default "clk_peripheral"
config CLOCK_CONTROL_QUARK_SE_EXTERNAL
def_bool y
config CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME
default "clk_external"
config CLOCK_CONTROL_QUARK_SE_SENSOR
def_bool y
config CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME
default "clk_sensor"
endif # CLOCK_CONTROL_QUARK_SE
endif
if SPI
config SPI_DW
def_bool y
if SPI_DW
config SPI_DW_CLOCK_GATE
def_bool n
config SPI_DW_CLOCK_GATE_DRV_NAME
default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
config SPI_DW_PORT_0
def_bool y
config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
default 14
depends on SPI_DW_CLOCK_GATE
config SPI_DW_PORT_0_REGS
default 0xb0001000
config SPI_DW_PORT_0_IRQ
default 2
config SPI_DW_PORT_0_PRI
default 2
config SPI_DW_PORT_1
def_bool y
config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
default 15
depends on SPI_DW_CLOCK_GATE
config SPI_DW_PORT_1_REGS
default 0xb0001400
config SPI_DW_PORT_1_IRQ
default 3
config SPI_DW_PORT_1_PRI
default 2
endif # SPI_DW
config SPI_QMSI
def_bool n
if SPI_QMSI
config SPI_QMSI_PORT_0
def_bool y
config SPI_QMSI_PORT_0_IRQ
default 2
config SPI_QMSI_PORT_0_PRI
default 2
config SPI_QMSI_PORT_1
def_bool y
config SPI_QMSI_PORT_1_IRQ
default 3
config SPI_QMSI_PORT_1_PRI
default 2
endif # SPI_QMSI
endif
if WATCHDOG
config WDT_DW
def_bool y
if WDT_DW
config WDT_DW_CLOCK_GATE
def_bool n
config WDT_DW_CLOCK_GATE_DRV_NAME
default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
config WDT_DW_CLOCK_GATE_SUBSYS
default 10
config WDT_DW_BASE_ADDR
default 0xB0000000
config WDT_DW_IRQ
default 12
config WDT_DW_IRQ_PRI
default 2
endif # WDT_DW
if WDT_QMSI
config WDT_QMSI_IRQ
default 12
config WDT_QMSI_IRQ_PRI
default 2
endif # WDT_QMSI
endif # WATCHDOG
if RTC
config RTC_IRQ
default 11
config RTC_IRQ_PRI
default 2
config RTC_DW
def_bool y
if RTC_DW
config RTC_DW_CLOCK_GATE
def_bool y
config RTC_DW_CLOCK_GATE_DRV_NAME
default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
config RTC_DW_CLOCK_GATE_SUBSYS
default 11
config RTC_DW_BASE_ADDR
default 0xB0000400
endif # RTC_DW
endif # RTC
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
config IPM_CONSOLE_PRIORITY
default 60
config GPIO_DW_INIT_PRIORITY
default 60
config I2C_INIT_PRIORITY
default 60
config SPI_DW_INIT_PRIORITY
default 70 # It might require GPIO to be ready first
if UART_NS16550
config UART_NS16550_PORT_0
def_bool y
if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_NAME
default "UART_0"
config UART_NS16550_PORT_0_BASE_ADDR
default 0xB0002000
config UART_NS16550_PORT_0_IRQ
default 5
config UART_NS16550_PORT_0_IRQ_PRI
default 3
config UART_NS16550_PORT_0_BAUD_RATE
default 115200
config UART_NS16550_PORT_0_CLK_FREQ
default 32000000
config UART_NS16550_PORT_0_OPTIONS
default 0
endif # UART_NS16550_PORT_0
config UART_NS16550_PORT_1
def_bool y
if UART_NS16550_PORT_1
config UART_NS16550_PORT_1_NAME
default "UART_1"
config UART_NS16550_PORT_1_BASE_ADDR
default 0xB0002400
config UART_NS16550_PORT_1_IRQ
default 6
config UART_NS16550_PORT_1_IRQ_PRI
default 3
config UART_NS16550_PORT_1_BAUD_RATE
default 115200
config UART_NS16550_PORT_1_CLK_FREQ
default 32000000
config UART_NS16550_PORT_1_OPTIONS
default 0
endif # UART_NS16550_PORT_1
endif # UART_NS16550
if UART_QMSI
config UART_QMSI_0
def_bool y
config UART_QMSI_0_IRQ
default 5
config UART_QMSI_0_IRQ_PRI
default 3
config UART_QMSI_1
def_bool y
config UART_QMSI_1_IRQ
default 6
config UART_QMSI_1_IRQ_PRI
default 3
endif # UART_QMSI
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME
default "UART_1"
endif
if BLUETOOTH_UART
config BLUETOOTH_UART_ON_DEV_NAME
default "UART_1"
endif
if PWM
if PWM_DW
config PWM_DW_BASE_ADDR
default 0xB0000800
config PWM_DW_NUM_PORTS
default 4
endif
endif
if IPM_CONSOLE_RECEIVER
config QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32
int "IPM Console Ring Buffer Size"

496
arch/x86/soc/quark_se/Kconfig.defconfig Normal file
View file

@ -0,0 +1,496 @@
# Kconfig - Quark SE configuration options
#
# Copyright (c) 2015-2016 Intel Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_QUARK_SE
config SOC
default quark_se
config PHYS_RAM_ADDR
default 0xA8006400
config PHYS_LOAD_ADDR
default 0x40030000 if XIP
config RAM_SIZE
default 55
config ROM_SIZE
default 144
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32000000
config IOAPIC_NUM_RTES
default 64 if IOAPIC
config LOAPIC_TIMER_IRQ
default 64 if LOAPIC_TIMER
config TOOLCHAIN_VARIANT
default "iamcu"
config PINMUX_BASE
default 0xb0800900 if PINMUX
config AIO_DW_COMPARATOR_BASE_ADDR
default 0xb0800300 if AIO_COMPARATOR && AIO_DW_COMPARATOR
if GPIO
config GPIO_DW
def_bool y
if GPIO_DW
config GPIO_DW_BOTHEDGES_SUPPORT
def_bool y
config GPIO_DW_CLOCK_GATE
def_bool n
if GPIO_DW_CLOCK_GATE
config GPIO_DW_CLOCK_GATE_DRV_NAME
default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
endif # GPIO_DW_CLOCK_GATE
config GPIO_DW_0
def_bool y
if GPIO_DW_0
config GPIO_DW_0_BASE_ADDR
default 0xb0000C00
config GPIO_DW_0_IRQ
default 8
config GPIO_DW_0_PRI
default 2
config GPIO_DW_0_BITS
default 32
config GPIO_DW_0_CLOCK_GATE_SUBSYS
default 13
depends on GPIO_DW_CLOCK_GATE
endif # GPIO_DW_0
config GPIO_DW_1
def_bool y
if GPIO_DW_1
config GPIO_DW_1_BASE_ADDR
default 0xb0800b00
config GPIO_DW_1_IRQ
default 31
config GPIO_DW_1_PRI
default 2
config GPIO_DW_1_BITS
default 6
endif # GPIO_DW_1
endif # GPIO_DW
if QMSI_DRIVERS
config GPIO_QMSI
def_bool n
if GPIO_QMSI
config GPIO_QMSI_0
def_bool n
if GPIO_QMSI_0
config GPIO_QMSI_0_IRQ
default 8
config GPIO_QMSI_0_PRI
default 2
endif # GPIO_QMSI_0
config GPIO_QMSI_AON
def_bool n
config GPIO_QMSI_AON_NAME
default "gpio_aon"
config GPIO_QMSI_AON_IRQ
default 31
config GPIO_QMSI_AON_PRI
default 2
endif # GPIO_QMSI
endif # QMSI_DRIVERS
endif # GPIO
if I2C
config I2C_DW
def_bool y
if I2C_DW
config I2C_DW_0
def_bool y
if I2C_DW_0
config I2C_DW_0_BASE
default 0xb0002800
config I2C_DW_0_NAME
default "I2C0"
config I2C_DW_0_IRQ
default 0
config I2C_DW_0_INT_PRIORITY
default 2
endif # I2C_DW_0
config I2C_DW_1
def_bool y
if I2C_DW_1
config I2C_DW_1_BASE
default 0xb0002c00
config I2C_DW_1_NAME
default "I2C1"
config I2C_DW_1_IRQ
default 1
config I2C_DW_1_INT_PRIORITY
default 2
endif # I2C_DW_1
endif # I2C_DW
if I2C_QMSI
config I2C_QMSI_0
def_bool y
if I2C_QMSI_0
config I2C_QMSI_0_IRQ
default 0
config I2C_QMSI_0_INT_PRIORITY
default 2
endif # I2C_QMSI_0
config I2C_QMSI_1
def_bool y
if I2C_QMSI_1
config I2C_QMSI_1_IRQ
default 1
config I2C_QMSI_1_INT_PRIORITY
default 2
endif # I2C_QMSI_1
endif # I2C_QMSI
endif # I2C
if CLOCK_CONTROL
config CLOCK_CONTROL_QUARK_SE
def_bool y
if CLOCK_CONTROL_QUARK_SE
config CLOCK_CONTROL_QUARK_SE_PERIPHERAL
def_bool y
config CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
default "clk_peripheral"
config CLOCK_CONTROL_QUARK_SE_EXTERNAL
def_bool y
config CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME
default "clk_external"
config CLOCK_CONTROL_QUARK_SE_SENSOR
def_bool y
config CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME
default "clk_sensor"
endif # CLOCK_CONTROL_QUARK_SE
endif # CLOCK_CONTROL
if SPI
config SPI_DW
def_bool y
if SPI_DW
config SPI_DW_CLOCK_GATE
def_bool n
if SPI_DW_CLOCK_GATE
config SPI_DW_CLOCK_GATE_DRV_NAME
default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
endif # SPI_DW_CLOCK_GATE
config SPI_DW_PORT_0
def_bool y
if SPI_DW_PORT_0
config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
default 14
depends on SPI_DW_CLOCK_GATE
config SPI_DW_PORT_0_REGS
default 0xb0001000
config SPI_DW_PORT_0_IRQ
default 2
config SPI_DW_PORT_0_PRI
default 2
endif # SPI_DW_PORT_0
config SPI_DW_PORT_1
def_bool y
if SPI_DW_PORT_1
config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
default 15
depends on SPI_DW_CLOCK_GATE
config SPI_DW_PORT_1_REGS
default 0xb0001400
config SPI_DW_PORT_1_IRQ
default 3
config SPI_DW_PORT_1_PRI
default 2
endif # SPI_DW_PORT_1
endif # SPI_DW
config SPI_QMSI
def_bool n
if SPI_QMSI
config SPI_QMSI_PORT_0
def_bool y
if SPI_QMSI_PORT_0
config SPI_QMSI_PORT_0_IRQ
default 2
config SPI_QMSI_PORT_0_PRI
default 2
endif # SPI_QMSI_PORT_0
config SPI_QMSI_PORT_1
def_bool y
if SPI_QMSI_PORT_1
config SPI_QMSI_PORT_1_IRQ
default 3
config SPI_QMSI_PORT_1_PRI
default 2
endif # SPI_QMSI_PORT_1
endif # SPI_QMSI
endif # SPI
if WATCHDOG
config WDT_DW
def_bool y
if WDT_DW
config WDT_DW_CLOCK_GATE
def_bool n
config WDT_DW_CLOCK_GATE_DRV_NAME
default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
config WDT_DW_CLOCK_GATE_SUBSYS
default 10
config WDT_DW_BASE_ADDR
default 0xB0000000
config WDT_DW_IRQ
default 12
config WDT_DW_IRQ_PRI
default 2
endif # WDT_DW
if WDT_QMSI
config WDT_QMSI_IRQ
default 12
config WDT_QMSI_IRQ_PRI
default 2
endif # WDT_QMSI
endif # WATCHDOG
if RTC
config RTC_IRQ
default 11
config RTC_IRQ_PRI
default 2
config RTC_DW
def_bool y
if RTC_DW
config RTC_DW_CLOCK_GATE
def_bool y
config RTC_DW_CLOCK_GATE_DRV_NAME
default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
config RTC_DW_CLOCK_GATE_SUBSYS
default 11
config RTC_DW_BASE_ADDR
default 0xB0000400
endif # RTC_DW
endif # RTC
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
config IPM_CONSOLE_PRIORITY
default 60
config GPIO_DW_INIT_PRIORITY
default 60
config I2C_INIT_PRIORITY
default 60
config SPI_DW_INIT_PRIORITY
default 70 # It might require GPIO to be ready first
if UART_NS16550
config UART_NS16550_PORT_0
def_bool y
if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_NAME
default "UART_0"
config UART_NS16550_PORT_0_BASE_ADDR
default 0xB0002000
config UART_NS16550_PORT_0_IRQ
default 5
config UART_NS16550_PORT_0_IRQ_PRI
default 3
config UART_NS16550_PORT_0_BAUD_RATE
default 115200
config UART_NS16550_PORT_0_CLK_FREQ
default 32000000
config UART_NS16550_PORT_0_OPTIONS
default 0
endif # UART_NS16550_PORT_0
config UART_NS16550_PORT_1
def_bool y
if UART_NS16550_PORT_1
config UART_NS16550_PORT_1_NAME
default "UART_1"
config UART_NS16550_PORT_1_BASE_ADDR
default 0xB0002400
config UART_NS16550_PORT_1_IRQ
default 6
config UART_NS16550_PORT_1_IRQ_PRI
default 3
config UART_NS16550_PORT_1_BAUD_RATE
default 115200
config UART_NS16550_PORT_1_CLK_FREQ
default 32000000
config UART_NS16550_PORT_1_OPTIONS
default 0
endif # UART_NS16550_PORT_1
endif # UART_NS16550
if UART_QMSI
config UART_QMSI_0
def_bool y
if UART_QMSI_0
config UART_QMSI_0_IRQ
default 5
config UART_QMSI_0_IRQ_PRI
default 3
endif # UART_QMSI_0
config UART_QMSI_1
def_bool y
if UART_QMSI_1
config UART_QMSI_1_IRQ
default 6
config UART_QMSI_1_IRQ_PRI
default 3
endif # UART_QMSI_1
endif # UART_QMSI
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME
default "UART_1"
endif
if BLUETOOTH_UART
config BLUETOOTH_UART_ON_DEV_NAME
default "UART_1"
endif
if PWM_DW
config PWM_DW_BASE_ADDR
default 0xB0000800
config PWM_DW_NUM_PORTS
default 4
endif # PWM_DW
endif # SOC_QUARK_SE

96
arch/x86/soc/quark_x1000/Kconfig → arch/x86/soc/quark_x1000/Kconfig.defconfig
View file

@ -2,6 +2,7 @@
#
# Copyright (c) 2014-2015 Wind River Systems, Inc.
# Copyright (c) 2015-2016 Intel Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@ -17,6 +18,7 @@
#
if SOC_QUARK_X1000
config SOC
default quark_x1000
@ -39,17 +41,25 @@ config CLFLUSH_DETECT
def_bool y if CACHE_FLUSHING
if SHARED_IRQ
config SHARED_IRQ_0
def_bool y
if SHARED_IRQ_0
config SHARED_IRQ_0_NAME
default "SHARED_IRQ0"
config SHARED_IRQ_0_IRQ
default 18
config SHARED_IRQ_0_PRI
default 2
endif
endif # SHARED_IRQ_0
endif # SHARED_IRQ
if PCI_LEGACY_BRIDGE
config PCI_LEGACY_BRIDGE_BUS
default 0
config PCI_LEGACY_BRIDGE_DEV
@ -58,21 +68,31 @@ config PCI_LEGACY_BRIDGE_VENDOR_ID
default 0x8086
config PCI_LEGACY_BRIDGE_DEVICE_ID
default 0x095e
endif
endif # PCI_LEGACY_BRIDGE
if I2C
config I2C_CLOCK_SPEED
default 25
config I2C_DW
def_bool y
if I2C_DW
config I2C_DW_VENDOR_ID
default 0x8086
config I2C_DW_DEVICE_ID
default 0x934
config I2C_DW_CLASS
default 0x0C
config I2C_DW_0
def_bool y
if I2C_DW_0
config I2C_DW_0_NAME
default "I2C0"
config I2C_DW_0_DEFAULT_CFG
@ -93,44 +113,62 @@ config I2C_DW_0_BAR
default 0
config I2C_DW_0_IRQ_SHARED_NAME
default SHARED_IRQ_0_NAME if SHARED_IRQ
endif
endif # I2C_DW_0
endif # I2C_DW
endif # I2C
if GPIO
config GPIO_SCH
def_bool y
if GPIO_SCH
config GPIO_SCH_0
def_bool y
config GPIO_SCH_1
def_bool y
config GPIO_DW
def_bool y
config GPIO_DW_0
def_bool y
if GPIO_SCH_0
config GPIO_SCH_0_DEV_NAME
default "GPIO_CW"
config GPIO_SCH_0_BASE_ADDR
default 0x1080
config GPIO_SCH_0_BITS
default 2
endif
endif # GPIO_SCH_0
if GPIO_SCH_1
config GPIO_SCH_1_DEV_NAME
default "GPIO_RW"
config GPIO_SCH_1_BASE_ADDR
default 0x10A0
config GPIO_SCH_1_BITS
default 6
endif
endif # GPIO_SCH_1
endif # GPIO_SCH
config GPIO_DW
def_bool y
if GPIO_DW
config GPIO_DW_0
def_bool y
select GPIO_DW_0_IRQ_SHARED if SHARED_IRQ
if GPIO_DW_0
config GPIO_DW_0_NAME
default "GPIO_0"
config GPIO_DW_0_BUS
@ -151,18 +189,29 @@ config GPIO_DW_0_PRI
default 2
config GPIO_DW_0_IRQ_SHARED_NAME
default SHARED_IRQ_0_NAME if SHARED_IRQ
endif
endif
endif # GPIO_DW_0
endif # GPIO_DW
endif # GPIO
if SPI
config SPI_INTEL
def_bool y
if SPI_INTEL
config SPI_INTEL_CS_GPIO
def_bool y
config SPI_INTEL_PORT_0
def_bool y
if SPI_INTEL_PORT_0
config SPI_INTEL_PORT_0_DRV_NAME
default "SPI0"
config SPI_INTEL_PORT_0_BUS
@ -182,8 +231,13 @@ config SPI_INTEL_PORT_0_CS_GPIO_PORT
config SPI_INTEL_PORT_0_CS_GPIO_PIN
default 0
endif # SPI_INTEL_PORT_0
config SPI_INTEL_PORT_1
def_bool n
if SPI_INTEL_PORT_1
config SPI_INTEL_PORT_1_DRV_NAME
default "SPI1"
config SPI_INTEL_PORT_1_BUS
@ -202,12 +256,17 @@ config SPI_INTEL_PORT_1_CS_GPIO_PORT
default GPIO_DW_0_NAME
config SPI_INTEL_PORT_1_CS_GPIO_PIN
default 2
endif # SPI_INTEL_PORT_1
endif # SPI_INTEL
endif # SPI
if UART_NS16550
config UART_NS16550_PCI
def_bool y
def_bool y if PCI
config UART_NS16550_PORT_0
def_bool y
@ -248,7 +307,7 @@ config UART_NS16550_PORT_0_PCI_BAR
endif # UART_NS16550_PORT_0
config UART_NS16550_PORT_1
def_bool y
def_bool y if PCI
if UART_NS16550_PORT_1
@ -289,15 +348,22 @@ endif # UART_NS16550
if ETH_DW
config ETH_DW_0
def_bool y
if ETH_DW_0
config ETH_DW_0_BASE_ADDR
default 0x90002000
config ETH_DW_0_IRQ
default 18
config ETH_DW_0_IRQ_SHARED_NAME
default SHARED_IRQ_0_NAME if SHARED_IRQ
endif
endif # ETH_DW_0
endif # ETH_DW
config KERNEL_INIT_PRIORITY_DEFAULT
default 40

11
boards/arduino_101/Kconfig → boards/arduino_101/Kconfig.defconfig
View file

@ -25,20 +25,25 @@ if FLASH
config SPI_FLASH_W25QXXDV
def_bool y
if SPI_FLASH_W25QXXDV
config SPI_FLASH_W25QXXDV_SPI_NAME
default SPI_DW_PORT_0_DRV_NAME
config SPI_FLASH_W25QXXDV_SPI_SLAVE
default 1
endif
endif # SPI_FLASH_W25QXXDV
if COUNTER
endif # FLASH
if COUNTER && AON_TIMER_QMSI
config AON_TIMER_IRQ
default 28
config AON_TIMER_IRQ_PRI
default 2
endif
endif # COUNTER && AON_TIMER_QMSI
endif # BOARD_ARDUINO_101

0
boards/arduino_101_sss/Kconfig → boards/arduino_101_sss/Kconfig.defconfig
View file

0
boards/arduino_due/Kconfig → boards/arduino_due/Kconfig.defconfig
View file

0
boards/basic_cortex_m3/Kconfig → boards/basic_cortex_m3/Kconfig.defconfig
View file

0
boards/basic_minuteia/Kconfig → boards/basic_minuteia/Kconfig.defconfig
View file

0
boards/frdm_k64f/Kconfig → boards/frdm_k64f/Kconfig.defconfig
View file

45
boards/galileo/Kconfig → boards/galileo/Kconfig.defconfig
View file

@ -26,12 +26,14 @@ config SHARED_IRQ
def_bool y
if PINMUX
config PINMUX_BASE
default 0x00000000
config PINMUX_NUM_PINS
default 20
config PINMUX_BASE
default 0x00000000
config PINMUX_GALILEO_EXP0_NAME
default GPIO_PCAL9535A_0_DEV_NAME
config PINMUX_GALILEO_EXP1_NAME
@ -46,26 +48,39 @@ config PINMUX_GALILEO_GPIO_INTEL_CW_NAME
default GPIO_SCH_0_DEV_NAME
config PINMUX_GALILEO_GPIO_INTEL_RW_NAME
default GPIO_SCH_1_DEV_NAME
endif
endif # PINMUX
if ADC
config ADC_TI_ADC108S102
def_bool y
if ADC_TI_ADC108S102
config ADC_TI_ADC108S102_SPI_PORT_NAME
default "SPI0"
config ADC_TI_ADC108S102_SPI_CONFIGURATION
default 0x81
config ADC_TI_ADC108S102_SPI_MAX_FREQ
default 0x20000000
endif
endif # ADC_TI_AC108S102
endif # ADC
if GPIO && I2C
config GPIO_PCAL9535A
def_bool y
if GPIO_PCAL9535A
config GPIO_PCAL9535A_0
def_bool y
if GPIO_PCAL9535A_0
config GPIO_PCAL9535A_0_DEV_NAME
default "EXP0"
config GPIO_PCAL9535A_0_I2C_ADDR
@ -73,8 +88,13 @@ config GPIO_PCAL9535A_0_I2C_ADDR
config GPIO_PCAL9535A_0_I2C_MASTER_DEV_NAME
default I2C_DW_0_NAME
endif # GPIO_PCAL9535A_0
config GPIO_PCAL9535A_1
def_bool y
if GPIO_PCAL9535A_1
config GPIO_PCAL9535A_1_DEV_NAME
default "EXP1"
config GPIO_PCAL9535A_1_I2C_ADDR
@ -82,21 +102,33 @@ config GPIO_PCAL9535A_1_I2C_ADDR
config GPIO_PCAL9535A_1_I2C_MASTER_DEV_NAME
default I2C_DW_0_NAME
endif # GPIO_PCAL9535A_1
config GPIO_PCAL9535A_2
def_bool y
if GPIO_PCAL9535A_2
config GPIO_PCAL9535A_2_DEV_NAME
default "EXP2"
config GPIO_PCAL9535A_2_I2C_ADDR
default 0x27
config GPIO_PCAL9535A_2_I2C_MASTER_DEV_NAME
default I2C_DW_0_NAME
endif
if PWM
endif # GPIO_PCAL9535A_2
endif # GPIO_PCAL9535A
endif # GPIO && I2C
if PWM && I2C
config PWM_PCA9685
def_bool y
if PWM_PCA9685
config PWM_PCA9685_0
def_bool y
@ -109,8 +141,9 @@ config PWM_PCA9685_0_I2C_ADDR
config PWM_PCA9685_0_I2C_MASTER_DEV_NAME
default I2C_DW_0_NAME
endif
endif
endif # PWM_PCA9685_0
endif # PWM_PCA9685
endif # PWM && I2C
# TI ADC108S102 uses SPI bus, thus

0
boards/minnowboard/Kconfig → boards/minnowboard/Kconfig.defconfig
View file

0
boards/nucleo_f103rb/Kconfig → boards/nucleo_f103rb/Kconfig.defconfig
View file

0
boards/qemu_cortex_m3/Kconfig → boards/qemu_cortex_m3/Kconfig.defconfig
View file

0
boards/qemu_x86/Kconfig → boards/qemu_x86/Kconfig.defconfig
View file

2
boards/quark_d2000_crb/Kconfig → boards/quark_d2000_crb/Kconfig.defconfig
View file

@ -5,7 +5,7 @@ if BOARD_QUARK_D2000_CRB
config BOARD
default "quark_d2000_crb"
if COUNTER
if COUNTER && AON_TIMER_QMSI
config AON_TIMER_IRQ
default 3

14
boards/quark_se_devboard/Kconfig → boards/quark_se_devboard/Kconfig.defconfig
View file

@ -19,17 +19,29 @@ config TI_CC2520_SPI_SLAVE
default 1
if SPI_DW
config SPI_DW_CS_GPIO
def_bool y
if SPI_DW_PORT_1 && SPI_DW_CS_GPIO
config SPI_DW_PORT_1_CS_GPIO_PORT
default GPIO_DW_0_NAME
config SPI_DW_PORT_1_CS_GPIO_PIN
default 11
endif # SPI_DW_PORT_1 && SPI_DW_CS_GPIO
if GPIO_DW
config TI_CC2520_GPIO_CS_NAME
default GPIO_DW_0_NAME
config TI_CC2520_GPIO_AON_NAME
default GPIO_DW_1_NAME
endif
endif # GPIO_DW
endif # SPI_DW
if SPI_QMSI
config SPI_QMSI_CS_GPIO

0
boards/quark_se_sss_devboard/Kconfig → boards/quark_se_sss_devboard/Kconfig.defconfig
View file

0
boards/stm32_mini_a15/Kconfig → boards/stm32_mini_a15/Kconfig.defconfig
View file

8
drivers/bluetooth/Kconfig
View file

@ -84,20 +84,20 @@ config BLUETOOTH_UART_ON_DEV_NAME
# Needed headroom for outgoing buffers (to controller)
config BLUETOOTH_HCI_SEND_RESERVE
int
default 0 if BLUETOOTH_H4
default 1 if BLUETOOTH_H5
# Even if no driver is selected the following default is still
# needed e.g. for unit tests.
default 0
default 0 if BLUETOOTH_H4
default 1 if BLUETOOTH_H5
# Needed headroom for incoming buffers (from controller)
config BLUETOOTH_HCI_RECV_RESERVE
int
default 0 if BLUETOOTH_H4
default 0 if BLUETOOTH_H5
# Even if no driver is selected the following default is still
# needed e.g. for unit tests.
default 0
default 0 if BLUETOOTH_H4
default 0 if BLUETOOTH_H5
endif # BLUETOOTH_STACK_HCI

2
drivers/gpio/Kconfig.dw
View file

@ -28,8 +28,8 @@ if GPIO_DW
config GPIO_DW_IO_ACCESS
prompt "I/O register access"
default y if ARC
default n
default y if ARC
depends on GPIO_DW
bool
help

2
kernel/Kconfig
View file

@ -47,8 +47,8 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config SYS_CLOCK_EXISTS
bool
# omit prompt to signify a "hidden" option
default n if (SYS_CLOCK_TICKS_PER_SEC = 0)
default y
default n if (SYS_CLOCK_TICKS_PER_SEC = 0)
help
This option specifies that the kernel lacks timer support.

2
kernel/microkernel/Kconfig
View file

@ -74,7 +74,7 @@ config NUM_TIMER_PACKETS
int
prompt "Number of timer packets" if SYS_CLOCK_EXISTS
default 0 if !SYS_CLOCK_EXISTS
default 10
default 10 if SYS_CLOCK_EXISTS
depends on MICROKERNEL
help
This option specifies the number of timer packets to create. Each

4
net/bluetooth/Kconfig
View file

@ -82,7 +82,7 @@ config BLUETOOTH_MAX_CMD_LEN
config BLUETOOTH_HCI_EVT_COUNT
int "Number of HCI event buffers"
default 8 if BLUETOOTH_CONN
default 4
default 4 if !BLUETOOTH_CONN
range 2 64
help
Number of buffers available for HCI events. This number should
@ -152,7 +152,7 @@ config BLUETOOTH_ATT_MTU
int "Attribute Protocol (ATT) channel MTU"
default 50 if BLUETOOTH_SMP # BLUETOOTH_L2CAP_IN_MTU is big enough
# for two complete ACL packets
default 23
default 23 if !BLUETOOTH_SMP
range 23 BLUETOOTH_L2CAP_IN_MTU
help
The MTU for the ATT channel. The minimum and default is 23,

4
samples/drivers/spi_test/src/spi.c
View file

@ -33,7 +33,11 @@
#include <spi.h>
#ifdef CONFIG_SPI_INTEL
#include <spi/spi_intel.h>
#if defined(CONFIG_SPI_INTEL_PORT_1)
#define SPI_DRV_NAME CONFIG_SPI_INTEL_PORT_1_DRV_NAME
#elif defined(CONFIG_SPI_INTEL_PORT_0)
#define SPI_DRV_NAME CONFIG_SPI_INTEL_PORT_0_DRV_NAME
#endif
#define SPI_SLAVE 0
#elif defined(CONFIG_SPI_DW)
#define SPI_MAX_CLK_FREQ_250KHZ 128

2
scripts/kconfig/symbol.c
View file

@ -27,7 +27,7 @@ struct utsname {
* return P_DEFAULT that are parsed later in Kconfig
* files.
*/
#define PREFER_LATER_DEFAULTS 0
#define PREFER_LATER_DEFAULTS 1
struct symbol symbol_yes = {
.name = "y",