From 8ec1e0cdaf296c0ab0306ecee9b61eaafe0bef99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Ku=C5=BAnia?= Date: Fri, 26 Apr 2024 12:43:14 +0200 Subject: [PATCH] drivers: spi_dw: add HSSI register layout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Synopsys Designware SPI peripheral exists in two versions with slightly different register layouts. Added a Kconfig option that makes the driver compatible with the HSSI register layout. Signed-off-by: Rafał Kuźnia --- drivers/spi/Kconfig.dw | 6 ++++++ drivers/spi/spi_dw.h | 15 +++++++++++---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/spi/Kconfig.dw b/drivers/spi/Kconfig.dw index 3ebdd54ee9..ed45361d8e 100644 --- a/drivers/spi/Kconfig.dw +++ b/drivers/spi/Kconfig.dw @@ -20,4 +20,10 @@ config SPI_DW_ACCESS_WORD_ONLY DesignWare SPI only allows word access, byte access will raise exception. +config SPI_DW_HSSI + bool "Designware SPI HSSI variant" + help + Use register layout compatible with the SPI DW HSSI variant of the + peripheral. + endif # SPI_DW diff --git a/drivers/spi/spi_dw.h b/drivers/spi/spi_dw.h index d6383bc4ed..6c073b4747 100644 --- a/drivers/spi/spi_dw.h +++ b/drivers/spi/spi_dw.h @@ -179,19 +179,26 @@ static int reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off) /* Common registers settings, bits etc... */ /* CTRLR0 settings */ +#if !IS_ENABLED(CONFIG_SPI_DW_HSSI) #define DW_SPI_CTRLR0_SCPH_BIT (6) #define DW_SPI_CTRLR0_SCPOL_BIT (7) +#define DW_SPI_CTRLR0_TMOD_SHIFT (8) +#define DW_SPI_CTRLR0_SLV_OE_BIT (10) #define DW_SPI_CTRLR0_SRL_BIT (11) +#else +/* The register layout is different in the HSSI variant */ +#define DW_SPI_CTRLR0_SCPH_BIT (8) +#define DW_SPI_CTRLR0_SCPOL_BIT (9) +#define DW_SPI_CTRLR0_TMOD_SHIFT (10) +#define DW_SPI_CTRLR0_SLV_OE_BIT (12) +#define DW_SPI_CTRLR0_SRL_BIT (13) +#endif #define DW_SPI_CTRLR0_SCPH BIT(DW_SPI_CTRLR0_SCPH_BIT) #define DW_SPI_CTRLR0_SCPOL BIT(DW_SPI_CTRLR0_SCPOL_BIT) #define DW_SPI_CTRLR0_SRL BIT(DW_SPI_CTRLR0_SRL_BIT) - -#define DW_SPI_CTRLR0_SLV_OE_BIT (10) #define DW_SPI_CTRLR0_SLV_OE BIT(DW_SPI_CTRLR0_SLV_OE_BIT) -#define DW_SPI_CTRLR0_TMOD_SHIFT (8) - #define DW_SPI_CTRLR0_TMOD_TX_RX (0) #define DW_SPI_CTRLR0_TMOD_TX (1 << DW_SPI_CTRLR0_TMOD_SHIFT) #define DW_SPI_CTRLR0_TMOD_RX (2 << DW_SPI_CTRLR0_TMOD_SHIFT)