boards: arm64: provide support for ROC-RK3568-PC

This is support for AArch64 development board.
The board uses 4-core Cortex-A55, which are based on
the ARMv8.2 architecture.
In addition,we support smp support and
it can use 4-cores to run basic samples.

Signed-off-by: Charlie Xiong <1981639884@qq.com>

boards/arm64/roc_rk3568_pc/CMakeLists.txt

@@ -0,0 +1 @@
+# SPDX-License-Identifier: Apache-2.0

boards/arm64/roc_rk3568_pc/Kconfig.board

@@ -0,0 +1,8 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ROC_RK3568_PC
+	bool "Rockchip ROC-RK3568-PC"
+	depends on SOC_SERIES_RK3568
+	select ARM64

boards/arm64/roc_rk3568_pc/Kconfig.defconfig

@@ -0,0 +1,10 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_ROC_RK3568_PC
+
+config BOARD
+	default "roc_rk3568_pc"
+
+endif # BOARD_ROC_RK3568_PC

boards/arm64/roc_rk3568_pc/board.cmake

@@ -0,0 +1 @@
+# SPDX-License-Identifier: Apache-2.0

boards/arm64/roc_rk3568_pc/doc/index.rst

@@ -0,0 +1,142 @@
+.. _roc_rk3568_pc:
+
+Firefly ROC-RK3568-PC (Quad-core Cortex-A55)
+############################################
+
+Overview
+********
+
+The ROC-RK3568-PC is a Quad-Core 64-Bit Mini Computer, which supports 4G large RAM. M.2
+and SATA3.0 interfaces enables expansion with large hard drives.
+Providing dual Gigabit Ethernet ports, it supports WiFi 6 wireless transmission.
+Control Port can be connected with RS485/RS232 devices.
+
+RK3568 quad-core 64-bit Cortex-A55 processor, with brand new ARM v8.2-A architecture,
+has frequency up to 2.0GHz. Zephyr OS is ported to run on it.
+
+
+- Board features:
+
+  - RAM: 4GB LPDDR4
+  - Storage:
+
+    - 32GB eMMC
+    - M.2 PCIe 3.0 x 1 (Expand with 2242 / 2280 NVMe SSD)
+    - TF-Card Slot
+  - Wireless:
+
+    - Supports WiFi 6 (802.11 AX)
+    - Supports BT5.0
+  - USB:
+
+    - One USB 3.0
+    - Two USB 2.0
+    - One Type-C
+  - Ethernet
+  - M.2 PCIe3.0 (Expand with NVMe SSD)
+  - LEDs:
+
+    - 1x Power status LED
+  - Debug
+
+    - UART debug ports for board
+
+
+Supported Features
+==================
+
+The Zephyr roc_rk3568_pc board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| GIC-v3    | on-chip    | interrupt controller                |
++-----------+------------+-------------------------------------+
+| ARM TIMER | on-chip    | system clock                        |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port                         |
++-----------+------------+-------------------------------------+
+
+Devices
+========
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 24 MHz.
+Cortex-A55 Core runs up to 2.0 GHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+CPU's UART2.
+
+Programming and Debugging
+*************************
+
+Use U-Boot to load the zephyr.bin to the memory and kick it:
+
+.. code-block:: console
+
+    tftp 0x40000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x40000000
+
+Use this configuration to run basic Zephyr applications and kernel tests,
+for example, with the :zephyr:code-sample:`synchronization` sample:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: roc_rk3568_pc
+   :goals: run
+
+This will build an image with the synchronization sample app, boot it and
+display the following ram console output:
+
+.. code-block:: console
+
+    ***  Booting Zephyr OS build bc695c6df5eb  ***
+    thread_a: Hello World from cpu 0 on roc_rk3568_pc!
+    thread_b: Hello World from cpu 0 on roc_rk3568_pc!
+    thread_a: Hello World from cpu 0 on roc_rk3568_pc!
+    thread_b: Hello World from cpu 0 on roc_rk3568_pc!
+
+
+roc_rk3568_pc_smp support, use this configuration to run Zephyr smp applications and subsys tests,
+for example, with the :zephyr:code-sample:`synchronization` sample:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: roc_rk3568_pc_smp
+   :goals: run
+
+This will build an image with the shell_module sample app, boot it and
+display the following ram console output:
+
+.. code-block:: console
+
+    ***  Booting Zephyr OS build bc695c6df5eb  ***
+    I/TC: Secondary CPU 1 initializing
+    I/TC: Secondary CPU 1 switching to normal world boot
+    I/TC: Secondary CPU 2 initializing
+    I/TC: Secondary CPU 2 switching to normal world boot
+    I/TC: Secondary CPU 3 initializing
+    I/TC: Secondary CPU 3 switching to normal world boot
+    Secondary CPU core 1 (MPID:0x100) is up
+    Secondary CPU core 2 (MPID:0x200) is up
+    Secondary CPU core 3 (MPID:0x300) is up
+
+    thread_a: Hello World from cpu 0 on roc_rk3568_pc!
+    thread_b: Hello World from cpu 1 on roc_rk3568_pc!
+    thread_a: Hello World from cpu 0 on roc_rk3568_pc!
+    thread_b: Hello World from cpu 1 on roc_rk3568_pc!
+
+References
+==========
+
+More information can refer to Firefly official website:
+`Firefly website`_.
+
+.. _Firefly website:
+   https://en.t-firefly.com/product/industry/rocrk3568pc.html?theme=pc

boards/arm64/roc_rk3568_pc/roc_rk3568_pc.dts

@@ -0,0 +1,33 @@
+/*
+ * Copyright 2022 HNU-ESNL
+ * Copyright 2022 openEuler SIG-Zephyr
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm64/rockchip/rk3568.dtsi>
+#include <common/mem.h>
+
+/ {
+	model = "Firefly ROC-RK3568-PC";
+	compatible = "rockchip,rk3568";
+
+	chosen {
+		zephyr,console = &uart2;
+		zephyr,shell-uart = &uart2;
+		zephyr,sram = &sram0;
+	};
+
+	sram0: memory@40000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x40000000 DT_SIZE_M(1)>;
+	};
+
+};
+
+&uart2 {
+	status = "okay";
+	current-speed = <1500000>;
+};

boards/arm64/roc_rk3568_pc/roc_rk3568_pc.yaml

@@ -0,0 +1,13 @@
+identifier: roc_rk3568_pc
+name: Rockchip ROC RK3568 PC
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 1024
+testing:
+  default: true
+  ignore_tags:
+    - net
+    - bluetooth

boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig

@@ -0,0 +1,26 @@
+# Copyright 2021 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_SOC_SERIES_RK3568=y
+CONFIG_SOC_RK3568=y
+CONFIG_BOARD_ROC_RK3568_PC=y
+CONFIG_ARM_ARCH_TIMER=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# ARMv8 NS world with cache management
+CONFIG_ARMV8_A_NS=y
+CONFIG_CACHE_MANAGEMENT=y
+
+# Clock support
+CONFIG_CLOCK_CONTROL=y
+CONFIG_TICKLESS_KERNEL=y

boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.dts

@@ -0,0 +1,8 @@
+/*
+ * Copyright 2022 HNU-ESNL
+ * Copyright 2022 openEuler SIG-Zephyr
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "roc_rk3568_pc.dts"

boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.yaml

@@ -0,0 +1,15 @@
+identifier: roc_rk3568_pc_smp
+name: Rockchip ROC RK3568 PC SMP
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 1024
+supported:
+  - smp
+testing:
+  default: true
+  ignore_tags:
+    - net
+    - bluetooth

boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp_defconfig

@@ -0,0 +1,36 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_SOC_SERIES_RK3568=y
+CONFIG_SOC_RK3568=y
+CONFIG_BOARD_ROC_RK3568_PC=y
+CONFIG_ARM_ARCH_TIMER=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# SMP support
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=4
+CONFIG_MAX_THREAD_BYTES=4
+
+# ARMv8 NS world with cache management
+CONFIG_ARMV8_A_NS=y
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_DCACHE=y
+
+# PSCI support
+CONFIG_PM_CPU_OPS=y
+CONFIG_PM_CPU_OPS_PSCI=y
+
+# Clock support
+CONFIG_CLOCK_CONTROL=y
+CONFIG_TICKLESS_KERNEL=y

dts/arm64/rockchip/rk3568.dtsi

@@ -0,0 +1,89 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 HNU-ESNL
+ * Copyright 2022 openEuler SIG-Zephyr
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm64/armv8-a.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	compatible = "rockchip,rk3568";
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x000>;
+		};
+
+		cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x100>;
+		};
+
+		cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x200>;
+
+		};
+
+		cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x300>;
+		};
+	};
+
+	gic: interrupt-controller@fd400000 {
+		#address-cells = <1>;
+		compatible = "arm,gic-v3","arm,gic";
+		#interrupt-cells = <4>;
+		interrupt-controller;
+
+		reg = <0xfd400000 0x10000>, /* GICD */
+		      <0xfd460000 0xc0000>; /* GICR */
+		status = "okay";
+	};
+
+	psci {
+		compatible = "arm,psci-0.2", "arm,psci";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	uart2: serial@fe660000 {
+		compatible = "rockchip,rk3568-uart", "ns16550";
+		reg = <0xfe660000 0x10000>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+		clock-frequency = <12000000>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+};

soc/arm64/rockchip/Kconfig

@@ -17,5 +17,6 @@ source "soc/arm64/rockchip/*/Kconfig.soc"
 
 config SOC_PART_NUMBER
 	default "RK3399" if SOC_SERIES_RK3399
+	default "RK3568" if SOC_SERIES_RK3568
 
 endif # SOC_FAMILY_ROCKCHIP

soc/arm64/rockchip/rk3568/CMakeLists.txt

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)

soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568

@@ -0,0 +1,24 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_RK3568
+
+config SOC
+	default "rk3568"
+
+config FLASH_SIZE
+	default 0
+
+config FLASH_BASE_ADDRESS
+	default 0
+
+config NUM_IRQS
+	int
+	default 240
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 24000000
+
+endif

soc/arm64/rockchip/rk3568/Kconfig.defconfig.series

@@ -0,0 +1,12 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RK3568
+
+config SOC_SERIES
+	default "rk3568"
+
+source "soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568"
+
+endif # SOC_SERIES_RK3568

soc/arm64/rockchip/rk3568/Kconfig.series

@@ -0,0 +1,10 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyrs
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RK3568
+	bool "Rockchip RK3568 Series"
+	select ARM64
+	select SOC_FAMILY_ROCKCHIP
+	help
+	  Enable support for RK3568 Series.

soc/arm64/rockchip/rk3568/Kconfig.soc

@@ -0,0 +1,16 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+prompt "Rockchip RK3568 SoC"
+depends on SOC_SERIES_RK3568
+
+config SOC_RK3568
+	bool "Rockchip rk3568"
+	select ARM64
+	select CPU_CORTEX_A55
+	select ARM_ARCH_TIMER
+	select GIC_V3
+
+endchoice

soc/arm64/rockchip/rk3568/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm64/scripts/linker.ld>

soc/arm64/rockchip/rk3568/mmu_regions.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 HNU-ESNL
+ * Copyright 2022 openEuler SIG-Zephyr
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/arch/arm64/arm_mmu.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_NS),
+
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_NS),
+
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};