drivers: display: add driver for ST7796s display
Add driver for ST7796s display. This is a MIPI DBI display controller, with a frame memory of 320x480x18 pixels. Support for 4 wire SPI mode is implemented using the MIPI DBI API. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse
Carles Cufí
parent
58e78c4af7
commit
8ffd1e2f53
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@ -19,6 +19,7 @@ zephyr_library_sources_ifdef(CONFIG_SSD1306 ssd1306.c)
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zephyr_library_sources_ifdef(CONFIG_SSD16XX ssd16xx.c)
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zephyr_library_sources_ifdef(CONFIG_SSD16XX ssd16xx.c)
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zephyr_library_sources_ifdef(CONFIG_ST7789V display_st7789v.c)
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zephyr_library_sources_ifdef(CONFIG_ST7789V display_st7789v.c)
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zephyr_library_sources_ifdef(CONFIG_ST7735R display_st7735r.c)
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zephyr_library_sources_ifdef(CONFIG_ST7735R display_st7735r.c)
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zephyr_library_sources_ifdef(CONFIG_ST7796S display_st7796s.c)
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zephyr_library_sources_ifdef(CONFIG_STM32_LTDC display_stm32_ltdc.c)
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zephyr_library_sources_ifdef(CONFIG_STM32_LTDC display_stm32_ltdc.c)
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zephyr_library_sources_ifdef(CONFIG_RM68200 display_rm68200.c)
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zephyr_library_sources_ifdef(CONFIG_RM68200 display_rm68200.c)
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zephyr_library_sources_ifdef(CONFIG_RM67162 display_rm67162.c)
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zephyr_library_sources_ifdef(CONFIG_RM67162 display_rm67162.c)
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@ -29,6 +29,7 @@ source "drivers/display/Kconfig.ssd1306"
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source "drivers/display/Kconfig.ssd16xx"
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source "drivers/display/Kconfig.ssd16xx"
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source "drivers/display/Kconfig.st7735r"
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source "drivers/display/Kconfig.st7735r"
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source "drivers/display/Kconfig.st7789v"
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source "drivers/display/Kconfig.st7789v"
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source "drivers/display/Kconfig.st7796s"
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source "drivers/display/Kconfig.stm32_ltdc"
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source "drivers/display/Kconfig.stm32_ltdc"
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source "drivers/display/Kconfig.uc81xx"
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source "drivers/display/Kconfig.uc81xx"
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source "drivers/display/Kconfig.dummy"
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source "drivers/display/Kconfig.dummy"
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10
drivers/display/Kconfig.st7796s
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10
drivers/display/Kconfig.st7796s
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@ -0,0 +1,10 @@
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# Copyright 2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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config ST7796S
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bool "ST7796S display driver"
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default y
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depends on DT_HAS_SITRONIX_ST7796S_ENABLED
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select MIPI_DBI
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help
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Enable driver for ST7796S display driver.
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354
drivers/display/display_st7796s.c
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354
drivers/display/display_st7796s.c
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@ -0,0 +1,354 @@
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/*
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* Copyright 2023, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sitronix_st7796s
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#include <zephyr/device.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/display.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/drivers/mipi_dbi.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(display_st7796s, CONFIG_DISPLAY_LOG_LEVEL);
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#include "display_st7796s.h"
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/* Magic numbers used to lock/unlock command settings */
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#define ST7796S_UNLOCK_1 0xC3
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#define ST7796S_UNLOCK_2 0x96
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#define ST7796S_LOCK_1 0x3C
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#define ST7796S_LOCK_2 0x69
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#define ST7796S_PIXEL_SIZE 2 /* Only 16 bit color mode supported with this driver */
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struct st7796s_config {
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const struct device *mipi_dbi;
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const struct mipi_dbi_config dbi_config;
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const struct gpio_dt_spec cmd_data_gpio;
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const struct gpio_dt_spec reset_gpio;
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uint16_t width;
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uint16_t height;
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bool inverted; /* Display color inversion */
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/* Display configuration parameters */
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uint8_t dic; /* Display inversion control */
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uint8_t frmctl1[2]; /* Frame rate control, normal mode */
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uint8_t frmctl2[2]; /* Frame rate control, idle mode */
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uint8_t frmctl3[2]; /* Frame rate control, partial mode */
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uint8_t bpc[4]; /* Blanking porch control */
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uint8_t dfc[4]; /* Display function control */
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uint8_t pwr1[2]; /* Power control 1 */
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uint8_t pwr2; /* Power control 2 */
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uint8_t pwr3; /* Power control 3 */
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uint8_t vcmpctl; /* VCOM control */
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uint8_t doca[8]; /* Display output ctrl */
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uint8_t pgc[14]; /* Positive gamma control */
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uint8_t ngc[14]; /* Negative gamma control */
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uint8_t madctl; /* Memory data access control */
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};
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static int st7796s_send_cmd(const struct device *dev,
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uint8_t cmd, const uint8_t *data, size_t len)
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{
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const struct st7796s_config *config = dev->config;
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return mipi_dbi_command_write(config->mipi_dbi, &config->dbi_config,
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cmd, data, len);
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}
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static int st7796s_set_cursor(const struct device *dev,
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const uint16_t x, const uint16_t y,
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const uint16_t width, const uint16_t height)
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{
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uint16_t addr_data[2];
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int ret;
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/* Column address */
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addr_data[0] = sys_cpu_to_be16(x);
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addr_data[1] = sys_cpu_to_be16(x + width - 1);
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ret = st7796s_send_cmd(dev, ST7796S_CMD_CASET,
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(uint8_t *)addr_data, sizeof(addr_data));
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if (ret < 0) {
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return ret;
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}
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/* Row address */
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addr_data[0] = sys_cpu_to_be16(y);
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addr_data[1] = sys_cpu_to_be16(y + height - 1);
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ret = st7796s_send_cmd(dev, ST7796S_CMD_RASET,
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(uint8_t *)addr_data, sizeof(addr_data));
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return ret;
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}
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static int st7796s_blanking_on(const struct device *dev)
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{
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return st7796s_send_cmd(dev, ST7796S_CMD_DISPOFF, NULL, 0);
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}
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static int st7796s_blanking_off(const struct device *dev)
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{
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return st7796s_send_cmd(dev, ST7796S_CMD_DISPON, NULL, 0);
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}
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static int st7796s_write(const struct device *dev,
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const uint16_t x,
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const uint16_t y,
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const struct display_buffer_descriptor *desc,
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const void *buf)
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{
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const struct st7796s_config *config = dev->config;
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int ret;
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struct display_buffer_descriptor mipi_desc;
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enum display_pixel_format pixfmt;
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ret = st7796s_set_cursor(dev, x, y, desc->width, desc->height);
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if (ret < 0) {
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return ret;
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}
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mipi_desc.buf_size = desc->width * desc->height * ST7796S_PIXEL_SIZE;
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ret = mipi_dbi_command_write(config->mipi_dbi,
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&config->dbi_config, ST7796S_CMD_RAMWR,
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NULL, 0);
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if (ret < 0) {
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return ret;
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}
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if (config->madctl & ST7796S_MADCTL_BGR) {
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/* Zephyr treats RGB565 as BGR565 */
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pixfmt = PIXEL_FORMAT_RGB_565;
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} else {
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pixfmt = PIXEL_FORMAT_BGR_565;
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}
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return mipi_dbi_write_display(config->mipi_dbi,
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&config->dbi_config, buf,
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&mipi_desc, pixfmt);
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}
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static void st7796s_get_capabilities(const struct device *dev,
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struct display_capabilities *capabilities)
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{
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const struct st7796s_config *config = dev->config;
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memset(capabilities, 0, sizeof(struct display_capabilities));
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if (config->madctl & ST7796S_MADCTL_BGR) {
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/* Zephyr treats RGB565 as BGR565 */
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capabilities->current_pixel_format = PIXEL_FORMAT_RGB_565;
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} else {
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capabilities->current_pixel_format = PIXEL_FORMAT_BGR_565;
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}
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capabilities->x_resolution = config->width;
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capabilities->y_resolution = config->height;
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capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
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}
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static int st7796s_lcd_config(const struct device *dev)
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{
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const struct st7796s_config *config = dev->config;
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int ret;
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uint8_t param;
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/* Unlock display configuration */
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param = ST7796S_UNLOCK_1;
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ret = st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param));
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if (ret < 0) {
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return ret;
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}
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param = ST7796S_UNLOCK_2;
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ret = st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_DIC, &config->dic, sizeof(config->dic));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_FRMCTR1, config->frmctl1,
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sizeof(config->frmctl1));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_FRMCTR2, config->frmctl2,
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sizeof(config->frmctl2));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_FRMCTR3, config->frmctl3,
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sizeof(config->frmctl3));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_BPC, config->bpc, sizeof(config->bpc));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_DFC, config->dfc, sizeof(config->dfc));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_PWR1, config->pwr1, sizeof(config->pwr1));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_PWR2, &config->pwr2, sizeof(config->pwr2));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_PWR3, &config->pwr3, sizeof(config->pwr3));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_VCMPCTL, &config->vcmpctl,
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sizeof(config->vcmpctl));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_DOCA, config->doca,
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sizeof(config->doca));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_PGC, config->pgc, sizeof(config->pgc));
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if (ret < 0) {
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return ret;
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}
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ret = st7796s_send_cmd(dev, ST7796S_CMD_NGC, config->ngc, sizeof(config->ngc));
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if (ret < 0) {
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return ret;
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}
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/* Lock display configuration */
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param = ST7796S_LOCK_1;
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ret = st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param));
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if (ret < 0) {
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return ret;
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}
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param = ST7796S_LOCK_2;
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return st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param));
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}
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static int st7796s_init(const struct device *dev)
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{
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const struct st7796s_config *config = dev->config;
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int ret;
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uint8_t param;
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/* Since VDDI comes up before reset pin is low, we must reset display
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* state. Pulse for 100 MS, per datasheet
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*/
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ret = mipi_dbi_reset(config->mipi_dbi, 100);
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if (ret < 0) {
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return ret;
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}
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/* Delay an additional 100ms after reset */
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k_msleep(100);
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/* Configure controller parameters */
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ret = st7796s_lcd_config(dev);
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if (ret < 0) {
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LOG_ERR("Could not set LCD configuration (%d)", ret);
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return ret;
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}
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if (config->inverted) {
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ret = st7796s_send_cmd(dev, ST7796S_CMD_INVON, NULL, 0);
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} else {
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ret = st7796s_send_cmd(dev, ST7796S_CMD_INVOFF, NULL, 0);
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}
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if (ret < 0) {
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return ret;
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}
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param = ST7796S_CONTROL_16BIT;
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ret = st7796s_send_cmd(dev, ST7796S_CMD_COLMOD, ¶m, sizeof(param));
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if (ret < 0) {
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return ret;
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}
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param = config->madctl;
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ret = st7796s_send_cmd(dev, ST7796S_CMD_MADCTL, ¶m, sizeof(param));
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if (ret < 0) {
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return ret;
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}
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/* Exit sleep */
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st7796s_send_cmd(dev, ST7796S_CMD_SLPOUT, NULL, 0);
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/* Delay 5ms after sleep out command, per datasheet */
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k_msleep(5);
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/* Turn on display */
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st7796s_send_cmd(dev, ST7796S_CMD_DISPON, NULL, 0);
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return 0;
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}
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static const struct display_driver_api st7796s_api = {
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.blanking_on = st7796s_blanking_on,
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.blanking_off = st7796s_blanking_off,
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.write = st7796s_write,
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.get_capabilities = st7796s_get_capabilities,
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};
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#define ST7796S_INIT(n) \
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||||||
|
static const struct st7796s_config st7796s_config_##n = { \
|
||||||
|
.mipi_dbi = DEVICE_DT_GET(DT_INST_PARENT(n)), \
|
||||||
|
.dbi_config = { \
|
||||||
|
.config = MIPI_DBI_SPI_CONFIG_DT( \
|
||||||
|
DT_DRV_INST(n), \
|
||||||
|
SPI_OP_MODE_MASTER | \
|
||||||
|
SPI_WORD_SET(8), \
|
||||||
|
0), \
|
||||||
|
.mode = MIPI_DBI_MODE_SPI_4WIRE, \
|
||||||
|
}, \
|
||||||
|
.width = DT_INST_PROP(n, width), \
|
||||||
|
.height = DT_INST_PROP(n, height), \
|
||||||
|
.inverted = DT_INST_PROP(n, color_invert), \
|
||||||
|
.dic = DT_INST_ENUM_IDX(n, invert_mode), \
|
||||||
|
.frmctl1 = DT_INST_PROP(n, frmctl1), \
|
||||||
|
.frmctl2 = DT_INST_PROP(n, frmctl2), \
|
||||||
|
.frmctl3 = DT_INST_PROP(n, frmctl3), \
|
||||||
|
.bpc = DT_INST_PROP(n, bpc), \
|
||||||
|
.dfc = DT_INST_PROP(n, dfc), \
|
||||||
|
.pwr1 = DT_INST_PROP(n, pwr1), \
|
||||||
|
.pwr2 = DT_INST_PROP(n, pwr2), \
|
||||||
|
.pwr3 = DT_INST_PROP(n, pwr3), \
|
||||||
|
.vcmpctl = DT_INST_PROP(n, vcmpctl), \
|
||||||
|
.doca = DT_INST_PROP(n, doca), \
|
||||||
|
.pgc = DT_INST_PROP(n, pgc), \
|
||||||
|
.ngc = DT_INST_PROP(n, ngc), \
|
||||||
|
.madctl = DT_INST_PROP(n, madctl), \
|
||||||
|
}; \
|
||||||
|
\
|
||||||
|
DEVICE_DT_INST_DEFINE(n, st7796s_init, \
|
||||||
|
NULL, \
|
||||||
|
NULL, \
|
||||||
|
&st7796s_config_##n, \
|
||||||
|
POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, \
|
||||||
|
&st7796s_api);
|
||||||
|
|
||||||
|
DT_INST_FOREACH_STATUS_OKAY(ST7796S_INIT)
|
||||||
40
drivers/display/display_st7796s.h
Normal file
40
drivers/display/display_st7796s.h
Normal file
|
|
@ -0,0 +1,40 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2023, NXP
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _ZEPHYR_DRIVERS_DISPLAY_ST7796S_H_
|
||||||
|
#define _ZEPHYR_DRIVERS_DISPLAY_ST7796S_H_
|
||||||
|
|
||||||
|
#define ST7796S_CMD_SLPIN 0x10 /* Sleep in */
|
||||||
|
#define ST7796S_CMD_SLPOUT 0x11 /* Sleep out */
|
||||||
|
#define ST7796S_CMD_INVOFF 0x20 /* Display inversion off */
|
||||||
|
#define ST7796S_CMD_INVON 0x21 /* Display inversion on */
|
||||||
|
#define ST7796S_CMD_CASET 0x2A /* Column address set */
|
||||||
|
#define ST7796S_CMD_RASET 0x2B /* Row address set */
|
||||||
|
#define ST7796S_CMD_RAMWR 0x2C /* Memory write */
|
||||||
|
#define ST7796S_CMD_DISPOFF 0x28 /* Display off */
|
||||||
|
#define ST7796S_CMD_DISPON 0x29 /* Display on */
|
||||||
|
#define ST7796S_CMD_MADCTL 0x36 /* Memory data access control */
|
||||||
|
#define ST7796S_CMD_COLMOD 0x3A /* Interface pixel format */
|
||||||
|
#define ST7796S_CMD_FRMCTR1 0xB1 /* Frame rate control 1 (normal mode) */
|
||||||
|
#define ST7796S_CMD_FRMCTR2 0xB2 /* Frame rate control 2 (idle mode) */
|
||||||
|
#define ST7796S_CMD_FRMCTR3 0xB3 /* Frame rate control 3 (partial mode) */
|
||||||
|
#define ST7796S_CMD_DIC 0xB4 /* Display inversion control */
|
||||||
|
#define ST7796S_CMD_BPC 0xB5 /* Blanking porch control */
|
||||||
|
#define ST7796S_CMD_DFC 0xB6 /* Display function control */
|
||||||
|
#define ST7796S_CMD_PWR1 0xC0 /* Power control 1 */
|
||||||
|
#define ST7796S_CMD_PWR2 0xC1 /* Power control 1 */
|
||||||
|
#define ST7796S_CMD_PWR3 0xC2 /* Power control 1 */
|
||||||
|
#define ST7796S_CMD_VCMPCTL 0xC5 /* VCOM control */
|
||||||
|
#define ST7796S_CMD_PGC 0xE0 /* Positive gamma control */
|
||||||
|
#define ST7796S_CMD_NGC 0xE1 /* Negative gamma control */
|
||||||
|
#define ST7796S_CMD_DOCA 0xE8 /* Display output control adjust */
|
||||||
|
#define ST7796S_CMD_CSCON 0xF0 /* Command set control */
|
||||||
|
|
||||||
|
#define ST7796S_CONTROL_16BIT 0x5 /* Sets control interface to 16 bit mode */
|
||||||
|
#define ST7796S_MADCTL_BGR BIT(3) /* Sets BGR color mode */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* _ZEPHYR_DRIVERS_DISPLAY_ST7796S_H_ */
|
||||||
Loading…
Reference in a new issue