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spi: add SPI driver for STM32 family

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Add a SPI master and slave driver for the L4, F4 and F3 STM32
SoCs families.

Change-Id: I1faf5c97f992c91eba852fd126e7d3b83158993d
Origin: Original
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Tested-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Neil Armstrong 2016-09-16 15:24:19 +02:00 committed by Anas Nashif
parent a3a57b4db1
commit 9033fb2f01
5 changed files with 544 additions and 0 deletions
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34
drivers/spi/Kconfig
View file

@ -50,6 +50,22 @@ config SPI_INTEL
was formerly found on XScale chips. It can be found nowadays
on CEXXXX Intel media controller and Quark CPU (2 of them).
config SPI_STM32
bool
prompt "STM32 MCU SPI controller driver"
depends on SPI && SOC_FAMILY_STM32
depends on SOC_SERIES_STM32L4X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F3X
default n
help
Enable SPI support on the STM32 family of processors.
config SPI_STM32_INTERRUPT
bool
prompt "STM32 MCU SPI Interrupt Support"
depends on SPI_STM32
default n
help
Enable Interrupt support for the SPI Driver of STM32 family.
if SPI
config SPI_INIT_PRIORITY
@ -195,6 +211,24 @@ config SPI_2_CS_GPIO_PIN
depends on SPI_2 && SPI_CS_GPIO
default 0
config SPI_3
bool
prompt "SPI port 3"
default n
help
Enable SPI controller port 3.
config SPI_3_NAME
string
prompt "SPI port 3 device name"
depends on SPI_3
default "SPI_3"
config SPI_3_IRQ_PRI
int
prompt "Port 3 interrupt priority"
depends on SPI_3
config SPI_SS_INIT_PRIORITY
int "Init priority"
depends on SPI_QMSI_SS

1
drivers/spi/Makefile
View file

@ -9,3 +9,4 @@ obj-$(CONFIG_SPIM_NRF52) += spim_nrf52.o
obj-$(CONFIG_SPIS_NRF5) += spis_nrf5.o
obj-$(CONFIG_SPI_QMSI) += spi_qmsi.o
obj-$(CONFIG_SPI_QMSI_SS) += spi_qmsi_ss.o
obj-$(CONFIG_SPI_STM32) += spi_ll_stm32.o

471
drivers/spi/spi_ll_stm32.c Normal file
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@ -0,0 +1,471 @@
/*
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#define SYS_LOG_LEVEL CONFIG_SYS_LOG_SPI_LEVEL
#include <logging/sys_log.h>
#include <misc/util.h>
#include <kernel.h>
#include <board.h>
#include <errno.h>
#include <spi.h>
#include <clock_control/stm32_clock_control.h>
#include <clock_control.h>
#include <drivers/spi/spi_ll_stm32.h>
#include <spi_ll_stm32.h>
#define CONFIG_CFG(cfg) \
((const struct spi_stm32_config * const)(cfg)->dev->config->config_info)
#define CONFIG_DATA(cfg) \
((struct spi_stm32_data * const)(cfg)->dev->driver_data)
#ifdef CONFIG_SPI_STM32_INTERRUPT
static void spi_stm32_transmit(SPI_TypeDef *spi, struct spi_stm32_data *data);
static void spi_stm32_receive(SPI_TypeDef *spi, struct spi_stm32_data *data);
static void spi_stm32_isr(void *arg)
{
struct device * const dev = (struct device *) arg;
const struct spi_stm32_config *cfg = dev->config->config_info;
struct spi_stm32_data *data = dev->driver_data;
SPI_TypeDef *spi = cfg->spi;
if (LL_SPI_IsActiveFlag_TXE(spi) &&
(spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx))) {
spi_stm32_transmit(spi, data);
}
if (LL_SPI_IsActiveFlag_RXNE(spi)) {
if (spi_context_rx_on(&data->ctx)) {
spi_stm32_receive(spi, data);
} else {
LL_SPI_DisableIT_RXNE(spi);
}
}
if (!spi_context_tx_on(&data->ctx) &&
!spi_context_rx_on(&data->ctx)) {
LL_SPI_DisableIT_TXE(spi);
LL_SPI_DisableIT_RXNE(spi);
spi_context_cs_control(&data->ctx, false);
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F3X)
/* Flush RX buffer */
while (LL_SPI_IsActiveFlag_RXNE(spi)) {
(void) LL_SPI_ReceiveData8(spi);
}
#endif
if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
while (LL_SPI_IsActiveFlag_BSY(spi)) {
/* NOP */
}
LL_SPI_Disable(spi);
}
spi_context_complete(&data->ctx, 0);
}
}
#endif
static int spi_stm32_configure(struct spi_config *config)
{
const struct spi_stm32_config *cfg = CONFIG_CFG(config);
struct spi_stm32_data *data = CONFIG_DATA(config);
const u32_t scaler[] = {
LL_SPI_BAUDRATEPRESCALER_DIV2,
LL_SPI_BAUDRATEPRESCALER_DIV4,
LL_SPI_BAUDRATEPRESCALER_DIV8,
LL_SPI_BAUDRATEPRESCALER_DIV16,
LL_SPI_BAUDRATEPRESCALER_DIV32,
LL_SPI_BAUDRATEPRESCALER_DIV64,
LL_SPI_BAUDRATEPRESCALER_DIV128,
LL_SPI_BAUDRATEPRESCALER_DIV256
};
SPI_TypeDef *spi = cfg->spi;
u32_t clock;
int br;
if (spi_context_configured(&data->ctx, config)) {
/* Nothing to do */
return 0;
}
if (SPI_WORD_SIZE_GET(config->operation) != 8) {
return -ENOTSUP;
}
clock_control_get_rate(device_get_binding(STM32_CLOCK_CONTROL_NAME),
(clock_control_subsys_t) &cfg->pclken, &clock);
for (br = 1 ; br <= ARRAY_SIZE(scaler) ; ++br) {
u32_t clk = clock >> br;
if (clk < config->frequency) {
break;
}
}
if (br > ARRAY_SIZE(scaler)) {
SYS_LOG_ERR("Unsupported frequency %uHz, max %uHz, min %uHz",
config->frequency,
clock >> 1,
clock >> ARRAY_SIZE(scaler));
return -EINVAL;
}
LL_SPI_Disable(spi);
LL_SPI_SetBaudRatePrescaler(spi, scaler[br - 1]);
if (SPI_MODE_GET(config->operation) == SPI_MODE_CPOL) {
LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_HIGH);
} else {
LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_LOW);
}
if (SPI_MODE_GET(config->operation) == SPI_MODE_CPHA) {
LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_2EDGE);
} else {
LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_1EDGE);
}
LL_SPI_SetTransferDirection(spi, LL_SPI_FULL_DUPLEX);
if (config->operation & SPI_TRANSFER_LSB) {
LL_SPI_SetTransferBitOrder(spi, LL_SPI_LSB_FIRST);
} else {
LL_SPI_SetTransferBitOrder(spi, LL_SPI_MSB_FIRST);
}
LL_SPI_DisableCRC(spi);
if (config->operation & SPI_OP_MODE_SLAVE) {
LL_SPI_SetMode(spi, LL_SPI_MODE_SLAVE);
} else {
LL_SPI_SetMode(spi, LL_SPI_MODE_MASTER);
}
if (config->vendor & STM32_SPI_NSS_IGNORE) {
LL_SPI_SetNSSMode(spi, LL_SPI_NSS_SOFT);
} else {
if (config->operation & SPI_OP_MODE_SLAVE) {
LL_SPI_SetNSSMode(spi, LL_SPI_NSS_HARD_OUTPUT);
} else {
LL_SPI_SetNSSMode(spi, LL_SPI_NSS_SOFT);
}
}
LL_SPI_SetDataWidth(spi, LL_SPI_DATAWIDTH_8BIT);
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F3X)
LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER);
#endif
LL_SPI_SetStandard(spi, LL_SPI_PROTOCOL_MOTOROLA);
/* At this point, it's mandatory to set this on the context! */
data->ctx.config = config;
spi_context_cs_configure(&data->ctx);
SYS_LOG_DBG("Installed config %p: freq %uHz (div = %u),"
" mode %u/%u/%u, slave %u",
config, clock >> br, 1 << br,
(SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) ? 1 : 0,
(SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) ? 1 : 0,
(SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) ? 1 : 0,
config->slave);
return 0;
}
static void spi_stm32_transmit(SPI_TypeDef *spi, struct spi_stm32_data *data)
{
if (spi_context_tx_on(&data->ctx)) {
LL_SPI_TransmitData8(spi, UNALIGNED_GET((u8_t *)
(data->ctx.tx_buf)));
} else {
/* Transmit NOP byte */
LL_SPI_TransmitData8(spi, 0);
}
spi_context_update_tx(&data->ctx, 1);
}
static void spi_stm32_receive(SPI_TypeDef *spi, struct spi_stm32_data *data)
{
if (spi_context_rx_on(&data->ctx)) {
u8_t byte = LL_SPI_ReceiveData8(spi);
UNALIGNED_PUT(byte, (u8_t *)data->ctx.rx_buf);
} else {
LL_SPI_ReceiveData8(spi);
}
spi_context_update_rx(&data->ctx, 1);
}
static int spi_stm32_release(struct spi_config *config)
{
struct spi_stm32_data *data = CONFIG_DATA(config);
spi_context_unlock_unconditionally(&data->ctx);
return 0;
}
static int transceive(struct spi_config *config,
const struct spi_buf *tx_bufs, u32_t tx_count,
struct spi_buf *rx_bufs, u32_t rx_count,
bool asynchronous, struct k_poll_signal *signal)
{
const struct spi_stm32_config *cfg = CONFIG_CFG(config);
struct spi_stm32_data *data = CONFIG_DATA(config);
SPI_TypeDef *spi = cfg->spi;
int ret;
if (!tx_count && !rx_count) {
return 0;
}
#ifndef CONFIG_SPI_STM32_INTERRUPT
if (asynchronous) {
return -ENOTSUP;
}
#endif
spi_context_lock(&data->ctx, asynchronous, signal);
ret = spi_stm32_configure(config);
if (ret) {
return ret;
}
/* Set buffers info */
spi_context_buffers_setup(&data->ctx, tx_bufs, tx_count,
rx_bufs, rx_count, 1);
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F3X)
/* Flush RX buffer */
while (LL_SPI_IsActiveFlag_RXNE(spi)) {
(void) LL_SPI_ReceiveData8(spi);
}
#endif
LL_SPI_Enable(spi);
spi_context_cs_control(&data->ctx, true);
#ifdef CONFIG_SPI_STM32_INTERRUPT
if (rx_bufs) {
LL_SPI_EnableIT_RXNE(spi);
}
LL_SPI_EnableIT_TXE(spi);
spi_context_wait_for_completion(&data->ctx);
#else
do {
/* Keep transmitting NOP data until RX data left */
if ((spi_context_tx_on(&data->ctx) ||
spi_context_rx_on(&data->ctx)) &&
LL_SPI_IsActiveFlag_TXE(spi)) {
spi_stm32_transmit(spi, data);
}
if (spi_context_rx_on(&data->ctx) &&
LL_SPI_IsActiveFlag_RXNE(spi)) {
spi_stm32_receive(spi, data);
}
} while (spi_context_tx_on(&data->ctx) ||
spi_context_rx_on(&data->ctx));
spi_context_complete(&data->ctx, 0);
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F3X)
/* Flush RX buffer */
while (LL_SPI_IsActiveFlag_RXNE(spi)) {
(void) LL_SPI_ReceiveData8(spi);
}
#endif
if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
while (LL_SPI_IsActiveFlag_BSY(spi)) {
/* NOP */
}
LL_SPI_Disable(spi);
}
#endif
spi_context_release(&data->ctx, 0);
return 0;
}
static int spi_stm32_transceive(struct spi_config *config,
const struct spi_buf *tx_bufs, u32_t tx_count,
struct spi_buf *rx_bufs, u32_t rx_count)
{
return transceive(config, tx_bufs, tx_count,
rx_bufs, rx_count, false, NULL);
}
#ifdef CONFIG_POLL
static int spi_stm32_transceive_async(struct spi_config *config,
const struct spi_buf *tx_bufs,
size_t tx_count,
struct spi_buf *rx_bufs,
size_t rx_count,
struct k_poll_signal *async)
{
return transceive(config, tx_bufs, tx_count,
rx_bufs, rx_count, true, async);
}
#endif /* CONFIG_POLL */
static const struct spi_driver_api api_funcs = {
.transceive = spi_stm32_transceive,
#ifdef CONFIG_POLL
.transceive_async = spi_stm32_transceive_async,
#endif
.release = spi_stm32_release,
};
static int spi_stm32_init(struct device *dev)
{
struct spi_stm32_data *data __attribute__((unused)) = dev->driver_data;
const struct spi_stm32_config *cfg = dev->config->config_info;
__ASSERT_NO_MSG(device_get_binding(STM32_CLOCK_CONTROL_NAME));
clock_control_on(device_get_binding(STM32_CLOCK_CONTROL_NAME),
(clock_control_subsys_t) &cfg->pclken);
#ifdef CONFIG_SPI_STM32_INTERRUPT
cfg->irq_config(dev);
#endif
spi_context_release(&data->ctx, 0);
return 0;
}
#ifdef CONFIG_SPI_1
#ifdef CONFIG_SPI_STM32_INTERRUPT
static void spi_stm32_irq_config_func_1(struct device *port);
#endif
static const struct spi_stm32_config spi_stm32_cfg_1 = {
.spi = (SPI_TypeDef *) SPI1_BASE,
.pclken = {
.enr = LL_APB2_GRP1_PERIPH_SPI1,
.bus = STM32_CLOCK_BUS_APB2
},
#ifdef CONFIG_SPI_STM32_INTERRUPT
.irq_config = spi_stm32_irq_config_func_1,
#endif
};
static struct spi_stm32_data spi_stm32_dev_data_1 = {
SPI_CONTEXT_INIT_LOCK(spi_stm32_dev_data_1, ctx),
SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_1, ctx),
};
DEVICE_AND_API_INIT(spi_stm32_1, CONFIG_SPI_1_NAME, &spi_stm32_init,
&spi_stm32_dev_data_1, &spi_stm32_cfg_1,
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&api_funcs);
#ifdef CONFIG_SPI_STM32_INTERRUPT
static void spi_stm32_irq_config_func_1(struct device *dev)
{
IRQ_CONNECT(SPI1_IRQn, CONFIG_SPI_1_IRQ_PRI,
spi_stm32_isr, DEVICE_GET(spi_stm32_1), 0);
irq_enable(SPI1_IRQn);
}
#endif
#endif /* CONFIG_SPI_1 */
#ifdef CONFIG_SPI_2
#ifdef CONFIG_SPI_STM32_INTERRUPT
static void spi_stm32_irq_config_func_2(struct device *port);
#endif
static const struct spi_stm32_config spi_stm32_cfg_2 = {
.spi = (SPI_TypeDef *) SPI2_BASE,
.pclken = {
.enr = LL_APB1_GRP1_PERIPH_SPI2,
.bus = STM32_CLOCK_BUS_APB1
},
#ifdef CONFIG_SPI_STM32_INTERRUPT
.irq_config = spi_stm32_irq_config_func_2,
#endif
};
static struct spi_stm32_data spi_stm32_dev_data_2 = {
SPI_CONTEXT_INIT_LOCK(spi_stm32_dev_data_2, ctx),
SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_2, ctx),
};
DEVICE_AND_API_INIT(spi_stm32_2, CONFIG_SPI_2_NAME, &spi_stm32_init,
&spi_stm32_dev_data_2, &spi_stm32_cfg_2,
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&api_funcs);
#ifdef CONFIG_SPI_STM32_INTERRUPT
static void spi_stm32_irq_config_func_2(struct device *dev)
{
IRQ_CONNECT(SPI2_IRQn, CONFIG_SPI_2_IRQ_PRI,
spi_stm32_isr, DEVICE_GET(spi_stm32_2), 0);
irq_enable(SPI2_IRQn);
}
#endif
#endif /* CONFIG_SPI_2 */
#ifdef CONFIG_SPI_3
#ifdef CONFIG_SPI_STM32_INTERRUPT
static void spi_stm32_irq_config_func_3(struct device *port);
#endif
static const struct spi_stm32_config spi_stm32_cfg_3 = {
.spi = (SPI_TypeDef *) SPI3_BASE,
.pclken = {
.enr = LL_APB1_GRP1_PERIPH_SPI3,
.bus = STM32_CLOCK_BUS_APB1
},
#ifdef CONFIG_SPI_STM32_INTERRUPT
.irq_config = spi_stm32_irq_config_func_3,
#endif
};
static struct spi_stm32_data spi_stm32_dev_data_3 = {
SPI_CONTEXT_INIT_LOCK(spi_stm32_dev_data_3, ctx),
SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_3, ctx),
};
DEVICE_AND_API_INIT(spi_stm32_3, CONFIG_SPI_3_NAME, &spi_stm32_init,
&spi_stm32_dev_data_3, &spi_stm32_cfg_3,
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&api_funcs);
#ifdef CONFIG_SPI_STM32_INTERRUPT
static void spi_stm32_irq_config_func_3(struct device *dev)
{
IRQ_CONNECT(SPI3_IRQn, CONFIG_SPI_3_IRQ_PRI,
spi_stm32_isr, DEVICE_GET(spi_stm32_3), 0);
irq_enable(SPI3_IRQn);
}
#endif
#endif /* CONFIG_SPI_3 */

26
drivers/spi/spi_ll_stm32.h Normal file
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@ -0,0 +1,26 @@
/*
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SPI_H_
#define _STM32_SPI_H_
#include "spi_context.h"
typedef void (*irq_config_func_t)(struct device *port);
struct spi_stm32_config {
struct stm32_pclken pclken;
SPI_TypeDef *spi;
#ifdef CONFIG_SPI_STM32_INTERRUPT
irq_config_func_t irq_config;
#endif
};
struct spi_stm32_data {
struct spi_context ctx;
};
#endif /* _STM32_SPI_H_ */

12
include/drivers/spi/spi_ll_stm32.h Normal file
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@ -0,0 +1,12 @@
/*
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _DRIVERS_STM32_SPI_H_
#define _DRIVERS_STM32_SPI_H_
#define STM32_SPI_NSS_IGNORE BIT(0)
#endif /* _DRIVERS_STM32_SPI_H_ */