timer: add support for MIPS CP0 timer

This commit adds a kernel device driver for the MIPS CP0 timer.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>

CODEOWNERS

@@ -388,6 +388,7 @@
 /drivers/timer/*cavs*                     @dcpleung
 /drivers/timer/*stm32_lptim*              @FRASTM
 /drivers/timer/*leon_gptimer*             @martin-aberg
+/drivers/timer/*mips_cp0*                 @frantony
 /drivers/timer/*rcar_cmt*                 @julien-massot
 /drivers/timer/*esp32c3_sys*              @uLipe
 /drivers/timer/*sam0_rtc*                 @bendiscz

arch/mips/include/mips/mipsregs.h

@@ -11,6 +11,8 @@
 #define _ZEPHYR_ARCH_MIPS_INCLUDE_MIPS_MIPSREGS_H_
 
 #define CP0_BADVADDR	$8
+#define CP0_COUNT	$9
+#define CP0_COMPARE	$11
 #define CP0_STATUS	$12
 #define CP0_CAUSE	$13
 #define CP0_EPC		$14

drivers/timer/CMakeLists.txt

@@ -19,6 +19,7 @@ zephyr_library_sources_ifdef(CONFIG_MCHP_XEC_RTOS_TIMER mchp_xec_rtos_timer.c)
 zephyr_library_sources_ifdef(CONFIG_MCUX_LPTMR_TIMER mcux_lptmr_timer.c)
 zephyr_library_sources_ifdef(CONFIG_MCUX_OS_TIMER mcux_os_timer.c)
 zephyr_library_sources_ifdef(CONFIG_MCUX_GPT_TIMER mcux_gpt_timer.c)
+zephyr_library_sources_ifdef(CONFIG_MIPS_CP0_TIMER mips_cp0_timer.c)
 zephyr_library_sources_ifdef(CONFIG_NATIVE_POSIX_TIMER native_posix_timer.c)
 zephyr_library_sources_ifdef(CONFIG_NPCX_ITIM_TIMER npcx_itim_timer.c)
 zephyr_library_sources_ifdef(CONFIG_NRF_RTC_TIMER nrf_rtc_timer.c)

drivers/timer/Kconfig

@@ -70,6 +70,7 @@ source "drivers/timer/Kconfig.mchp_xec_rtos"
 source "drivers/timer/Kconfig.mcux_gpt"
 source "drivers/timer/Kconfig.mcux_lptmr"
 source "drivers/timer/Kconfig.mcux_os"
+source "drivers/timer/Kconfig.mips_cp0"
 source "drivers/timer/Kconfig.native_posix"
 source "drivers/timer/Kconfig.npcx_itim"
 source "drivers/timer/Kconfig.nrf_rtc"

drivers/timer/Kconfig.mips_cp0

@@ -0,0 +1,9 @@
+# Copyright (c) 2021 Antony Pavlov <antonynpavlov@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config MIPS_CP0_TIMER
+	bool "MIPS CP0 Timer"
+	depends on MIPS
+	help
+	  This module implements a kernel device driver for the MIPS CP0 timer.

drivers/timer/mips_cp0_timer.c

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2020, 2021 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * based on riscv_machine_timer.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <drivers/timer/system_timer.h>
+#include <sys_clock.h>
+#include <spinlock.h>
+#include <soc.h>
+#include <mips/mipsregs.h>
+
+#define CYC_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec() \
+				 / (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
+#define MAX_CYC INT_MAX
+#define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
+#define MIN_DELAY 1000
+
+static struct k_spinlock lock;
+static uint32_t last_count;
+
+static ALWAYS_INLINE void set_cp0_compare(uint32_t time)
+{
+	_mips_write_32bit_c0_register(CP0_COMPARE, time);
+}
+
+static ALWAYS_INLINE uint32_t get_cp0_count(void)
+{
+	return _mips_read_32bit_c0_register(CP0_COUNT);
+}
+
+static void timer_isr(const void *arg)
+{
+	ARG_UNUSED(arg);
+
+	k_spinlock_key_t key = k_spin_lock(&lock);
+	uint32_t now = get_cp0_count();
+	uint32_t dticks = ((now - last_count) / CYC_PER_TICK);
+
+	last_count = now;
+
+	uint32_t next = last_count + CYC_PER_TICK;
+
+	if (next - now < MIN_DELAY) {
+		next += CYC_PER_TICK;
+	}
+	set_cp0_compare(next);
+
+	k_spin_unlock(&lock, key);
+	sys_clock_announce(1);
+}
+
+/* tickless kernel is not supported */
+uint32_t sys_clock_elapsed(void)
+{
+	return 0;
+}
+
+uint32_t sys_clock_cycle_get_32(void)
+{
+	return get_cp0_count();
+}
+
+static int sys_clock_driver_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	IRQ_CONNECT(MIPS_MACHINE_TIMER_IRQ, 0, timer_isr, NULL, 0);
+	last_count = get_cp0_count();
+	set_cp0_compare(last_count + CYC_PER_TICK);
+
+	irq_enable(MIPS_MACHINE_TIMER_IRQ);
+
+	return 0;
+}
+
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
+	 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);