dts: arm64: intel_socfpga: Add Cadence QSPI NOR flash device tree element

This patch is to add Cadence QSPI NOR flash device tree element
for the Cadence QSPI NOR flash driver bringup

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>

dts/arm64/intel/intel_socfpga_agilex.dtsi

@@ -8,6 +8,7 @@
 #include <arm64/armv8-a.dtsi>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
 #include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
+#include <mem.h>
 
 / {
 	cpus {
@@ -72,6 +73,27 @@
 		#clock-cells = <1>;
 	};
 
+	/*
+	 * This qspi setting included
+	 * The QSPI controller register and
+	 * The QSPI data register
+	 * QSPI REG  <0xff8d2000 0x100>
+	 * QSPI DATA <0xff900000 0x100000>
+	 */
+	qspi: qspi@ff8d2000 {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		compatible = "cdns,qspi-nor";
+		reg = <0xff8d2000 0x100>,
+		      <0xff900000 0x100000>;
+		reg-names = "qspi_reg", "qspi_data";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL
+			     IRQ_DEFAULT_PRIORITY>;
+		clock-frequency = <50000000>;
+		status = "disabled";
+	};
+
 	mem0: memory@10000000 {
 		device_type = "memory";
 		reg = <0x10000000 0x200000>;

dts/bindings/flash_controller/cdns,qspi-nor.yaml

@@ -0,0 +1,14 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cadence Quad-SPI NOR flash controller
+
+compatible: "cdns,qspi-nor"
+
+include: flash-controller.yaml
+
+properties:
+    clock-frequency:
+      type: int
+      required: true
+      description: clock frequency information for Cadence QSPI NOR Flash

dts/bindings/flash_controller/micron,mt25qu02g.yaml

@@ -0,0 +1,13 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Micron QSPI Flash
+
+compatible: "micron,mt25qu02g"
+
+include: flash-controller.yaml
+
+properties:
+    size:
+      type: int
+      description: Flash memory size in bit.