From 929dc717cfa60195632cf50cc529cf994942e088 Mon Sep 17 00:00:00 2001 From: Bradley Bolen Date: Mon, 22 Jul 2019 10:23:47 -0400 Subject: [PATCH] soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen --- CODEOWNERS | 1 + dts/arm/xilinx/zynqmp.dtsi | 90 +++++++++++++++++++++++++ soc/arm/xilinx_zynqmp/CMakeLists.txt | 7 ++ soc/arm/xilinx_zynqmp/Kconfig.defconfig | 35 ++++++++++ soc/arm/xilinx_zynqmp/Kconfig.soc | 10 +++ soc/arm/xilinx_zynqmp/dts_fixup.h | 16 +++++ soc/arm/xilinx_zynqmp/linker.ld | 8 +++ soc/arm/xilinx_zynqmp/soc.c | 31 +++++++++ soc/arm/xilinx_zynqmp/soc.h | 28 ++++++++ 9 files changed, 226 insertions(+) create mode 100644 dts/arm/xilinx/zynqmp.dtsi create mode 100644 soc/arm/xilinx_zynqmp/CMakeLists.txt create mode 100644 soc/arm/xilinx_zynqmp/Kconfig.defconfig create mode 100644 soc/arm/xilinx_zynqmp/Kconfig.soc create mode 100644 soc/arm/xilinx_zynqmp/dts_fixup.h create mode 100644 soc/arm/xilinx_zynqmp/linker.ld create mode 100644 soc/arm/xilinx_zynqmp/soc.c create mode 100644 soc/arm/xilinx_zynqmp/soc.h diff --git a/CODEOWNERS b/CODEOWNERS index 32fc14542b..77afda033b 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -188,6 +188,7 @@ /dts/riscv/riscv32-fe310.dtsi @nategraff-sifive /dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda /dts/arm/armv7-r.dtsi @bbolen +/dts/arm/xilinx/ @bbolen /dts/xtensa/xtensa.dtsi @ydamigos /dts/bindings/ @galak /dts/bindings/can/ @alexanderwachter diff --git a/dts/arm/xilinx/zynqmp.dtsi b/dts/arm/xilinx/zynqmp.dtsi new file mode 100644 index 0000000000..f9dbfe7026 --- /dev/null +++ b/dts/arm/xilinx/zynqmp.dtsi @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019 Lexmark International, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include +#include +#include + +/ { + soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@f9010000 { + compatible = "arm,gic"; + reg = <0xf9010000 0x1000>, + <0xf9020000 0x100>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&core_intc 0>; + label = "GIC"; + status = "okay"; + }; + + flash0: flash@c0000000 { + compatible = "soc-nv-flash"; + reg = <0xc0000000 DT_SIZE_K(64)>; + }; + + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0 DT_SIZE_K(256)>; + }; + + uart0: uart@ff000000 { + compatible = "xlnx,xuartps"; + reg = <0xff000000 0x4c>; + status = "disabled"; + interrupts = <21 0 IRQ_TYPE_LEVEL>; + interrupt-names = "irq_0"; + label = "UART_0"; + }; + + ttc0: timer@ff110000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <36 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>, + <37 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>, + <38 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>; + interrupt-names = "irq_0", "irq_1", "irq_2"; + reg = <0xff110000 0x1000>; + label = "ttc0"; + }; + + ttc1: timer@ff120000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <39 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>, + <40 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>, + <41 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>; + interrupt-names = "irq_0", "irq_1", "irq_2"; + reg = <0xff120000 0x1000>; + label = "ttc1"; + }; + + ttc2: timer@ff130000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <42 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>, + <43 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>, + <44 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>; + interrupt-names = "irq_0", "irq_1", "irq_2"; + reg = <0xff130000 0x1000>; + label = "ttc2"; + }; + + ttc3: timer@ff140000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <45 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>, + <46 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>, + <47 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>; + interrupt-names = "irq_0", "irq_1", "irq_2"; + reg = <0xff140000 0x1000>; + label = "ttc3"; + }; + }; +}; diff --git a/soc/arm/xilinx_zynqmp/CMakeLists.txt b/soc/arm/xilinx_zynqmp/CMakeLists.txt new file mode 100644 index 0000000000..3d770db77d --- /dev/null +++ b/soc/arm/xilinx_zynqmp/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c +) diff --git a/soc/arm/xilinx_zynqmp/Kconfig.defconfig b/soc/arm/xilinx_zynqmp/Kconfig.defconfig new file mode 100644 index 0000000000..5cfed93644 --- /dev/null +++ b/soc/arm/xilinx_zynqmp/Kconfig.defconfig @@ -0,0 +1,35 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_XILINX_ZYNQMP + +config SOC + default "xilinx_zynqmp" + +config NUM_IRQS + int + # must be >= the highest interrupt number used + # - include the UART interrupts + default 220 + +config 2ND_LVL_ISR_TBL_OFFSET + default 1 + +config MAX_IRQ_PER_AGGREGATOR + default 219 + +config NUM_2ND_LEVEL_AGGREGATORS + default 1 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 12000000 + +config FLASH_SIZE + default $(dt_int_val,DT_FLASH_SIZE) + +config FLASH_BASE_ADDRESS + default $(dt_hex_val,DT_FLASH_BASE_ADDRESS) + +endif diff --git a/soc/arm/xilinx_zynqmp/Kconfig.soc b/soc/arm/xilinx_zynqmp/Kconfig.soc new file mode 100644 index 0000000000..4ad0bc70fa --- /dev/null +++ b/soc/arm/xilinx_zynqmp/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# +config SOC_XILINX_ZYNQMP + bool "Xilinx ZynqMP" + select CPU_CORTEX_R5 + select GIC + select MULTI_LEVEL_INTERRUPTS + select 2ND_LEVEL_INTERRUPTS diff --git a/soc/arm/xilinx_zynqmp/dts_fixup.h b/soc/arm/xilinx_zynqmp/dts_fixup.h new file mode 100644 index 0000000000..70b231a114 --- /dev/null +++ b/soc/arm/xilinx_zynqmp/dts_fixup.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019 Lexmark International, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#undef DT_INST_0_XLNX_XUARTPS_IRQ_0 +#define DT_INST_0_XLNX_XUARTPS_IRQ_0 ((DT_INST_0_XLNX_XUARTPS_IRQ_IRQ_0 + 1) << 8) + +#undef DT_INST_0_CDNS_TTC_IRQ_0 +#define DT_INST_0_CDNS_TTC_IRQ_0 ((DT_INST_0_CDNS_TTC_IRQ_IRQ_0 + 1) << 8) +#undef DT_INST_0_CDNS_TTC_IRQ_1 +#define DT_INST_0_CDNS_TTC_IRQ_1 ((DT_INST_0_CDNS_TTC_IRQ_IRQ_1 + 1) << 8) +#undef DT_INST_0_CDNS_TTC_IRQ_2 +#define DT_INST_0_CDNS_TTC_IRQ_2 ((DT_INST_0_CDNS_TTC_IRQ_IRQ_2 + 1) << 8) diff --git a/soc/arm/xilinx_zynqmp/linker.ld b/soc/arm/xilinx_zynqmp/linker.ld new file mode 100644 index 0000000000..507494c0d4 --- /dev/null +++ b/soc/arm/xilinx_zynqmp/linker.ld @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2019 Lexmark International, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include diff --git a/soc/arm/xilinx_zynqmp/soc.c b/soc/arm/xilinx_zynqmp/soc.c new file mode 100644 index 0000000000..68fae6a2c8 --- /dev/null +++ b/soc/arm/xilinx_zynqmp/soc.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019 Lexmark International, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include +#include +#include + +#include +/** + * + * @brief Perform basic hardware initialization + * + * @return 0 + */ + +static int soc_init(struct device *arg) +{ + ARG_UNUSED(arg); + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + return 0; +} + +SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/arm/xilinx_zynqmp/soc.h b/soc/arm/xilinx_zynqmp/soc.h new file mode 100644 index 0000000000..6c212d1c99 --- /dev/null +++ b/soc/arm/xilinx_zynqmp/soc.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2019 Lexmark International, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#ifndef _BOARD__H_ +#define _BOARD__H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef _ASMLANGUAGE + +#include +#include + +#endif /* !_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BOARD__H_ */