drivers: serial: ns16550: use MMIO device depending on Kconfig option
Add a new selectable Kconfig option to decide wether the device driver is a MMIO device or not. Previous to this patch, the decision was maded based on the existence of a definition in <soc.h>. The design was fragile, as code compiled anyway if the definition was not present. All platforms/boards that had the definition in <soc.h> select the Kconfig option in their respective defconfig files. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
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@ -67,6 +67,9 @@ config QEMU_ICOUNT
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config QEMU_ICOUNT_SHIFT
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default 5
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config UART_NS16550_ACCESS_IOPORT
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default y if UART_NS16550
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endif # BOARD_QEMU_X86_LAKEMONT
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if BOARD_QEMU_X86_TINY
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@ -58,6 +58,12 @@ config UART_NS16550_ACCESS_WORD_ONLY
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16550 (DesignWare UART) only allows word access, byte access will raise
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exception.
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config UART_NS16550_ACCESS_IOPORT
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bool
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help
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When enabled, NS16550 will not be a memory mapped device. This option
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must be selected at SoC/board level if needed.
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menu "NS16550 Workarounds"
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config UART_NS16550_WA_ISR_REENABLE_INTERRUPT
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@ -207,7 +207,7 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
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#define IIRC(dev) (((struct uart_ns16550_dev_data *)(dev)->data)->iir_cache)
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#ifdef UART_NS16550_ACCESS_IOPORT
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#ifdef CONFIG_UART_NS16550_ACCESS_IOPORT
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#define INBYTE(x) sys_in8(x)
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#define INWORD(x) sys_in32(x)
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#define OUTBYTE(x, d) sys_out8(d, x)
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@ -217,7 +217,7 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
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#define INWORD(x) sys_read32(x)
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#define OUTBYTE(x, d) sys_write8(d, x)
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#define OUTWORD(x, d) sys_write32(d, x)
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#endif /* UART_NS16550_ACCESS_IOPORT */
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#endif /* CONFIG_UART_NS16550_ACCESS_IOPORT */
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#ifdef CONFIG_UART_NS16550_ACCESS_WORD_ONLY
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#undef INBYTE
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@ -228,7 +228,7 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
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/* device config */
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struct uart_ns16550_device_config {
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#ifndef UART_NS16550_ACCESS_IOPORT
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#ifndef CONFIG_UART_NS16550_ACCESS_IOPORT
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DEVICE_MMIO_ROM;
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#else
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uint32_t port;
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@ -252,7 +252,7 @@ struct uart_ns16550_device_config {
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/** Device data structure */
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struct uart_ns16550_dev_data {
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#ifndef UART_NS16550_ACCESS_IOPORT
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#ifndef CONFIG_UART_NS16550_ACCESS_IOPORT
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DEVICE_MMIO_RAM;
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#endif
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struct uart_config uart_config;
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@ -276,7 +276,7 @@ struct uart_ns16550_dev_data {
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#if defined(UART_REG_ADDR_INTERVAL)
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#define DEFAULT_REG_INTERVAL UART_REG_ADDR_INTERVAL
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#elif defined(UART_NS16550_ACCESS_IOPORT)
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#elif defined(CONFIG_UART_NS16550_ACCESS_IOPORT)
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#define DEFAULT_REG_INTERVAL 1
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#else
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#define DEFAULT_REG_INTERVAL 4
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@ -301,7 +301,7 @@ static const struct uart_driver_api uart_ns16550_driver_api;
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static inline uintptr_t get_port(const struct device *dev)
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{
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#ifndef UART_NS16550_ACCESS_IOPORT
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#ifndef CONFIG_UART_NS16550_ACCESS_IOPORT
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return DEVICE_MMIO_GET(dev);
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#else
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const struct uart_ns16550_device_config *config = dev->config;
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@ -353,7 +353,7 @@ static int uart_ns16550_configure(const struct device *dev,
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ARG_UNUSED(dev_data);
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ARG_UNUSED(dev_cfg);
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#ifndef UART_NS16550_ACCESS_IOPORT
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#ifndef CONFIG_UART_NS16550_ACCESS_IOPORT
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#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
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if (dev_cfg->pcie) {
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struct pcie_mbar mbar;
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@ -1085,7 +1085,7 @@ static const struct uart_driver_api uart_ns16550_driver_api = {
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pcie_irq_enable(DT_INST_REG_ADDR(n), irq); \
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}
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#ifdef UART_NS16550_ACCESS_IOPORT
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#ifdef CONFIG_UART_NS16550_ACCESS_IOPORT
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#define DEV_CONFIG_REG_INIT(n) \
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.port = DT_INST_REG_ADDR(n),
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#else
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@ -19,4 +19,7 @@ config UART_PIPE_ON_DEV_NAME
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endif
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config UART_NS16550_ACCESS_IOPORT
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default y if UART_NS16550
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endif
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@ -11,4 +11,7 @@ config SOC
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 25000000 if HPET_TIMER
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config UART_NS16550_ACCESS_IOPORT
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default y if UART_NS16550
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endif
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