dts/arm/st: Add stm32u5 base and initial device
Add initial basic description for Cortex-M33 based stm32u5 soc series. This encompass description for base nodes, such as: - cpu - flash - clocks - sram Additionally, provide description for variant stm32u575Xi. Related to clocks nodes, added bindings for stm32u5 specific rcc node as well as msi and pll clocks. Header file stm32_clock_control.h was also updated to support these new bindings. Note that for compatibility with existing definitions, clock node describing main pll clock, known as "PLL1", was given two labels: "pll" and "pll1". Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
parent
6c41bf6135
commit
93c005de3e
105
dts/arm/st/u5/stm32u5.dtsi
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105
dts/arm/st/u5/stm32u5.dtsi
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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <freq.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <8>;
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};
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(16)>;
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status = "disabled";
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};
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clk_msis: clk-msis {
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#clock-cells = <0>;
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compatible = "st,stm32u5-msi-clock";
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msi-range = <4>; /* 4MHz (reset value) */
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll1: pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32u5-pll-clock";
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status = "disabled";
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};
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};
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soc {
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flash-controller@40022000 {
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compatible = "st,stm32u5-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x40022000 0x400>;
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interrupts = <6 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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label = "FLASH_STM32";
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};
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};
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rcc: rcc@46020c00 {
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compatible = "st,stm32u5-rcc";
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clocks-controller;
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#clock-cells = <2>;
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reg = <0x46020c00 0x400>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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7
dts/arm/st/u5/stm32u575.dtsi
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7
dts/arm/st/u5/stm32u575.dtsi
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@ -0,0 +1,7 @@
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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u5.dtsi>
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21
dts/arm/st/u5/stm32u575Xi.dtsi
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21
dts/arm/st/u5/stm32u575Xi.dtsi
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/u5/stm32u575.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(786)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_M(2)>;
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};
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};
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};
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};
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37
dts/bindings/clock/st,stm32u5-msi-clock.yaml
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37
dts/bindings/clock/st,stm32u5-msi-clock.yaml
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# Copyright (c) 2021, Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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description: STM32U5 Multi Speed Internal Clock
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compatible: "st,stm32u5-msi-clock"
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include:
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- name: st,stm32-msi-clock.yaml
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property-blocklist:
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- msi-range
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properties:
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msi-range:
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default: 4
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required: true
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type: int
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description: |
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MSI clock ranges
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enum:
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- 0 # range 0 around 48 MHz
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- 1 # range 1 around 24 MHz
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- 2 # range 2 around 16 MHz
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- 3 # range 3 around 12 MHz
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- 4 # range 4 around 4 MHz (reset value)
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- 5 # range 5 around 2 MHz
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- 6 # range 6 around 1.33 MHz
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- 7 # range 7 around 1 MHz
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- 8 # range 8 around 3.072 MHz
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- 9 # range 9 around 1.536 MHz
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- 10 # range 10 around 1.024 MHz
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- 11 # range 11 around 768 KHz
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- 12 # range 12 around 400 KHz
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- 13 # range 13 around 200 KHz
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- 14 # range 14 around 133 KHz
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- 15 # range 14 around 100 KHz
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67
dts/bindings/clock/st,stm32u5-pll-clock.yaml
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67
dts/bindings/clock/st,stm32u5-pll-clock.yaml
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# Copyright (c) 2021, Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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description: |
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PLL node binding for STM32U5 devices
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It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.
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Only main PLL (PLL1) is supported for now.
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These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with
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an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
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clock in this acceptable range.
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Each PLL can have up to 3 output clocks and for each output clock, the
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frequency can be computed with the following formulae:
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f(PLL_P) = f(VCO clock) / PLLP
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f(PLL_Q) = f(VCO clock) / PLLQ
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f(PLL_R) = f(VCO clock) / PLLR
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with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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Note: To reduce the power consumption, it is recommended to configure the VCOx
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clock output to the lowest frequency.
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The PLL output frequency must not exceed 160 MHz.
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compatible: "st,stm32u5-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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div-m:
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type: int
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required: true
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description: |
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Prescaler for PLLx
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input clock
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Valid range: 1 - 16
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mul-n:
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type: int
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required: true
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description: |
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PLLx multiplication factor for VCO
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Valid range: 4 - 512
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div-q:
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type: int
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required: false
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description: |
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PLLx DIVQ division factor
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Valid range: 2 - 128
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div-r:
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type: int
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required: true
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description: |
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PLLx DIVR division factor
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Valid range: 2 - 128
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22
dts/bindings/clock/st,stm32u5-rcc.yaml
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dts/bindings/clock/st,stm32u5-rcc.yaml
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# Copyright (c) 2021, Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32U5 Reset and Clock controller node.
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For more description confere st,stm32-rcc.yaml
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compatible: "st,stm32u5-rcc"
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include: st,stm32-rcc.yaml
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properties:
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apb3-prescaler:
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type: int
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required: false
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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#endif
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#endif
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), ahb_prescaler) || \
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), ahb_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32f0_rcc), ahb_prescaler)
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32f0_rcc), ahb_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), ahb_prescaler)
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#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
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#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
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#else
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#else
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#define STM32_AHB_PRESCALER CONFIG_CLOCK_STM32_AHB_PRESCALER
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#define STM32_AHB_PRESCALER CONFIG_CLOCK_STM32_AHB_PRESCALER
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb1_prescaler) || \
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb1_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32f0_rcc), apb1_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32f0_rcc), apb1_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), apb1_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), apb1_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), apb1_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), apb1_prescaler)
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), apb1_prescaler)
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#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
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#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
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#endif
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#endif
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb2_prescaler) || \
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb2_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), apb2_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), apb2_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), apb2_prescaler) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), apb2_prescaler)
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), apb2_prescaler)
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#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
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#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
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#define STM32_APB2_PRESCALER CONFIG_CLOCK_STM32_APB2_PRESCALER
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#define STM32_APB2_PRESCALER CONFIG_CLOCK_STM32_APB2_PRESCALER
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#endif
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#endif
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), apb3_prescaler)
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#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
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#endif
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), ahb3_prescaler)
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), ahb3_prescaler)
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#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
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#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
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#else
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#else
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@ -161,6 +168,7 @@
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay)
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay)
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#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
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#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
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#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32_rcc, okay) || \
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#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32_rcc, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32f0_rcc, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32f0_rcc, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32h7_rcc, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32h7_rcc, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32u5_rcc, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32wb_rcc, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32wb_rcc, okay) || \
|
||||||
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32wl_rcc, okay)) && \
|
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32wl_rcc, okay)) && \
|
||||||
DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks)
|
DT_NODE_HAS_PROP(DT_NODELABEL(rcc), clocks)
|
||||||
|
@ -252,10 +261,12 @@
|
||||||
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
|
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
|
||||||
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay) || \
|
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay) || \
|
||||||
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
|
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
|
||||||
|
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
|
||||||
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay)) && \
|
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay)) && \
|
||||||
DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
|
DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
|
||||||
#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
|
#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
|
||||||
#define STM32_PLL_SRC_MSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
|
#define STM32_PLL_SRC_MSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
|
||||||
|
#define STM32_PLL_SRC_MSIS DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
|
||||||
#define STM32_PLL_SRC_HSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
|
#define STM32_PLL_SRC_HSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
|
||||||
#define STM32_PLL_SRC_HSE DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
|
#define STM32_PLL_SRC_HSE DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
|
||||||
#define STM32_PLL_SRC_PLL2 DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
|
#define STM32_PLL_SRC_PLL2 DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
|
||||||
|
@ -275,16 +286,21 @@
|
||||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
|
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
|
||||||
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
|
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
|
||||||
#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
|
#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
|
||||||
#else
|
#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
|
||||||
#define STM32_MSI_RANGE CONFIG_CLOCK_STM32_MSI_RANGE
|
#define STM32_MSI_RANGE CONFIG_CLOCK_STM32_MSI_RANGE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
|
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
|
||||||
#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
|
#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
|
||||||
#else
|
#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
|
||||||
#define STM32_MSI_PLL_MODE CONFIG_CLOCK_STM32_MSI_PLL_MODE
|
#define STM32_MSI_PLL_MODE CONFIG_CLOCK_STM32_MSI_PLL_MODE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
|
||||||
|
#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
|
||||||
|
#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
|
||||||
|
#endif
|
||||||
|
|
||||||
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay)
|
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay)
|
||||||
#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
|
#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
|
||||||
#else
|
#else
|
||||||
|
|
Loading…
Reference in a new issue