interrupt-controller: intc_esp32c3: make logs optional
Allowing cleaner debug experience and preventing unwanted outputs during debug. Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
This commit is contained in:
Felipe Neves
Anas Nashif
parent
16be75b68f
commit
949a6a8e53
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@ -8,3 +8,13 @@ config INTC_ESP32C3
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help
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Enables the esp32c3 interrupt controller driver to handle ISR
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management at SoC level.
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config INTC_ESP32C3_DECISIONS_LOG
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bool "Enables Espressif's interrupt allocator logging"
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depends on INTC_ESP32C3
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select LOG
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help
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Enable this option to visualize information on decisions made by the
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interrupt allocator. This has no impact on the interrupt allocator usage
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but may be valuable for debugging purposes. When enabled, messages are
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print to the serial console.
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@ -21,6 +21,17 @@
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#include <logging/log.h>
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LOG_MODULE_REGISTER(intc_esp32c3, CONFIG_LOG_DEFAULT_LEVEL);
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/*
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* Define this to debug the choices made when allocating the interrupt. This leads to much debugging
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* output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
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* being triggered, that is why it is separate from the normal LOG* scheme.
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*/
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#ifdef CONFIG_INTC_ESP32C3_DECISIONS_LOG
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# define INTC_LOG(...) LOG_INF(__VA_ARGS__)
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#else
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# define INTC_LOG(...) do {} while (0)
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#endif
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#define ESP32C3_INTC_DEFAULT_PRIORITY 15
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#define ESP32C3_INTC_DEFAULT_THRESHOLD 1
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#define ESP32C3_INTC_DISABLED_SLOT 31
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@ -37,7 +48,7 @@ static void esp_intr_default_isr(const void *arg)
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__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
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mcause &= SOC_MCAUSE_EXP_MASK;
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LOG_DBG("Spurious interrupt, mcause: %ld, source %d", mcause, soc_intr_get_next_source());
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INTC_LOG("Spurious interrupt, mcause: %ld, source %d", mcause, soc_intr_get_next_source());
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}
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static uint32_t esp_intr_find_irq_for_source(uint32_t source)
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@ -48,13 +59,13 @@ static uint32_t esp_intr_find_irq_for_source(uint32_t source)
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uint32_t irq = (source / ESP32C3_INTC_SRCS_PER_IRQ);
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if (irq > ESP32C3_INTC_AVAILABLE_IRQS) {
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LOG_DBG("Clamping the source: %d no more IRQs available", source);
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INTC_LOG("Clamping the source: %d no more IRQs available", source);
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irq = ESP32C3_INTC_AVAILABLE_IRQS;
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} else if (irq == 0) {
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irq = 1;
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}
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LOG_DBG("Found IRQ: %d for source: %d", irq, source);
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INTC_LOG("Found IRQ: %d for source: %d", irq, source);
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return irq;
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}
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@ -118,7 +129,7 @@ int esp_intr_alloc(int source,
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esp_intr_enabled_mask[1] |= (1 << (source - 32));
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}
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LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
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irq_unlock(key);
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@ -145,7 +156,7 @@ int esp_intr_disable(int source)
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esp_intr_enabled_mask[1] &= ~(1 << (source - 32));
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}
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LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
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irq_unlock(key);
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@ -171,7 +182,7 @@ int esp_intr_enable(int source)
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esp_intr_enabled_mask[1] |= (1 << (source - 32));
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}
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LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
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irq_enable(irq);
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@ -182,7 +193,7 @@ int esp_intr_enable(int source)
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uint32_t esp_intr_get_enabled_intmask(int status_mask_number)
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{
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LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
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if (status_mask_number == 0) {
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@ -13,7 +13,6 @@
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/*
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* Interrupt allocation flags - These flags can be used to specify
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* which interrupt qualities the code calling esp_intr_alloc* needs.
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*
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*/
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/* Keep the LEVELx values as they are here; they match up with (1<<level) */
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@ -7,67 +7,67 @@
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
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#define WIFI_MAC_INTR_SOURCE 0 /**< interrupt of WiFi MAC, level*/
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#define WIFI_MAC_NMI_SOURCE 1 /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
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#define WIFI_PWR_INTR_SOURCE 2 /**< */
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#define WIFI_BB_INTR_SOURCE 3 /**< interrupt of WiFi BB, level, we can do some calibartion*/
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#define BT_MAC_INTR_SOURCE 4 /**< will be cancelled*/
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#define BT_BB_INTR_SOURCE 5 /**< interrupt of BT BB, level*/
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#define BT_BB_NMI_SOURCE 6 /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
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#define RWBT_INTR_SOURCE 7 /**< interrupt of RWBT, level*/
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#define RWBLE_INTR_SOURCE 8 /**< interrupt of RWBLE, level*/
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#define RWBT_NMI_SOURCE 9 /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
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#define RWBLE_NMI_SOURCE 10 /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
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#define I2C_MASTER_SOURCE 11 /**< interrupt of I2C Master, level*/
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#define SLC0_INTR_SOURCE 12 /**< interrupt of SLC0, level*/
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#define SLC1_INTR_SOURCE 13 /**< interrupt of SLC1, level*/
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#define APB_CTRL_INTR_SOURCE 14 /**< interrupt of APB ctrl, ?*/
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#define UHCI0_INTR_SOURCE 15 /**< interrupt of UHCI0, level*/
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#define GPIO_INTR_SOURCE 16 /**< interrupt of GPIO, level*/
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#define GPIO_NMI_SOURCE 17 /**< interrupt of GPIO, NMI*/
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#define SPI1_INTR_SOURCE 18 /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
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#define SPI2_INTR_SOURCE 19 /**< interrupt of SPI2, level*/
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#define I2S1_INTR_SOURCE 20 /**< interrupt of I2S1, level*/
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#define UART0_INTR_SOURCE 21 /**< interrupt of UART0, level*/
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#define UART1_INTR_SOURCE 22 /**< interrupt of UART1, level*/
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#define LEDC_INTR_SOURCE 23 /**< interrupt of LED PWM, level*/
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#define EFUSE_INTR_SOURCE 24 /**< interrupt of efuse, level, not likely to use*/
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#define TWAI_INTR_SOURCE 25 /**< interrupt of can, level*/
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#define USB_INTR_SOURCE 26 /**< interrupt of USB, level*/
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#define RTC_CORE_INTR_SOURCE 27 /**< interrupt of rtc core, level, include rtc watchdog*/
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#define RMT_INTR_SOURCE 28 /**< interrupt of remote controller, level*/
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#define I2C_EXT0_INTR_SOURCE 29 /**< interrupt of I2C controller1, level*/
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#define TIMER1_INTR_SOURCE 30
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#define TIMER2_INTR_SOURCE 31
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#define TG0_T0_LEVEL_INTR_SOURCE 32 /**< interrupt of TIMER_GROUP0, TIMER0, level*/
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#define TG0_WDT_LEVEL_INTR_SOURCE 33 /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
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#define TG1_T0_LEVEL_INTR_SOURCE 34 /**< interrupt of TIMER_GROUP1, TIMER0, level*/
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#define TG1_WDT_LEVEL_INTR_SOURCE 35 /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
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#define CACHE_IA_INTR_SOURCE 36 /**< interrupt of Cache Invalied Access, LEVEL*/
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#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 37 /**< interrupt of system timer 0, EDGE*/
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#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 38 /**< interrupt of system timer 1, EDGE*/
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#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 39 /**< interrupt of system timer 2, EDGE*/
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#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40 /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
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#define ICACHE_PRELOAD0_INTR_SOURCE 41 /**< interrupt of ICache perload operation, LEVEL*/
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#define ICACHE_SYNC0_INTR_SOURCE 42 /**< interrupt of instruction cache sync done, LEVEL*/
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#define APB_ADC_INTR_SOURCE 43 /**< interrupt of APB ADC, LEVEL*/
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#define DMA_CH0_INTR_SOURCE 44 /**< interrupt of general DMA channel 0, LEVEL*/
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#define DMA_CH1_INTR_SOURCE 45 /**< interrupt of general DMA channel 1, LEVEL*/
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#define DMA_CH2_INTR_SOURCE 46 /**< interrupt of general DMA channel 2, LEVEL*/
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#define RSA_INTR_SOURCE 47 /**< interrupt of RSA accelerator, level*/
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#define AES_INTR_SOURCE 48 /**< interrupt of AES accelerator, level*/
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#define SHA_INTR_SOURCE 49 /**< interrupt of SHA accelerator, level*/
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#define FROM_CPU_INTR0_SOURCE 50 /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
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#define FROM_CPU_INTR1_SOURCE 51 /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
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#define FROM_CPU_INTR2_SOURCE 52 /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
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#define FROM_CPU_INTR3_SOURCE 53 /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
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#define ASSIST_DEBUG_INTR_SOURCE 54 /**< interrupt of Assist debug module, LEVEL*/
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#define DMA_APBPERI_PMS_INTR_SOURCE 55
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#define CORE0_IRAM0_PMS_INTR_SOURCE 56
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#define CORE0_DRAM0_PMS_INTR_SOURCE 57
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#define CORE0_PIF_PMS_INTR_SOURCE 58
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#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 59
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#define BAK_PMS_VIOLATE_INTR_SOURCE 60
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#define CACHE_CORE0_ACS_INTR_SOURCE 61
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#define WIFI_MAC_INTR_SOURCE 0
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#define WIFI_MAC_NMI_SOURCE 1
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#define WIFI_PWR_INTR_SOURCE 2
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#define WIFI_BB_INTR_SOURCE 3
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#define BT_MAC_INTR_SOURCE 4
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#define BT_BB_INTR_SOURCE 5
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#define BT_BB_NMI_SOURCE 6
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#define RWBT_INTR_SOURCE 7
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#define RWBLE_INTR_SOURCE 8
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#define RWBT_NMI_SOURCE 9
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#define RWBLE_NMI_SOURCE 10
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#define I2C_MASTER_SOURCE 11
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#define SLC0_INTR_SOURCE 12
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#define SLC1_INTR_SOURCE 13
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#define APB_CTRL_INTR_SOURCE 14
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#define UHCI0_INTR_SOURCE 15
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#define GPIO_INTR_SOURCE 16
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#define GPIO_NMI_SOURCE 17
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#define SPI1_INTR_SOURCE 18
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#define SPI2_INTR_SOURCE 19
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#define I2S1_INTR_SOURCE 20
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#define UART0_INTR_SOURCE 21
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#define UART1_INTR_SOURCE 22
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#define LEDC_INTR_SOURCE 23
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#define EFUSE_INTR_SOURCE 24
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#define TWAI_INTR_SOURCE 25
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#define USB_INTR_SOURCE 26
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#define RTC_CORE_INTR_SOURCE 27
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#define RMT_INTR_SOURCE 28
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#define I2C_EXT0_INTR_SOURCE 29
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#define TIMER1_INTR_SOURCE 30
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#define TIMER2_INTR_SOURCE 31
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#define TG0_T0_LEVEL_INTR_SOURCE 32
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#define TG0_WDT_LEVEL_INTR_SOURCE 33
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#define TG1_T0_LEVEL_INTR_SOURCE 34
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#define TG1_WDT_LEVEL_INTR_SOURCE 35
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#define CACHE_IA_INTR_SOURCE 36
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#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 37
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#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 38
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#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 39
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#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40
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#define ICACHE_PRELOAD0_INTR_SOURCE 41
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#define ICACHE_SYNC0_INTR_SOURCE 42
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#define APB_ADC_INTR_SOURCE 43
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#define DMA_CH0_INTR_SOURCE 44
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#define DMA_CH1_INTR_SOURCE 45
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#define DMA_CH2_INTR_SOURCE 46
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#define RSA_INTR_SOURCE 47
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#define AES_INTR_SOURCE 48
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#define SHA_INTR_SOURCE 49
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#define FROM_CPU_INTR0_SOURCE 50
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#define FROM_CPU_INTR1_SOURCE 51
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#define FROM_CPU_INTR2_SOURCE 52
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#define FROM_CPU_INTR3_SOURCE 53
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#define ASSIST_DEBUG_INTR_SOURCE 54
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#define DMA_APBPERI_PMS_INTR_SOURCE 55
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#define CORE0_IRAM0_PMS_INTR_SOURCE 56
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#define CORE0_DRAM0_PMS_INTR_SOURCE 57
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#define CORE0_PIF_PMS_INTR_SOURCE 58
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#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 59
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#define BAK_PMS_VIOLATE_INTR_SOURCE 60
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#define CACHE_CORE0_ACS_INTR_SOURCE 61
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#endif
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