ipm: remove ipm_cavs_idc driver
The ipm_cavs_idc driver was used with the old intel_s1000 board which has been removed. On the audio DSP side, the IDC under CAVS is being handled by SoC layer code. Now the ipm_cavs_idc is not needed anymore for anything. So remove it. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
f618522144
commit
94cc1bf455
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@ -10,7 +10,6 @@ zephyr_library_sources_ifdef(CONFIG_IPM_IMX_REV2 ipm_imx.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_MHU ipm_mhu.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_STM32_IPCC ipm_stm32_ipcc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_NRFX ipm_nrfx_ipc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_CAVS_IDC ipm_cavs_idc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_STM32_HSEM ipm_stm32_hsem.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_CAVS_HOST ipm_cavs_host.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_SEDI ipm_sedi.c)
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@ -1,14 +1,6 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2022, Intel Corporation
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config IPM_CAVS_IDC
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bool "CAVS DSP Intra-DSP Communication (IDC) driver"
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default y if MP_NUM_CPUS > 1 && SMP
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depends on CAVS_ICTL && DT_HAS_INTEL_ADSP_IDC_ENABLED
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help
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Driver for the Intra-DSP Communication (IDC) channel for
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cross SoC communications.
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config IPM_CALLBACK_ASYNC
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bool "Deliver callbacks asynchronously"
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default y if IPM_CAVS_HOST
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@ -1,242 +0,0 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/drivers/ipm.h>
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#include <zephyr/arch/common/sys_io.h>
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#include <soc.h>
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#include <zephyr/irq.h>
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#include "ipm_cavs_idc.h"
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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extern void z_sched_ipi(void);
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#endif
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struct cavs_idc_data {
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ipm_callback_t cb;
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void *user_data;
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};
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static struct cavs_idc_data cavs_idc_device_data;
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static void cavs_idc_isr(const struct device *dev)
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{
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struct cavs_idc_data *drv_data = dev->data;
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uint32_t i, id;
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void *ext;
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uint32_t idctfc;
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uint32_t curr_cpu_id = arch_curr_cpu()->id;
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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bool do_sched_ipi = false;
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#endif
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unsigned int num_cpus = arch_num_cpus();
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for (i = 0; i < num_cpus; i++) {
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if (i == curr_cpu_id) {
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/* skip current core */
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continue;
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}
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idctfc = idc_read(IPC_IDCTFC(i), curr_cpu_id);
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if ((idctfc & IPC_IDCTFC_BUSY) == 0) {
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/* No message from this core */
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continue;
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}
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/* Extract the message */
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id = idctfc & IPC_IDCTFC_MSG_MASK;
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switch (id) {
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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case IPM_CAVS_IDC_MSG_SCHED_IPI_ID:
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do_sched_ipi = true;
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break;
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#endif
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default:
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if (drv_data->cb != NULL) {
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ext = UINT_TO_POINTER(
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idc_read(IPC_IDCTEFC(i), curr_cpu_id) &
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IPC_IDCTEFC_MSG_MASK);
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drv_data->cb(dev, drv_data->user_data, id, ext);
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}
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break;
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}
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/* Reset busy bit by writing to it */
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idctfc |= IPC_IDCTFC_BUSY;
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idc_write(IPC_IDCTFC(i), curr_cpu_id, idctfc);
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}
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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if (do_sched_ipi) {
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z_sched_ipi();
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}
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#endif
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}
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static int cavs_idc_send(const struct device *dev, int wait, uint32_t id,
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const void *data, int size)
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{
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uint32_t curr_cpu_id = arch_curr_cpu()->id;
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uint32_t ext = POINTER_TO_UINT(data);
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uint32_t reg;
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bool busy;
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int i;
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if ((wait != 0) || (size != 0)) {
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return -ENOTSUP;
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}
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/* Check if any core is still busy */
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busy = false;
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unsigned int num_cpus = arch_num_cpus();
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for (i = 0; i < num_cpus; i++) {
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if (i == curr_cpu_id) {
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/* skip current core */
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continue;
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}
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reg = idc_read(IPC_IDCITC(i), curr_cpu_id);
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if ((reg & IPC_IDCITC_BUSY) != 0) {
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busy = true;
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break;
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}
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}
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/* Can't send if busy */
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if (busy) {
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return -EBUSY;
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}
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id &= IPC_IDCITC_MSG_MASK;
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ext &= IPC_IDCIETC_MSG_MASK;
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ext |= IPC_IDCIETC_DONE; /* always clear DONE bit */
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for (i = 0; i < num_cpus; i++) {
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if (i == curr_cpu_id) {
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/* skip current core */
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continue;
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}
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idc_write(IPC_IDCIETC(i), curr_cpu_id, ext);
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idc_write(IPC_IDCITC(i), curr_cpu_id, id | IPC_IDCITC_BUSY);
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}
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return 0;
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}
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static int cavs_idc_max_data_size_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/* IDC can send an ID (of 31 bits, the header) and
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* another data of 30 bits (the extension). It cannot
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* send a whole message over. Best we can do is send
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* a 4-byte aligned pointer.
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*
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* So return 0 here for max data size.
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*/
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return 0;
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}
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static uint32_t cavs_idc_max_id_val_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return IPM_CAVS_IDC_ID_MASK;
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}
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static void cavs_idc_register_callback(const struct device *dev,
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ipm_callback_t cb,
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void *user_data)
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{
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struct cavs_idc_data *drv_data = dev->data;
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drv_data->cb = cb;
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drv_data->user_data = user_data;
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}
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static int cavs_idc_set_enabled(const struct device *dev, int enable)
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{
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int i, j;
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uint32_t mask;
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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/* With scheduler IPI, IDC must always be enabled. */
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if (enable == 0) {
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return -ENOTSUP;
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}
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#endif
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unsigned int num_cpus = arch_num_cpus();
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for (i = 0; i < num_cpus; i++) {
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mask = 0;
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if (enable) {
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for (j = 0; j < num_cpus; j++) {
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if (i == j) {
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continue;
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}
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mask |= IPC_IDCCTL_IDCTBIE(j);
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}
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}
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idc_write(IPC_IDCCTL, i, mask);
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/* FIXME: when we have API to enable IRQ on specific core. */
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sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs_intc0)) + 0x04 +
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CAVS_ICTL_INT_CPU_OFFSET(i),
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CAVS_IRQ_NUMBER(DT_INST_IRQN(0)));
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}
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return 0;
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}
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static int cavs_idc_init(const struct device *dev)
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{
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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cavs_idc_isr, DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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return 0;
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}
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static const struct ipm_driver_api cavs_idc_driver_api = {
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.send = cavs_idc_send,
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.register_callback = cavs_idc_register_callback,
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.max_data_size_get = cavs_idc_max_data_size_get,
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.max_id_val_get = cavs_idc_max_id_val_get,
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.set_enabled = cavs_idc_set_enabled,
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};
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DEVICE_DT_INST_DEFINE(0, &cavs_idc_init, NULL,
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&cavs_idc_device_data, NULL,
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PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&cavs_idc_driver_api);
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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int cavs_idc_smp_init(void)
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{
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/* Enable IDC for scheduler IPI */
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cavs_idc_set_enabled(dev, 1);
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return 0;
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}
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#ifndef CONFIG_SMP_BOOT_DELAY
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SYS_INIT(cavs_idc_smp_init, SMP, 0);
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#endif
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#endif
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@ -1,68 +0,0 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_
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#define ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_
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#define DT_DRV_COMPAT intel_adsp_idc
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#include <intel_adsp_ipc_devtree.h>
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/* Redeclaration of the earlier IDC register API for platforms being
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* held back on this driver.
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*/
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# ifndef IPC_DSP_BASE
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# define IPC_DSP_BASE(core) (INTEL_ADSP_IDC_REG_ADDRESS + 0x80 * (core))
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# endif
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#define IPC_IDCTFC(x) (x * 0x10)
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#define IPC_IDCTFC_BUSY BIT(31)
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#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF
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#define IPC_IDCTEFC(x) (0x4 + x * 0x10)
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#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF
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#define IPC_IDCITC(x) (0x8 + x * 0x10)
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#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF
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#define IPC_IDCITC_BUSY BIT(31)
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#define IPC_IDCIETC(x) (0xc + x * 0x10)
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#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF
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#define IPC_IDCIETC_DONE BIT(30)
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#define IPC_IDCCTL 0x50
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#define IPC_IDCCTL_IDCTBIE(x) BIT(x)
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#define IPM_CAVS_IDC_ID_MASK \
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(CAVS_IDC_TYPE(CAVS_IDC_TYPE_MASK) | \
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CAVS_IDC_HEADER(CAVS_IDC_HEADER_MASK))
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/* IDC message type. */
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#define CAVS_IDC_TYPE_SHIFT 24U
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#define CAVS_IDC_TYPE_MASK 0x7FU
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#define CAVS_IDC_TYPE(x) \
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(((x) & CAVS_IDC_TYPE_MASK) << CAVS_IDC_TYPE_SHIFT)
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/* IDC message header. */
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#define CAVS_IDC_HEADER_MASK 0xFFFFFFU
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#define CAVS_IDC_HEADER(x) ((x) & CAVS_IDC_HEADER_MASK)
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/* IDC message extension. */
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#define CAVS_IDC_EXTENSION_MASK 0x3FFFFFFFU
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#define CAVS_IDC_EXTENSION(x) ((x) & CAVS_IDC_EXTENSION_MASK)
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/* Scheduler IPI message (type 0x7F, header 'IPI' in ascii) */
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_DATA 0
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_ID \
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(CAVS_IDC_TYPE(0x7FU) | CAVS_IDC_HEADER(0x495049U))
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static inline uint32_t idc_read(uint32_t reg, uint32_t core_id)
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{
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return *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg));
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}
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static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val)
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{
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*((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)) = val;
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}
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int cavs_idc_smp_init(const struct device *dev);
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#endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_ */
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@ -5,4 +5,3 @@ CONFIG_SMP_BOOT_DELAY=y
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CONFIG_SCHED_CPU_MASK=y
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CONFIG_IPM=y
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CONFIG_IPM_CAVS_HOST=y
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CONFIG_IPM_CAVS_IDC=n
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