soc: intel_adsp: cavs: start using zephyr power management
Start using zephyr power management in cavs platform in a similar way that is already done in ace. This commit only addresses the power off/on sequence. Runtime power management is not implemented. Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This commit is contained in:
Jaska Uimonen
Anas Nashif
parent
59fe77a6b4
commit
95168e6776
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@ -16,6 +16,7 @@
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <0>;
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cpu-power-states = <&d3>;
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i-cache-line-size = <64>;
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d-cache-line-size = <64>;
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};
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@ -24,18 +25,33 @@
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <1>;
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cpu-power-states = <&d3>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <2>;
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cpu-power-states = <&d3>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <3>;
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cpu-power-states = <&d3>;
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};
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};
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power-states {
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/* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force.
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* The procedure is triggered by IPC from the HOST (SET_DX).
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*/
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d3: off {
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compatible = "zephyr,power-state";
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power-state-name = "soft-off";
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min-residency-us = <2147483647>;
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exit-latency-us = <0>;
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};
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};
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@ -16,6 +16,7 @@
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <0>;
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cpu-power-states = <&d3>;
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i-cache-line-size = <64>;
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d-cache-line-size = <64>;
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};
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@ -24,6 +25,19 @@
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <1>;
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cpu-power-states = <&d3>;
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};
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};
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power-states {
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/* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force.
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* The procedure is triggered by IPC from the HOST (SET_DX).
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*/
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d3: off {
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compatible = "zephyr,power-state";
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power-state-name = "soft-off";
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min-residency-us = <2147483647>;
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exit-latency-us = <0>;
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};
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};
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@ -9,6 +9,7 @@ zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_library_sources(
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sram.c
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power.c
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power_down_cavs.S
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)
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if(CONFIG_SMP OR CONFIG_MP_MAX_NUM_CPUS GREATER 1)
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108
soc/xtensa/intel_adsp/cavs/asm_ldo_management.h
Normal file
108
soc/xtensa/intel_adsp/cavs/asm_ldo_management.h
Normal file
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@ -0,0 +1,108 @@
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/* Copyright (c) 2023 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__
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#define __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__
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#ifdef _ASMLANGUAGE
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#define SHIM_BASE 0x00071F00
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#define SHIM_LDOCTL 0xA4
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#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0 | 3 << 16)
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#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
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#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16)
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#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
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#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
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#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
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#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS (BIT(0) | BIT(16))
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#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
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.macro m_cavs_set_ldo_state state, ax
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movi \ax, (SHIM_BASE + SHIM_LDOCTL)
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s32i \state, \ax, 0
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memw
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/* wait loop > 300ns (min 100ns required) */
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movi \ax, 128
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1 :
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addi \ax, \ax, -1
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nop
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bnez \ax, 1b
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.endm
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.macro m_cavs_set_hpldo_state state, ax, ay
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movi \ax, (SHIM_BASE + SHIM_LDOCTL)
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l32i \ay, \ax, 0
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movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK)
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and \ay, \ax, \ay
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or \state, \ay, \state
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m_cavs_set_ldo_state \state, \ax
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.endm
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.macro m_cavs_set_lpldo_state state, ax, ay
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movi \ax, (SHIM_BASE + SHIM_LDOCTL)
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l32i \ay, \ax, 0
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/* LP SRAM mask */
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movi \ax, ~(SHIM_LDOCTL_LPSRAM_MASK)
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and \ay, \ax, \ay
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or \state, \ay, \state
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m_cavs_set_ldo_state \state, \ax
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.endm
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.macro m_cavs_set_ldo_on_state ax, ay, az
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movi \ay, (SHIM_BASE + SHIM_LDOCTL)
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l32i \az, \ay, 0
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movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
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and \az, \ax, \az
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movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_ON | SHIM_LDOCTL_LPSRAM_LDO_ON)
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or \ax, \az, \ax
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m_cavs_set_ldo_state \ax, \ay
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.endm
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.macro m_cavs_set_ldo_off_state ax, ay, az
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/* wait loop > 300ns (min 100ns required) */
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movi \ax, 128
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1 :
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addi \ax, \ax, -1
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nop
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bnez \ax, 1b
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movi \ay, (SHIM_BASE + SHIM_LDOCTL)
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l32i \az, \ay, 0
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movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
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and \az, \az, \ax
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movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_OFF | SHIM_LDOCTL_LPSRAM_LDO_OFF)
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or \ax, \ax, \az
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s32i \ax, \ay, 0
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l32i \ax, \ay, 0
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.endm
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.macro m_cavs_set_ldo_bypass_state ax, ay, az
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/* wait loop > 300ns (min 100ns required) */
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movi \ax, 128
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1 :
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addi \ax, \ax, -1
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nop
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bnez \ax, 1b
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movi \ay, (SHIM_BASE + SHIM_LDOCTL)
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l32i \az, \ay, 0
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movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
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and \az, \az, \ax
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movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_BYPASS | SHIM_LDOCTL_LPSRAM_LDO_BYPASS)
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or \ax, \ax, \az
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s32i \ax, \ay, 0
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l32i \ax, \ay, 0
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.endm
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#endif
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#endif /* __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__ */
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76
soc/xtensa/intel_adsp/cavs/asm_memory_management.h
Normal file
76
soc/xtensa/intel_adsp/cavs/asm_memory_management.h
Normal file
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@ -0,0 +1,76 @@
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/* Copyright (c) 2023 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __ZEPHYR_CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__
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#define __ZEPHYR_CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__
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#ifdef _ASMLANGUAGE
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#define HSPGCTL0 0x71D10
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#define HSRMCTL0 0x71D14
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#define HSPGISTS0 0x71D18
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#define LSPGCTL 0x71D50
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#define LSRMCTL 0x71D54
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#define LSPGISTS 0x71D58
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#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x))
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#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x))
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#define LPSRAM_MASK 0x1
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/**
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* Macro powers down entire HPSRAM. On entry literals and code for section from
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* where this code is executed need to be placed in memory which is not
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* HPSRAM (in case when this code is located in HPSRAM, lock memory in L1$ or
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* L1 SRAM)
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*/
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.macro m_cavs_hpsram_power_down_entire ax, ay, az
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/* SEGMENT #0 */
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movi \az, SHIM_HSPGCTL(0)
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movi \ax, SHIM_HSPGISTS(0)
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movi \ay, 0x1FFFFFFF /* HPSRAM_MASK(0) */
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s32i \ay, \ax, 0
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memw
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1 :
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l32i \ax, \az, 0
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bne \ax, \ay, 1b
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/* SEGMENT #1 */
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movi \az, SHIM_HSPGCTL(1)
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movi \ax, SHIM_HSPGISTS(1)
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movi \ay, 0x0FFFFFFF /* HPSRAM_MASK(1) */
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s32i \ay, \ax, 0
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memw
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1 :
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l32i \ax, \az, 0
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bne \ax, \ay, 1b
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.endm
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.macro m_cavs_hpsram_power_change segment_index, mask, ax, ay, az
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movi \ax, SHIM_HSPGCTL(\segment_index)
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movi \ay, SHIM_HSPGISTS(\segment_index)
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s32i \mask, \ax, 0
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memw
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/* assumed that HDA shared dma buffer will be in LPSRAM */
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1 :
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l32i \ax, \ay, 0
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bne \ax, \mask, 1b
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.endm
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.macro m_cavs_lpsram_power_down_entire ax, ay, az, loop_cnt_addr
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movi \az, LSPGISTS
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movi \ax, LSPGCTL
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movi \ay, LPSRAM_MASK
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s32i \ay, \ax, 0
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memw
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/* assumed that HDA shared dma buffer will be in LPSRAM */
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movi \ax, \loop_cnt_addr
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l32i \ax, \ax, 0
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1 :
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addi \ax, \ax, -1
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bnez \ax, 1b
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.endm
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#endif
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#endif
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@ -10,6 +10,9 @@
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#include <xtensa/hal.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/pm/pm.h>
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#include <zephyr/device.h>
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#include <cpu_init.h>
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#include <adsp_shim.h>
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#include <adsp_clk.h>
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@ -32,6 +35,84 @@ LOG_MODULE_REGISTER(soc);
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#endif
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#ifdef CONFIG_PM
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#define SRAM_ALIAS_BASE 0x9E000000
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#define SRAM_ALIAS_MASK 0xFF000000
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#define EBB_BANKS_IN_SEGMENT 32
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#define SRAM_ALIAS_OFFSET 0x20000000
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#define L2_INTERRUPT_NUMBER 4
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#define L2_INTERRUPT_MASK (1<<L2_INTERRUPT_NUMBER)
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#define L3_INTERRUPT_NUMBER 6
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#define L3_INTERRUPT_MASK (1<<L3_INTERRUPT_NUMBER)
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#define ALL_USED_INT_LEVELS_MASK (L2_INTERRUPT_MASK | L3_INTERRUPT_MASK)
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struct core_state {
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uint32_t intenable;
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};
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static struct core_state core_desc[CONFIG_MP_MAX_NUM_CPUS] = {{0}};
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/**
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* @brief Power down procedure.
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*
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* Locks its code in L1 cache and shuts down memories.
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* NOTE: there's no return from this function.
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*
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* @param disable_lpsram flag if LPSRAM is to be disabled (whole)
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* @param hpsram_pg_mask pointer to memory segments power gating mask
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* (each bit corresponds to one ebb)
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*/
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extern void power_down_cavs(bool disable_lpsram, uint32_t *hpsram_pg_mask);
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static inline void __sparse_cache *uncache_to_cache(void *address)
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{
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return (void __sparse_cache *)((uintptr_t)(address) | SRAM_ALIAS_OFFSET);
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}
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__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(substate_id);
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uint32_t cpu = arch_proc_id();
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if (state == PM_STATE_SOFT_OFF) {
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core_desc[cpu].intenable = XTENSA_RSR("INTENABLE");
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z_xt_ints_off(0xffffffff);
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soc_cpus_active[cpu] = false;
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z_xtensa_cache_flush_inv_all();
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if (cpu == 0) {
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uint32_t ebb = EBB_BANKS_IN_SEGMENT;
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/* turn off all HPSRAM banks - get a full bitmap */
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uint32_t hpsram_mask = (1 << ebb) - 1;
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/* do power down - this function won't return */
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power_down_cavs(true, uncache_to_cache(&hpsram_mask));
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} else {
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z_xt_ints_on(core_desc[cpu].intenable);
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k_cpu_idle();
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}
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} else {
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__ASSERT(false, "invalid argument - unsupported power state");
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}
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}
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/* Handle SOC specific activity after Low Power Mode Exit */
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__weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(substate_id);
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uint32_t cpu = arch_proc_id();
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if (state == PM_STATE_SOFT_OFF) {
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soc_cpus_active[cpu] = true;
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z_xtensa_cache_flush_inv_all();
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z_xt_ints_on(core_desc[cpu].intenable);
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} else {
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__ASSERT(false, "invalid argument - unsupported power state");
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}
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}
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#endif
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__imr void power_init(void)
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{
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157
soc/xtensa/intel_adsp/cavs/power_down_cavs.S
Normal file
157
soc/xtensa/intel_adsp/cavs/power_down_cavs.S
Normal file
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@ -0,0 +1,157 @@
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/* Copyright (c) 2022 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "asm_ldo_management.h"
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#include "asm_memory_management.h"
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#define IPC_HOST_BASE 0x00071E00
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#define IPC_DIPCIDD 0x18
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#define IPC_DIPCIDR 0x10
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.section .text, "ax"
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.align 64
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power_down_literals:
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.literal_position
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set_dx_reply:
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/* BUSY (bit31), MODULE_MSG (bit30), reply (bit29), SET_DX (bit 24-28: 7) */
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.word 0xE7000000
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sram_dis_loop_cnt:
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.word 4096
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.global power_down_cavs
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.type power_down_cavs, @function
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/**
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* Perform power down.
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*
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* Depending on arguments, memories are switched off.
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* A2 - argument for LPSRAM
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* A3 - pointer to array containing power gating mask.
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*Size of array is determined by MEMORY_SEGMENTS define.
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* A4 - platform type
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* A5 - response_to_ipc
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*/
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#define b_enable_lpsram a2
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#define pu32_hpsram_mask a3
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#define temp_reg0 a6
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#define temp_reg1 a7
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#define temp_reg2 a8
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#define temp_reg3 a9
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#define host_base a10
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#define pfl_reg a15
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#define MAX_MEMORY_SEGMENTS 2
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power_down_cavs:
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entry sp, 32
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/**
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* effectively executes:
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* xthal_dcache_region_lock(&literals, 128);
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* xthal_dcache_region_lock(&powerdown, 256);
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* xthal_dcache_region_lock(&pu32_hpsram_mask, 64);
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*/
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movi pfl_reg, power_down_literals
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dpfl pfl_reg, 0
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dpfl pfl_reg, 64
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movi pfl_reg, power_down_cavs
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ipfl pfl_reg, 0
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ipfl pfl_reg, 64
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ipfl pfl_reg, 128
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ipfl pfl_reg, 192
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mov pfl_reg, pu32_hpsram_mask
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dpfl pfl_reg, 0
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movi host_base, IPC_HOST_BASE
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_PD_DISABLE_LPSRAM:
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/* effectively executes:
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* if (b_enable_lpsram){
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* cavs_lpsram_power_down_entire();
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* }
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*/
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beqz b_enable_lpsram, _PD_DISABLE_HPSRAM
|
||||
m_cavs_lpsram_power_down_entire temp_reg0, temp_reg1, temp_reg2, sram_dis_loop_cnt
|
||||
j _PD_DISABLE_HPSRAM
|
||||
|
||||
_PD_DISABLE_HPSRAM:
|
||||
/* if value in memory pointed by pu32_hpsram_mask = 0
|
||||
(hpsram_pwrgating_mask) - do not disable hpsram. */
|
||||
beqz pu32_hpsram_mask, _PD_SEND_IPC
|
||||
|
||||
/* mandatory sequence for LDO ON - effectively executes:
|
||||
* m_cavs_s_set_ldo_hpsram_on_state();
|
||||
* WAIT_300NS();
|
||||
*/
|
||||
movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_ON
|
||||
m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
|
||||
movi temp_reg0, 128
|
||||
1 :
|
||||
addi temp_reg0, temp_reg0, -1
|
||||
bnez temp_reg0, 1b
|
||||
|
||||
|
||||
/* effectively executes:
|
||||
* for (size_t seg_index = (MAX_MEMORY_SEGMENTS - 1); seg_index >= 0;
|
||||
* --seg_index) {
|
||||
* cavs_hpsram_power_change(seg_index, mask[seg_index]);
|
||||
* }
|
||||
* where mask is given in pu32_hpsram_mask register
|
||||
*/
|
||||
|
||||
.set seg_index, MAX_MEMORY_SEGMENTS - 1
|
||||
.rept MAX_MEMORY_SEGMENTS
|
||||
l32i temp_reg0, pu32_hpsram_mask, 4 * seg_index
|
||||
m_cavs_hpsram_power_change\
|
||||
/*segment_index=*/ seg_index,\
|
||||
/*mask=*/ temp_reg0,\
|
||||
temp_reg1,\
|
||||
temp_reg2,\
|
||||
temp_reg3
|
||||
.set seg_index, seg_index - 1
|
||||
.endr
|
||||
|
||||
|
||||
/* mandatory sequence for LDO OFF - effectively executes:
|
||||
* WAIT_300NS();
|
||||
* m_cavs_set_ldo_hpsram_on_state()
|
||||
*/
|
||||
movi temp_reg0, 128
|
||||
1 :
|
||||
addi temp_reg0, temp_reg0, -1
|
||||
bnez temp_reg0, 1b
|
||||
|
||||
movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_OFF
|
||||
m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
|
||||
|
||||
_PD_SEND_IPC:
|
||||
/* Send IPC reply for SET_DX message */
|
||||
movi temp_reg1, 0
|
||||
s32i temp_reg1, host_base, IPC_DIPCIDD
|
||||
|
||||
movi temp_reg1, set_dx_reply
|
||||
l32i temp_reg1, temp_reg1, 0
|
||||
s32i temp_reg1, host_base, IPC_DIPCIDR
|
||||
|
||||
_PD_SLEEP:
|
||||
/* effecfively executes:
|
||||
* xmp_spin()
|
||||
* waiti 5
|
||||
*/
|
||||
movi temp_reg0, 128
|
||||
loop:
|
||||
addi temp_reg0, temp_reg0, -1
|
||||
bnez temp_reg0, loop
|
||||
|
||||
extw
|
||||
extw
|
||||
waiti 5
|
||||
1:
|
||||
j 1b
|
||||
|
||||
.size power_down_cavs , . - power_down_cavs
|
||||
|
||||
|
||||
Loading…
Reference in a new issue