arm: st_stm32: Add support for STM32F4x SoC family
This patch adds support for the STMicroelectronics STM32F4x family in the STM32 MCU line. Configuration is included for the STM32F401RE MCU. Acknowledgements to Pawel Wodnicki's earlier submission from February that was used as a starting point for this port. In the end, we rewrote all of it. Change-Id: I9797c282ac3c0cc66a63b9d34821de95df537ef6 Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
This commit is contained in:
Amit Kucheria
Kumar Gala
parent
31a3f6a70e
commit
95e7fb6c98
29
arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series
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29
arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series
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@ -0,0 +1,29 @@
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# Kconfig.defconfig.series - ST Microelectronics STM32F4 MCU line
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#
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# Copyright (c) 2016 Linaro Limited
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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if SOC_SERIES_STM32F4X
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source "arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f4*"
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config SOC_SERIES
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default stm32f4
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config NUM_IRQ_PRIO_BITS
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int
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default 4
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endif # SOC_SERIES_STM32F4X
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34
arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f401re
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34
arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f401re
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@ -0,0 +1,34 @@
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# Kconfig - ST STM32F401RE MCU configuration options
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#
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# Copyright (c) 2016 Linaro Limited.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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if SOC_STM32F401RE
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config SOC
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string
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default stm32f401re
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config SRAM_SIZE
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default 96
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config FLASH_SIZE
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default 512
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config NUM_IRQS
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int
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default 85
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endif # SOC_STM32F401RE
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25
arch/arm/soc/st_stm32/stm32f4/Kconfig.series
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25
arch/arm/soc/st_stm32/stm32f4/Kconfig.series
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@ -0,0 +1,25 @@
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# Kconfig - ST Microelectronics STM32F1 MCU series
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#
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# Copyright (c) 2016 Linaro Limited
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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config SOC_SERIES_STM32F4X
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bool "STM32F4x Series MCU"
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select CPU_CORTEX_M
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select CPU_CORTEX_M4
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select SOC_FAMILY_STM32
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select SYS_POWER_LOW_POWER_STATE_SUPPORTED
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help
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Enable support for STM32F4 MCU series
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25
arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
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25
arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
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@ -0,0 +1,25 @@
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# Kconfig.soc - ST Microelectronics STM32F4 MCU line
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#
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# Copyright (c) 2016 Linaro Limited.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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choice
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prompt "STM32F4x MCU Selection"
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depends on SOC_SERIES_STM32F4X
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config SOC_STM32F401RE
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bool "STM32F401RE"
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endchoice
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4
arch/arm/soc/st_stm32/stm32f4/Makefile
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4
arch/arm/soc/st_stm32/stm32f4/Makefile
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@ -0,0 +1,4 @@
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obj-y += soc.o
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zephyr: $(KERNEL_HEX_NAME)
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all: $(KERNEL_HEX_NAME)
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19
arch/arm/soc/st_stm32/stm32f4/linker.ld
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19
arch/arm/soc/st_stm32/stm32f4/linker.ld
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@ -0,0 +1,19 @@
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/* linker.ld - Linker command/script file */
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/*
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* Copyright (c) 2014-2016 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <arch/arm/cortex_m/scripts/linker.ld>
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67
arch/arm/soc/st_stm32/stm32f4/soc.c
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67
arch/arm/soc/st_stm32/stm32f4/soc.c
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@ -0,0 +1,67 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 Linaro Limited.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief System/hardware module for STM32F4 processor
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*/
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#include <nanokernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <arch/cpu.h>
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int st_stm32f4_init(struct device *arg)
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{
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uint32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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/* Setup the vector table offset register (VTOR),
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* which is located at the beginning of flash area.
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*/
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_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
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/* Clear all faults */
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_ScbMemFaultAllFaultsReset();
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_ScbBusFaultAllFaultsReset();
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_ScbUsageFaultAllFaultsReset();
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_ScbHardFaultAllFaultsReset();
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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return 0;
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}
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SYS_INIT(st_stm32f4_init, PRIMARY, 0);
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81
arch/arm/soc/st_stm32/stm32f4/soc.h
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81
arch/arm/soc/st_stm32/stm32f4/soc.h
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@ -0,0 +1,81 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 Linaro Limited.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file SoC configuration macros for the ST STM32F4 family processors.
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*
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* Based on reference manual:
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* RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 2.3: Memory Map
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*/
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#ifndef _STM32F4_SOC_H_
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#define _STM32F4_SOC_H_
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/* peripherals start address */
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#define PERIPH_BASE 0x40000000
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/* use naming consistent with STMF4 Peripherals Library */
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#define APB1PERIPH_BASE PERIPH_BASE
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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#define AHB1PERIPH_BASE (PERIPH_BASE + 0x20000)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
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/* UART */
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#define USART1_ADDR (APB2PERIPH_BASE + 0x1000)
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#define USART2_ADDR (APB1PERIPH_BASE + 0x4400)
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#define USART6_ADDR (APB2PERIPH_BASE + 0x1400)
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/* Reset and Clock Control */
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#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
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#define GPIO_REG_SIZE 0x400
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#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
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#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
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#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
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#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
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#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
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#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
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#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
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#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
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#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
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/* base address for where GPIO registers start */
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#define GPIO_PORTS_BASE (GPIOA_BASE)
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/* EXTI */
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#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
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/* IWDG */
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#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
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/* FLASH */
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#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
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#ifndef _ASMLANGUAGE
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#include <device.h>
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#include <misc/util.h>
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#include <drivers/rand32.h>
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#include "soc_irq.h"
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32F4_SOC_H_ */
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135
arch/arm/soc/st_stm32/stm32f4/soc_irq.h
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135
arch/arm/soc/st_stm32/stm32f4/soc_irq.h
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@ -0,0 +1,135 @@
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/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file Interrupt numbers for STM32F4 family processors.
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*
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* Based on reference manual:
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* RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
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* advanced ARM-based 32-bit MCUs
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*
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* Chapter 10.1.3: Interrupt and exception vectors
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*/
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#ifndef _STM32F4_SOC_IRQ_H_
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#define _STM32F4_SOC_IRQ_H_
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#define STM32F4_IRQ_WWDG 0
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#define STM32F4_IRQ_PVD 1
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#define STM32F4_IRQ_EXTI16 STM32F4_IRQ_PVD
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#define STM32F4_IRQ_TAMP_STAMP 2
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#define STM32F4_IRQ_EXTI21 STM32F4_IRQ_TAMP_STAMP
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#define STM32F4_IRQ_RTC_WKUP 3
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#define STM32F4_IRQ_EXTI22 STM32F4_IRQ_RTC_WKUP
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#define STM32F4_IRQ_FLASH 4
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#define STM32F4_IRQ_RCC 5
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#define STM32F4_IRQ_EXTI0 6
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#define STM32F4_IRQ_EXTI1 7
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#define STM32F4_IRQ_EXTI2 8
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#define STM32F4_IRQ_EXTI3 9
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#define STM32F4_IRQ_EXTI4 10
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#define STM32F4_IRQ_DMA1_STREAM0 11
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#define STM32F4_IRQ_DMA1_STREAM1 12
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#define STM32F4_IRQ_DMA1_STREAM2 13
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#define STM32F4_IRQ_DMA1_STREAM3 14
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#define STM32F4_IRQ_DMA1_STREAM4 15
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#define STM32F4_IRQ_DMA1_STREAM5 16
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#define STM32F4_IRQ_DMA1_STREAM6 17
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#define STM32F4_IRQ_ADC 18
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#define STM32F4_IRQ_CAN1_TX 19
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#define STM32F4_IRQ_CAN1_RX0 20
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#define STM32F4_IRQ_CAN1_RX1 21
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#define STM32F4_IRQ_CAN1_SCE 22
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#define STM32F4_IRQ_EXTI9_5 23
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#define STM32F4_IRQ_TIM1_BRK_TIM9 24
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#define STM32F4_IRQ_TIM1_UP_TIM10 25
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#define STM32F4_IRQ_TIM1_TRG_COM_TIM11 26
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#define STM32F4_IRQ_TIM1_CC 27
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#define STM32F4_IRQ_TIM2 28
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#define STM32F4_IRQ_TIM3 29
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#define STM32F4_IRQ_TIM4 30
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#define STM32F4_IRQ_I2C1_EV 31
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#define STM32F4_IRQ_I2C1_ER 32
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#define STM32F4_IRQ_I2C2_EV 33
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#define STM32F4_IRQ_I2C2_ER 34
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#define STM32F4_IRQ_SPI1 35
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#define STM32F4_IRQ_SPI2 36
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#define STM32F4_IRQ_USART1 37
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#define STM32F4_IRQ_USART2 38
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#define STM32F4_IRQ_USART3 39
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#define STM32F4_IRQ_EXTI15_10 40
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#define STM32F4_IRQ_RTC_ALARM 41
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#define STM32F4_IRQ_EXTI17 STM32F4_IRQ_RTC_ALARM
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#define STM32F4_IRQ_OTG_FS_WKUP 42
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#define STM32F4_IRQ_EXTI18 STM32F4_IRQ_OTG_FS_WKUP
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#define STM32F4_IRQ_TIM8_BRK_TIM12 43
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#define STM32F4_IRQ_TIM8_UP_TIM12 44
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#define STM32F4_IRQ_TIM8_TRG_COM_TIM14 45
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#define STM32F4_IRQ_TIM8_CC 46
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#define STM32F4_IRQ_DMA1_STREAM7 47
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#define STM32F4_IRQ_FSMC 48
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#define STM32F4_IRQ_SDIO 49
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#define STM32F4_IRQ_TIM5 50
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#define STM32F4_IRQ_SPI3 51
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#define STM32F4_IRQ_UART4 52
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#define STM32F4_IRQ_UART5 53
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#define STM32F4_IRQ_TIM6_DAC 54
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#define STM32F4_IRQ_TIM7 55
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#define STM32F4_IRQ_DMA2_STREAM0 56
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#define STM32F4_IRQ_DMA2_STREAM1 57
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#define STM32F4_IRQ_DMA2_STREAM2 58
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#define STM32F4_IRQ_DMA2_STREAM3 59
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#define STM32F4_IRQ_DMA2_STREAM4 60
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#define STM32F4_IRQ_ETH 61
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#define STM32F4_IRQ_ETH_WKUP 62
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#define STM32F4_IRQ_CAN2_TX 63
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#define STM32F4_IRQ_CAN2_RX0 64
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#define STM32F4_IRQ_CAN2_RX1 65
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#define STM32F4_IRQ_CAN2_SCE 66
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#define STM32F4_IRQ_OTG_FS 67
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#define STM32F4_IRQ_DMA2_STREAM5 68
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#define STM32F4_IRQ_DMA2_STREAM6 69
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#define STM32F4_IRQ_DMA2_STREAM7 70
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#define STM32F4_IRQ_USART6 71
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#define STM32F4_IRQ_I2C3_EV 72
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#define STM32F4_IRQ_I2C3_ER 73
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#define STM32F4_IRQ_OTG_HS_EP1_OUT 74
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||||
#define STM32F4_IRQ_OTG_HS_EP1_IN 75
|
||||
#define STM32F4_IRQ_OTG_HS_WKUP 76
|
||||
#define STM32F4_IRQ_OTG_HS 77
|
||||
#define STM32F4_IRQ_DCMI 78
|
||||
#define STM32F4_IRQ_CRYP 79
|
||||
#define STM32F4_IRQ_HASH_RNG 80
|
||||
#define STM32F4_IRQ_FPU 81
|
||||
#define STM32F4_IRQ_UART7 82
|
||||
#define STM32F4_IRQ_UART8 83
|
||||
#define STM32F4_IRQ_SPI4 84
|
||||
#define STM32F4_IRQ_SPI5 85
|
||||
#define STM32F4_IRQ_SPI6 86
|
||||
#define STM32F4_IRQ_SAI1 87
|
||||
#define STM32F4_IRQ_LTDC 88
|
||||
#define STM32F4_IRQ_LTDC_ER 89
|
||||
#define STM32F4_IRQ_DMA2D 90
|
||||
#define STM32F4_IRQ_QUADSPI 91
|
||||
#define STM32F4_IRQ_DSI 92
|
||||
#define STM32F4_IRQ_CEC 93
|
||||
#define STM32F4_IRQ_SPDIF_RX 94
|
||||
#define STM32F4_IRQ_FMPI2C1_EV 95
|
||||
#define STM32F4_IRQ_FMPI2C1_ER 96
|
||||
#define STM32F4_IRQ_LPTIM1 97
|
||||
|
||||
#endif /* _STM32F4_SOC_IRQ_H_ */
|
||||
|
|
@ -72,4 +72,44 @@ config EXTI_STM32_EXTI15_10_IRQ_PRI
|
|||
help
|
||||
IRQ priority of EXTI15:10 interrupt
|
||||
|
||||
config EXTI_STM32_EXTI16_IRQ_PRI
|
||||
int "EXTI16 IRQ priority"
|
||||
depends on EXTI_STM32
|
||||
depends on SOC_SERIES_STM32F4X
|
||||
default 0
|
||||
help
|
||||
IRQ priority of EXTI16 interrupt
|
||||
|
||||
config EXTI_STM32_EXTI17_IRQ_PRI
|
||||
int "EXTI17 IRQ priority"
|
||||
depends on EXTI_STM32
|
||||
depends on SOC_SERIES_STM32F4X
|
||||
default 0
|
||||
help
|
||||
IRQ priority of EXTI17 interrupt
|
||||
|
||||
config EXTI_STM32_EXTI18_IRQ_PRI
|
||||
int "EXTI18 IRQ priority"
|
||||
depends on EXTI_STM32
|
||||
depends on SOC_SERIES_STM32F4X
|
||||
default 0
|
||||
help
|
||||
IRQ priority of EXTI18 interrupt
|
||||
|
||||
config EXTI_STM32_EXTI21_IRQ_PRI
|
||||
int "EXTI21 IRQ priority"
|
||||
depends on EXTI_STM32
|
||||
depends on SOC_SERIES_STM32F4X
|
||||
default 0
|
||||
help
|
||||
IRQ priority of EXTI21 interrupt
|
||||
|
||||
config EXTI_STM32_EXTI22_IRQ_PRI
|
||||
int "EXTI22 IRQ priority"
|
||||
depends on EXTI_STM32
|
||||
depends on SOC_SERIES_STM32F4X
|
||||
default 0
|
||||
help
|
||||
IRQ priority of EXTI22 interrupt
|
||||
|
||||
endif # SOC_FAMILY_STM32
|
||||
|
|
|
|||
|
|
@ -17,9 +17,12 @@
|
|||
/**
|
||||
* @brief Driver for External interrupt/event controller in STM32 MCUs
|
||||
*
|
||||
* Based on reference manual:
|
||||
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
|
||||
* advanced ARM ® -based 32-bit MCUs
|
||||
* Based on reference manuals:
|
||||
* RM0008 Reference Manual: STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx
|
||||
* and STM32F107xx advanced ARM-based 32-bit MCUs
|
||||
* and
|
||||
* RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
|
||||
* advanced ARM-based 32-bit MCUs
|
||||
*
|
||||
* Chapter 10.2: External interrupt/event controller (EXTI)
|
||||
*
|
||||
|
|
@ -54,6 +57,8 @@ struct __exti_cb {
|
|||
|
||||
#ifdef CONFIG_SOC_SERIES_STM32F1X
|
||||
#define EXTI_LINES 19
|
||||
#elif CONFIG_SOC_SERIES_STM32F4X
|
||||
#define EXTI_LINES 23
|
||||
#endif
|
||||
|
||||
/* driver data */
|
||||
|
|
@ -70,7 +75,7 @@ static inline struct stm32_exti *get_exti_base_addr(int line)
|
|||
void stm32_exti_enable(int line)
|
||||
{
|
||||
volatile struct stm32_exti *exti = get_exti_base_addr(line);
|
||||
int irqnum;
|
||||
int irqnum = 0;
|
||||
|
||||
exti->imr |= 1 << line;
|
||||
|
||||
|
|
@ -83,6 +88,35 @@ void stm32_exti_enable(int line)
|
|||
/* pins 0..4 are mapped to EXTI0.. EXTI4 */
|
||||
irqnum = STM32F1_IRQ_EXTI0 + line;
|
||||
}
|
||||
#elif CONFIG_SOC_SERIES_STM32F4X
|
||||
if (line >= 5 && line <= 9) {
|
||||
irqnum = STM32F4_IRQ_EXTI9_5;
|
||||
} else if (line >= 10 && line <= 15) {
|
||||
irqnum = STM32F4_IRQ_EXTI15_10;
|
||||
} else if (line >= 0 && line <= 4) {
|
||||
/* pins 0..4 are mapped to EXTI0.. EXTI4 */
|
||||
irqnum = STM32F4_IRQ_EXTI0 + line;
|
||||
} else {
|
||||
switch (line) {
|
||||
case 16:
|
||||
irqnum = STM32F4_IRQ_EXTI16;
|
||||
break;
|
||||
case 17:
|
||||
irqnum = STM32F4_IRQ_EXTI17;
|
||||
break;
|
||||
case 18:
|
||||
irqnum = STM32F4_IRQ_EXTI18;
|
||||
break;
|
||||
case 21:
|
||||
irqnum = STM32F4_IRQ_EXTI21;
|
||||
break;
|
||||
case 22:
|
||||
irqnum = STM32F4_IRQ_EXTI22;
|
||||
break;
|
||||
}
|
||||
}
|
||||
#else
|
||||
#error "Unknown STM32 SoC"
|
||||
#endif
|
||||
|
||||
irq_enable(irqnum);
|
||||
|
|
@ -199,6 +233,33 @@ static inline void __stm32_exti_isr_15_10(void *arg)
|
|||
__stm32_exti_isr(10, 16, arg);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_SERIES_STM32F4X
|
||||
static inline void __stm32_exti_isr_16(void *arg)
|
||||
{
|
||||
__stm32_exti_isr(16, 17, arg);
|
||||
}
|
||||
|
||||
static inline void __stm32_exti_isr_17(void *arg)
|
||||
{
|
||||
__stm32_exti_isr(17, 18, arg);
|
||||
}
|
||||
|
||||
static inline void __stm32_exti_isr_18(void *arg)
|
||||
{
|
||||
__stm32_exti_isr(18, 19, arg);
|
||||
}
|
||||
|
||||
static inline void __stm32_exti_isr_21(void *arg)
|
||||
{
|
||||
__stm32_exti_isr(21, 22, arg);
|
||||
}
|
||||
|
||||
static inline void __stm32_exti_isr_22(void *arg)
|
||||
{
|
||||
__stm32_exti_isr(22, 23, arg);
|
||||
}
|
||||
#endif /* CONFIG_SOC_SERIES_STM32F4X */
|
||||
|
||||
static void __stm32_exti_connect_irqs(struct device *dev);
|
||||
|
||||
/**
|
||||
|
|
@ -274,7 +335,56 @@ static void __stm32_exti_connect_irqs(struct device *dev)
|
|||
CONFIG_EXTI_STM32_EXTI15_10_IRQ_PRI,
|
||||
__stm32_exti_isr_15_10, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
#endif
|
||||
#elif CONFIG_SOC_SERIES_STM32F4X
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI0,
|
||||
CONFIG_EXTI_STM32_EXTI0_IRQ_PRI,
|
||||
__stm32_exti_isr_0, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI1,
|
||||
CONFIG_EXTI_STM32_EXTI1_IRQ_PRI,
|
||||
__stm32_exti_isr_1, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI2,
|
||||
CONFIG_EXTI_STM32_EXTI2_IRQ_PRI,
|
||||
__stm32_exti_isr_2, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI3,
|
||||
CONFIG_EXTI_STM32_EXTI3_IRQ_PRI,
|
||||
__stm32_exti_isr_3, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI4,
|
||||
CONFIG_EXTI_STM32_EXTI4_IRQ_PRI,
|
||||
__stm32_exti_isr_4, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI9_5,
|
||||
CONFIG_EXTI_STM32_EXTI9_5_IRQ_PRI,
|
||||
__stm32_exti_isr_9_5, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI15_10,
|
||||
CONFIG_EXTI_STM32_EXTI15_10_IRQ_PRI,
|
||||
__stm32_exti_isr_15_10, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI16,
|
||||
CONFIG_EXTI_STM32_EXTI16_IRQ_PRI,
|
||||
__stm32_exti_isr_16, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI17,
|
||||
CONFIG_EXTI_STM32_EXTI17_IRQ_PRI,
|
||||
__stm32_exti_isr_17, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI18,
|
||||
CONFIG_EXTI_STM32_EXTI18_IRQ_PRI,
|
||||
__stm32_exti_isr_18, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI21,
|
||||
CONFIG_EXTI_STM32_EXTI21_IRQ_PRI,
|
||||
__stm32_exti_isr_21, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
IRQ_CONNECT(STM32F4_IRQ_EXTI22,
|
||||
CONFIG_EXTI_STM32_EXTI22_IRQ_PRI,
|
||||
__stm32_exti_isr_22, DEVICE_GET(exti_stm32),
|
||||
0);
|
||||
#endif /* CONFIG_SOC_SERIES_STM32FXX */
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -17,11 +17,14 @@
|
|||
/**
|
||||
* @brief Driver for External interrupt/event controller in STM32 MCUs
|
||||
*
|
||||
* Based on reference manual:
|
||||
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
|
||||
* advanced ARM ® -based 32-bit MCUs
|
||||
* Based on reference manuals:
|
||||
* RM0008 Reference Manual: STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx
|
||||
* and STM32F107xx advanced ARM-based 32-bit MCUs
|
||||
* and
|
||||
* RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
|
||||
* advanced ARM-based 32-bit MCUs
|
||||
*
|
||||
* Chapter 8.2: External interrupt/event controller (EXTI)
|
||||
* Chapter 10.2: External interrupt/event controller (EXTI)
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue