drivers: display: smartbond: Add support for the display driver class.
Exhibit Renesas LCD controller's driver implementation. The driver is intended to employ the controller in the continuous mode so it can drive display panels in the parallel RGB mode. Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
This commit is contained in:
Ioannis Karachalios
Fabio Baltieri
parent
ca52603b09
commit
96677e402e
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@ -25,6 +25,7 @@ zephyr_library_sources_ifdef(CONFIG_RM67162 display_rm67162.c)
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zephyr_library_sources_ifdef(CONFIG_HX8394 display_hx8394.c)
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zephyr_library_sources_ifdef(CONFIG_GC9X01X display_gc9x01x.c)
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zephyr_library_sources_ifdef(CONFIG_LED_STRIP_MATRIX display_led_strip_matrix.c)
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zephyr_library_sources_ifdef(CONFIG_DISPLAY_RENESAS_LCDC display_renesas_lcdc.c)
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zephyr_library_sources_ifdef(CONFIG_MICROBIT_DISPLAY
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mb_display.c
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@ -42,5 +42,6 @@ source "drivers/display/Kconfig.otm8009a"
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source "drivers/display/Kconfig.hx8394"
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source "drivers/display/Kconfig.gc9x01x"
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source "drivers/display/Kconfig.led_strip_matrix"
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source "drivers/display/Kconfig.renesas_lcdc"
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endif # DISPLAY
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19
drivers/display/Kconfig.renesas_lcdc
Normal file
19
drivers/display/Kconfig.renesas_lcdc
Normal file
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@ -0,0 +1,19 @@
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# Smartbond display controller configuration options
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# Copyright (c) 2023 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config DISPLAY_RENESAS_LCDC
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bool "Smartbond display controller driver"
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depends on DT_HAS_RENESAS_SMARTBOND_DISPLAY_ENABLED
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select DMA
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default y
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help
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Enable Smartbond display controller.
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config DISPLAY_RENESAS_LCDC_BUFFER_PSRAM
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bool "Allocate the display buffer into PSRAM"
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depends on DISPLAY_RENESAS_LCDC
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select MEMC
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help
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Allocate the display buffer into PSRAM
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582
drivers/display/display_renesas_lcdc.c
Normal file
582
drivers/display/display_renesas_lcdc.c
Normal file
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@ -0,0 +1,582 @@
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/*
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* Copyright (c) 2023 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_smartbond_display
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/irq.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/smartbond_clock_control.h>
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#include <zephyr/drivers/display.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/dma.h>
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#include <da1469x_lcdc.h>
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#include <DA1469xAB.h>
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#include <da1469x_pd.h>
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#include <zephyr/linker/devicetree_regions.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(smartbond_display, CONFIG_DISPLAY_LOG_LEVEL);
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#define SMARTBOND_IRQN DT_INST_IRQN(0)
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#define SMARTBOND_IRQ_PRIO DT_INST_IRQ(0, priority)
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#define LCDC_SMARTBOND_CLK_DIV(_freq) \
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((32000000U % (_freq)) ? (96000000U / (_freq)) : (32000000U / (_freq)))
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#define LCDC_SMARTBOND_IS_PLL_REQUIRED \
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!!(32000000U % DT_PROP(DT_INST_CHILD(0, display_timings), clock_frequency))
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#define DISPLAY_SMARTBOND_IS_DMA_PREFETCH_ENABLED \
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DT_INST_ENUM_IDX_OR(0, dma_prefetch, 0)
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#define LCDC_LAYER0_OFFSETX_REG_SET_FIELD(_field, _var, _val)\
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((_var)) = \
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((_var) & ~(LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk)) | \
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(((_val) << LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Pos) & \
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LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk)
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#define DISPLAY_SMARTBOND_PIXEL_SIZE(inst) \
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(DISPLAY_BITS_PER_PIXEL(DT_INST_PROP(inst, pixel_format)) / 8)
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#if CONFIG_DISPLAY_RENESAS_LCDC_BUFFER_PSRAM
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#define DISPLAY_BUFFER_LINKER_SECTION \
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Z_GENERIC_SECTION(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(psram)))
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#else
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#define DISPLAY_BUFFER_LINKER_SECTION
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#endif
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struct display_smartbond_data {
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/* Provide mutual exclusion when a display operation is requested. */
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struct k_sem device_sem;
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/* Frame update synchronization token */
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struct k_sem sync_sem;
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/* Flag indicating whether or not an underflow took place */
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volatile bool underflow_flag;
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/* Layer settings */
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lcdc_smartbond_layer_cfg layer;
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/* Frame buffer */
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uint8_t *buffer;
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/* DMA device */
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const struct device *dma;
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/* DMA configuration structures */
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struct dma_config dma_cfg;
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struct dma_block_config dma_block_cfg;
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/* DMA memory transfer synchronization token */
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struct k_sem dma_sync_sem;
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/* Granted DMA channel used for memory transfers */
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int dma_channel;
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};
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struct display_smartbond_config {
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/* Reference to device instance's pinctrl configurations */
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const struct pinctrl_dev_config *pcfg;
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/* Display ON/OFF GPIO */
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const struct gpio_dt_spec disp;
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/* Host controller's timing settings */
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lcdc_smartbond_timing_cfg timing_cfg;
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/* Parallel interface settings */
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lcdc_smartbond_mode_cfg mode;
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/* Background default color configuration */
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lcdc_smartbond_bgcolor_cfg bgcolor_cfg;
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/* Display dimensions */
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const uint16_t x_res;
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const uint16_t y_res;
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/* Pixel size in bytes */
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uint8_t pixel_size;
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enum display_pixel_format pixel_format;
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};
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/* Display pixel to layer color format translation */
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static uint8_t lcdc_smartbond_pixel_to_lcm(enum display_pixel_format pixel_format)
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{
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switch (pixel_format) {
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case PIXEL_FORMAT_RGB_565:
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return (uint8_t)LCDC_SMARTBOND_L0_RGB565;
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case PIXEL_FORMAT_ARGB_8888:
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return (uint8_t)LCDC_SMARTBOND_L0_ARGB8888;
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default:
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LOG_ERR("Unsupported pixel format");
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return 0;
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};
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}
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static int display_smartbond_configure(const struct device *dev)
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{
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uint8_t clk_div =
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LCDC_SMARTBOND_CLK_DIV(DT_PROP(DT_INST_CHILD(0, display_timings), clock_frequency));
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const struct display_smartbond_config *config = dev->config;
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struct display_smartbond_data *data = dev->data;
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int ret = 0;
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/* First enable the controller so registers can be written. */
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da1469x_lcdc_set_status(true, LCDC_SMARTBOND_IS_PLL_REQUIRED, clk_div);
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if (!da1469x_lcdc_check_id()) {
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LOG_ERR("Invalid LCDC ID");
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da1469x_lcdc_set_status(false, false, 0);
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return -EINVAL;
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}
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da1469x_lcdc_parallel_interface_configure((lcdc_smartbond_mode_cfg *)&config->mode);
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da1469x_lcdc_bgcolor_configure((lcdc_smartbond_bgcolor_cfg *)&config->bgcolor_cfg);
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/*
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* Partial update is not supported and so timing and layer settings can be configured
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* once at initialization.
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*/
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ret = da1469x_lcdc_timings_configure(config->x_res, config->y_res,
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(lcdc_smartbond_timing_cfg *)&config->timing_cfg);
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if (ret < 0) {
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LOG_ERR("Unable to configure timing settings");
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da1469x_lcdc_set_status(false, false, 0);
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return ret;
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}
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/*
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* Stride should be updated at the end of a frame update (typically in ISR context).
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* It's OK to update stride here as continuous mode should not be enabled yet.
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*/
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data->layer.color_format =
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lcdc_smartbond_pixel_to_lcm(config->pixel_format);
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data->layer.stride =
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da1469x_lcdc_stride_calculation(data->layer.color_format, config->x_res);
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ret = da1469x_lcdc_layer_configure(&data->layer);
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if (ret < 0) {
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LOG_ERR("Unable to configure layer settings");
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da1469x_lcdc_set_status(false, false, 0);
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}
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LCDC_LAYER0_OFFSETX_REG_SET_FIELD(LCDC_L0_DMA_PREFETCH,
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LCDC->LCDC_LAYER0_OFFSETX_REG, DISPLAY_SMARTBOND_IS_DMA_PREFETCH_ENABLED);
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LCDC->LCDC_MODE_REG |= LCDC_LCDC_MODE_REG_LCDC_MODE_EN_Msk;
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return ret;
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}
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static void smartbond_display_isr(const void *arg)
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{
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struct display_smartbond_data *data = ((const struct device *)arg)->data;
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data->underflow_flag = LCDC_STATUS_REG_GET_FIELD(LCDC_STICKY_UNDERFLOW);
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/*
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* Underflow sticky bit will remain high until cleared by writing
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* any value to LCDC_INTERRUPT_REG.
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*/
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LCDC->LCDC_INTERRUPT_REG &= ~LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk;
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/* Notify that current frame update is completed */
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k_sem_give(&data->sync_sem);
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}
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static int display_smartbond_resume(const struct device *dev)
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{
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const struct display_smartbond_config *config = dev->config;
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int ret;
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/* Select default state */
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("Could not apply LCDC pins' default state (%d)", ret);
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return -EIO;
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}
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#if LCDC_SMARTBOND_IS_PLL_REQUIRED
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const struct device *clock_dev = DEVICE_DT_GET(DT_NODELABEL(osc));
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if (!device_is_ready(clock_dev)) {
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LOG_WRN("Clock device is not ready");
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return -ENODEV;
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}
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ret = z_smartbond_select_sys_clk(SMARTBOND_CLK_PLL96M);
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if (ret < 0) {
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LOG_WRN("Could not switch to PLL");
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return -EIO;
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}
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#endif
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return display_smartbond_configure(dev);
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}
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static void display_smartbond_dma_cb(const struct device *dma, void *arg,
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uint32_t id, int status)
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{
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struct display_smartbond_data *data = arg;
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if (status < 0) {
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LOG_WRN("DMA transfer did not complete");
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}
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k_sem_give(&data->dma_sync_sem);
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}
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static int display_smartbond_dma_config(const struct device *dev)
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{
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struct display_smartbond_data *data = dev->data;
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data->dma = DEVICE_DT_GET(DT_NODELABEL(dma));
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if (!device_is_ready(data->dma)) {
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LOG_ERR("DMA device is not ready");
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return -ENODEV;
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}
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data->dma_cfg.channel_direction = MEMORY_TO_MEMORY;
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data->dma_cfg.user_data = data;
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data->dma_cfg.dma_callback = display_smartbond_dma_cb;
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data->dma_cfg.block_count = 1;
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data->dma_cfg.head_block = &data->dma_block_cfg;
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/* Request an arbitrary DMA channel */
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data->dma_channel = dma_request_channel(data->dma, NULL);
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if (data->dma_channel < 0) {
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LOG_ERR("Could not acquire a DMA channel");
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return -EIO;
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}
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return 0;
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}
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static int display_smartbond_init(const struct device *dev)
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{
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const struct display_smartbond_config *config = dev->config;
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struct display_smartbond_data *data = dev->data;
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int ret;
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/* Device should be ready to be acquired */
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k_sem_init(&data->device_sem, 1, 1);
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/* Event should be signaled by LCDC ISR */
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k_sem_init(&data->sync_sem, 0, 1);
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/* Event should be signaled by DMA ISR */
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k_sem_init(&data->dma_sync_sem, 0, 1);
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/* As per docs, display port should be enabled by default. */
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if (gpio_is_ready_dt(&config->disp)) {
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ret = gpio_pin_configure_dt(&config->disp, GPIO_OUTPUT_ACTIVE);
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if (ret < 0) {
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LOG_ERR("Could not activate display port");
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return -EIO;
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}
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}
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ret = display_smartbond_resume(dev);
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if (ret < 0) {
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return ret;
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}
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ret = display_smartbond_dma_config(dev);
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if (ret < 0) {
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return ret;
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}
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IRQ_CONNECT(SMARTBOND_IRQN, SMARTBOND_IRQ_PRIO, smartbond_display_isr,
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DEVICE_DT_INST_GET(0), 0);
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#if CONFIG_PM
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/*
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* When in continues mode, the display device should always be refreshed
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* and so the controller is not allowed to be turned off. The latter, is
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* powered by PD_SYS which is turned off when the SoC enters the extended
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* sleep state. By acquiring PD_SYS, the deep sleep state is prevented
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* and the system enters the low-power state (i.e. ARM WFI) when possible.
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*
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* XXX CONFIG_PM_DEVICE_RUNTIME is no supported yet!
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*/
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da1469x_pd_acquire_noconf(MCU_PD_DOMAIN_SYS);
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#endif
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return 0;
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}
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static int display_smartbond_blanking_on(const struct device *dev)
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{
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const struct display_smartbond_config *config = dev->config;
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struct display_smartbond_data *data = dev->data;
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int ret = 0;
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k_sem_take(&data->device_sem, K_FOREVER);
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/*
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* This bit will force LCD controller's output to blank that is,
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* the controller will keep operating without outputting any
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* pixel data.
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*/
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LCDC->LCDC_MODE_REG |= LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Msk;
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/* If enabled, disable display port. */
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if (gpio_is_ready_dt(&config->disp)) {
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ret = gpio_pin_configure_dt(&config->disp, GPIO_OUTPUT_INACTIVE);
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if (ret < 0) {
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LOG_WRN("Display port could not be de-activated");
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}
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}
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k_sem_give(&data->device_sem);
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return ret;
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}
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static int display_smartbond_blanking_off(const struct device *dev)
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{
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const struct display_smartbond_config *config = dev->config;
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struct display_smartbond_data *data = dev->data;
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int ret = 0;
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k_sem_take(&data->device_sem, K_FOREVER);
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/* If used, enable display port */
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if (gpio_is_ready_dt(&config->disp)) {
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ret = gpio_pin_configure_dt(&config->disp, GPIO_OUTPUT_ACTIVE);
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if (ret < 0) {
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LOG_WRN("Display port could not be activated");
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}
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}
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/*
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* This bit will force LCD controller's output to blank that is,
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* the controller will keep operating without outputting any
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* pixel data.
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*/
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LCDC->LCDC_MODE_REG &= ~LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Msk;
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k_sem_give(&data->device_sem);
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return ret;
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}
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static void *display_smartbond_get_framebuffer(const struct device *dev)
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{
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struct display_smartbond_data *data = dev->data;
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return ((void *)data->buffer);
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}
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static void display_smartbond_get_capabilities(const struct device *dev,
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struct display_capabilities *capabilities)
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{
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memset(capabilities, 0, sizeof(*capabilities));
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/*
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* Multiple color formats should be supported by LCDC. Currently, RGB56 and ARGB888
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* exposed by display API are supported. In the future we should consider supporting
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* more color formats which should require changes in LVGL porting.
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* Here, only one color format should be supported as the frame buffer is accessed
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* directly by LCDC and is allocated statically during device initialization. The color
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* format is defined based on the pixel-format property dictated by lcd-controller
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* bindings.
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*/
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capabilities->supported_pixel_formats = DT_INST_PROP(0, pixel_format);
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capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
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capabilities->current_pixel_format = DT_INST_PROP(0, pixel_format);
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capabilities->x_resolution = DT_INST_PROP(0, width);
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capabilities->y_resolution = DT_INST_PROP(0, height);
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}
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static int display_smartbond_read(const struct device *dev,
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const uint16_t x, const uint16_t y,
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const struct display_buffer_descriptor *desc,
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void *buf)
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{
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struct display_smartbond_data *data = dev->data;
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const struct display_smartbond_config *config = dev->config;
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uint8_t *dst = buf;
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const uint8_t *src = data->buffer;
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k_sem_take(&data->device_sem, K_FOREVER);
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/* pointer to upper left pixel of the rectangle */
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src += (x * config->pixel_size);
|
||||
src += (y * data->layer.stride);
|
||||
|
||||
data->dma_block_cfg.block_size = desc->width * config->pixel_size;
|
||||
/*
|
||||
* Source and destination base address is word aligned.
|
||||
* Data size should be selected based on color depth as
|
||||
* cursor is shifted multiple of pixel color depth.
|
||||
*/
|
||||
data->dma_cfg.source_data_size = data->dma_cfg.dest_data_size =
|
||||
!(config->pixel_size & 3) ? 4 :
|
||||
!(config->pixel_size & 1) ? 2 : 1;
|
||||
|
||||
data->dma_cfg.dest_burst_length = data->dma_cfg.source_burst_length =
|
||||
!((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 7) ? 8 :
|
||||
!((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 3) ? 4 : 1;
|
||||
|
||||
for (int row = 0; row < desc->height; row++) {
|
||||
|
||||
data->dma_block_cfg.dest_address = (uint32_t)dst;
|
||||
data->dma_block_cfg.source_address = (uint32_t)src;
|
||||
|
||||
if (dma_config(data->dma, data->dma_channel, &data->dma_cfg)) {
|
||||
LOG_ERR("Could not configure DMA");
|
||||
k_sem_give(&data->device_sem);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (dma_start(data->dma, data->dma_channel)) {
|
||||
LOG_ERR("Could not start DMA");
|
||||
k_sem_give(&data->device_sem);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
k_sem_take(&data->dma_sync_sem, K_FOREVER);
|
||||
|
||||
src += data->layer.stride;
|
||||
dst += (desc->pitch * config->pixel_size);
|
||||
}
|
||||
|
||||
if (dma_stop(data->dma, data->dma_channel)) {
|
||||
LOG_WRN("Could not stop DMA");
|
||||
}
|
||||
|
||||
k_sem_give(&data->device_sem);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int display_smartbond_write(const struct device *dev,
|
||||
const uint16_t x, const uint16_t y,
|
||||
const struct display_buffer_descriptor *desc,
|
||||
const void *buf)
|
||||
{
|
||||
struct display_smartbond_data *data = dev->data;
|
||||
const struct display_smartbond_config *config = dev->config;
|
||||
uint8_t *dst = data->buffer;
|
||||
const uint8_t *src = buf;
|
||||
|
||||
k_sem_take(&data->device_sem, K_FOREVER);
|
||||
|
||||
/* pointer to upper left pixel of the rectangle */
|
||||
dst += (x * config->pixel_size);
|
||||
dst += (y * data->layer.stride);
|
||||
|
||||
/*
|
||||
* Wait for the current frame to finish. Do not disable continuous mode as this
|
||||
* will have visual artifacts.
|
||||
*/
|
||||
LCDC->LCDC_INTERRUPT_REG |= LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk;
|
||||
k_sem_take(&data->sync_sem, K_FOREVER);
|
||||
|
||||
data->dma_block_cfg.block_size = desc->width * config->pixel_size;
|
||||
/*
|
||||
* Source and destination base address is word aligned.
|
||||
* Data size should be selected based on color depth as
|
||||
* cursor is shifted multiple of pixel color depth.
|
||||
*/
|
||||
data->dma_cfg.source_data_size = data->dma_cfg.dest_data_size =
|
||||
!(config->pixel_size & 3) ? 4 :
|
||||
!(config->pixel_size & 1) ? 2 : 1;
|
||||
|
||||
data->dma_cfg.dest_burst_length = data->dma_cfg.source_burst_length =
|
||||
!((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 7) ? 8 :
|
||||
!((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 3) ? 4 : 1;
|
||||
|
||||
for (int row = 0; row < desc->height; row++) {
|
||||
|
||||
data->dma_block_cfg.dest_address = (uint32_t)dst;
|
||||
data->dma_block_cfg.source_address = (uint32_t)src;
|
||||
|
||||
if (dma_config(data->dma, data->dma_channel, &data->dma_cfg)) {
|
||||
LOG_ERR("Could not configure DMA");
|
||||
k_sem_give(&data->device_sem);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (dma_start(data->dma, data->dma_channel)) {
|
||||
LOG_ERR("Could not start DMA");
|
||||
k_sem_give(&data->device_sem);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
k_sem_take(&data->dma_sync_sem, K_FOREVER);
|
||||
|
||||
dst += data->layer.stride;
|
||||
src += (desc->pitch * config->pixel_size);
|
||||
}
|
||||
|
||||
if (dma_stop(data->dma, data->dma_channel)) {
|
||||
LOG_WRN("Could not stop DMA");
|
||||
}
|
||||
|
||||
k_sem_give(&data->device_sem);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static struct display_driver_api display_smartbond_driver_api = {
|
||||
.write = display_smartbond_write,
|
||||
.read = display_smartbond_read,
|
||||
.get_framebuffer = display_smartbond_get_framebuffer,
|
||||
.get_capabilities = display_smartbond_get_capabilities,
|
||||
.blanking_off = display_smartbond_blanking_off,
|
||||
.blanking_on = display_smartbond_blanking_on
|
||||
};
|
||||
|
||||
#define SMARTBOND_DISPLAY_INIT(inst) \
|
||||
PINCTRL_DT_INST_DEFINE(inst); \
|
||||
\
|
||||
__aligned(4) static uint8_t buffer_ ## inst[(((DT_INST_PROP(inst, width) * \
|
||||
DISPLAY_SMARTBOND_PIXEL_SIZE(inst)) + 0x3) & ~0x3) * \
|
||||
DT_INST_PROP(inst, height)] DISPLAY_BUFFER_LINKER_SECTION; \
|
||||
\
|
||||
static const struct display_smartbond_config display_smartbond_config_## inst = { \
|
||||
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
|
||||
.disp = GPIO_DT_SPEC_INST_GET_OR(inst, disp_gpios, {}), \
|
||||
.timing_cfg.vsync_len = \
|
||||
DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_len), \
|
||||
.timing_cfg.hsync_len = \
|
||||
DT_PROP(DT_INST_CHILD(inst, display_timings), hsync_len), \
|
||||
.timing_cfg.hfront_porch = \
|
||||
DT_PROP(DT_INST_CHILD(inst, display_timings), hfront_porch), \
|
||||
.timing_cfg.vfront_porch = \
|
||||
DT_PROP(DT_INST_CHILD(inst, display_timings), vfront_porch), \
|
||||
.timing_cfg.hback_porch = \
|
||||
DT_PROP(DT_INST_CHILD(inst, display_timings), hback_porch), \
|
||||
.timing_cfg.vback_porch = \
|
||||
DT_PROP(DT_INST_CHILD(inst, display_timings), vback_porch), \
|
||||
.bgcolor_cfg = {0xFF, 0xFF, 0xFF, 0}, \
|
||||
.x_res = DT_INST_PROP(inst, width), \
|
||||
.y_res = DT_INST_PROP(inst, height), \
|
||||
.pixel_size = DISPLAY_SMARTBOND_PIXEL_SIZE(inst), \
|
||||
.pixel_format = DT_INST_PROP(0, pixel_format), \
|
||||
.mode.vsync_pol = \
|
||||
DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_active) ? 0 : 1, \
|
||||
.mode.hsync_pol = \
|
||||
DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_active) ? 0 : 1, \
|
||||
.mode.de_pol = \
|
||||
DT_PROP(DT_INST_CHILD(inst, display_timings), de_active) ? 0 : 1, \
|
||||
.mode.pixelclk_pol = \
|
||||
DT_PROP(DT_INST_CHILD(inst, display_timings), pixelclk_active) ? 0 : 1, \
|
||||
}; \
|
||||
\
|
||||
static struct display_smartbond_data display_smartbond_data_## inst = { \
|
||||
.buffer = buffer_ ##inst, \
|
||||
.layer.start_x = 0, \
|
||||
.layer.start_y = 0, \
|
||||
.layer.size_x = DT_INST_PROP(inst, width), \
|
||||
.layer.size_y = DT_INST_PROP(inst, height), \
|
||||
.layer.frame_buf = (uint32_t)buffer_ ## inst, \
|
||||
}; \
|
||||
\
|
||||
\
|
||||
DEVICE_DT_INST_DEFINE(inst, display_smartbond_init, NULL, \
|
||||
&display_smartbond_data_## inst, \
|
||||
&display_smartbond_config_## inst, \
|
||||
POST_KERNEL, \
|
||||
CONFIG_DISPLAY_INIT_PRIORITY, \
|
||||
&display_smartbond_driver_api);
|
||||
|
||||
SMARTBOND_DISPLAY_INIT(0);
|
||||
37
dts/bindings/display/renesas,smartbond-display.yaml
Normal file
37
dts/bindings/display/renesas,smartbond-display.yaml
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
# Copyright (c) 2023 Renesas Electronics Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
include: [display-controller.yaml, lcd-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
description: Renesas Smartbond(tm) display controller
|
||||
|
||||
compatible: "renesas,smartbond-display"
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
disp-gpios:
|
||||
type: phandle-array
|
||||
description: |
|
||||
Display ON/OFF port control.
|
||||
|
||||
dma-prefetch:
|
||||
type: string
|
||||
enum:
|
||||
- "no-prefetch"
|
||||
- "prefetch-44-bytes"
|
||||
- "prefetch-84-bytes"
|
||||
- "prefetch-116-bytes"
|
||||
- "prefetch-108-bytes"
|
||||
description: |
|
||||
Host controller will wait for at least the specified number of bytes before triggering
|
||||
a single frame update. The prefetch mechanism should be enabled when frame buffer(s)
|
||||
is stored into external storage mediums, e.g. PSRAM, that introduce comparable delays.
|
||||
In such a case it might case that the controller runs into underrun conditions which
|
||||
results in correpting the whole frame update. It's user's responsibility to ensure that
|
||||
the selected value does not exceed frame's total size as otherwise the controller will
|
||||
not be able to trigger the frame update.
|
||||
Loading…
Reference in a new issue