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everywhere: fix typos

Browse source 
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
This commit is contained in:
Nazar Kazakov 2022-02-24 12:00:55 +00:00 committed by Anas Nashif
parent 210ed711a3
commit 9713f0d47c
331 changed files with 478 additions and 478 deletions
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2
.github/ISSUE_TEMPLATE/ext-source.md vendored
View file

@ -18,7 +18,7 @@ Brief description of what this software does
## Mode of integration
Describe whether you'd like to integrate this exernal component in the main tree
Describe whether you'd like to integrate this external component in the main tree
or as a module, and why. If the mode of integration is a module, suggest a
repository name for the module

2
arch/arc/core/mpu/arc_mpu_v4_internal.h
View file

@ -132,7 +132,7 @@ static inline bool _is_user_accessible_region(uint32_t r_index, int write)
return false;
}
#else /* CONFIG_ARC_NORMAL_FIRMWARE */
/* the following functions are prepared for SECURE_FRIMWARE */
/* the following functions are prepared for SECURE_FIRMWARE */
static inline void _region_init(uint32_t index, uint32_t region_addr, uint32_t size,
uint32_t region_attr)
{

4
arch/arc/core/secureshield/arc_sjli.c
View file

@ -34,7 +34,7 @@ static void _default_sjli_entry(void)
}
/*
* @brief initializaiton of sjli related functions
* @brief initialization of sjli related functions
*
*/
static void sjli_table_init(void)
@ -46,7 +46,7 @@ static void sjli_table_init(void)
}
/*
* @brief initializaiton of secureshield related functions.
* @brief initialization of secureshield related functions.
*/
static int arc_secureshield_init(const struct device *arg)
{

2
arch/arc/include/kernel_arch_data.h
View file

@ -159,7 +159,7 @@ struct _callee_saved_stack {
#endif
/*
* No need to save r31 (blink), it's either alread pushed as the pc or
* No need to save r31 (blink), it's either already pushed as the pc or
* blink on an irq stack frame.
*/
};

4
arch/arm/core/aarch32/cortex_m/Kconfig
View file

@ -7,7 +7,7 @@
# if CPU_CORTEX_M block so that SoCs can select which core they are using
# without having to select all the options related to that core. Everything
# else is captured inside the if CPU_CORTEX_M block so they are not exposed
# if one select a differnet ARM Cortex Family (Cortex-A or Cortex-R)
# if one select a different ARM Cortex Family (Cortex-A or Cortex-R)
config CPU_CORTEX_M0
bool
@ -409,7 +409,7 @@ config NULL_POINTER_EXCEPTION_DETECTION_MPU
CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE)
is not unmapped (covered by an MPU region already).
If it is unmapped null-pointer dereferencing may
still be idirectly detected (e.g. via a precise
still be indirectly detected (e.g. via a precise
Bus access fault), but this is not guaranteed. A
build-time message warns the user of this scenario.

2
arch/arm/core/aarch32/cortex_m/timing.c
View file

@ -63,7 +63,7 @@ static inline uint64_t z_arm_dwt_freq_get(void)
/*
* cycles are in 32-bit, and delta must be
* calculated in 32-bit percision. Or it would
* calculated in 32-bit precision. Or it would be
* wrapping around in 64-bit.
*/
dcyc = (uint32_t)cyc_end - (uint32_t)cyc_start;

2
arch/arm/core/aarch32/fatal.c
View file

@ -74,7 +74,7 @@ void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
* - We expect the supplied exception stack frame to always be a valid
* frame. That is because, if the ESF cannot be stacked during an SVC,
* a processor fault (e.g. stacking error) will be generated, and the
* fault handler will executed insted of the SVC.
* fault handler will executed instead of the SVC.
*
* @param esf exception frame
*/

2
arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h
View file

@ -583,7 +583,7 @@ static int mpu_configure_dynamic_mpu_regions(const struct z_arm_mpu_partition
#else
/* We are going to skip the full partition of the background areas.
* So we can disable MPU regions inside which dynamic memroy regions
* So we can disable MPU regions inside which dynamic memory regions
* may be programmed.
*/
for (int i = 0; i < MPU_DYNAMIC_REGION_AREAS_NUM; i++) {

2
arch/posix/include/asm_inline_gcc.h
View file

@ -1 +1 @@
/* EMTPTY ON PURPOSE. Why do the intel and ARM arch have 2 versions of it? */
/* EMPTY ON PURPOSE. Why do the intel and ARM arch have 2 versions of it? */

2
arch/posix/include/posix_cheats.h
View file

@ -12,7 +12,7 @@
*
* Most users will be normally unaware of this file existence, unless they have
* a link issue in which their POSIX functions calls are reported in errors (as
* zap_<origian_func_name>).
* zap_<original_func_name>).
* If you do see a link error telling you that zap_something is undefined, it is
* likely that you forgot to select the corresponding Zephyr POSIX API.
*

2
arch/x86/core/ia32/gdbstub.c
View file

@ -196,7 +196,7 @@ size_t arch_gdb_reg_writeone(struct gdb_ctx *ctx, uint8_t *hex, size_t hexlen,
if (regno == GDB_ORIG_EAX) {
/* GDB requires orig_eax that seems to be
* Linux specific. Unfortunely if we just
* Linux specific. Unfortunately if we just
* return error, GDB will stop working.
* So just fake an OK response by saying
* that we have processed the hex string.

2
arch/x86/gen_gdt.py
View file

@ -75,7 +75,7 @@ ACCESS_RW = 1 << 1 # read or write permission
def create_gdt_pseudo_desc(addr, size):
"""Create pseudo GDT descriptor"""
debug("create pseudo decriptor: %x %x" % (addr, size))
debug("create pseudo descriptor: %x %x" % (addr, size))
# ...and take back one byte for the Intel god whose Ark this is...
size = size - 1
return struct.pack(GDT_PD_FMT, size, addr, 0)

2
arch/x86/gen_mmu.py
View file

@ -608,7 +608,7 @@ def parse_args():
parser.add_argument("--map", action='append',
help=textwrap.dedent('''\
Map extra memory:
<physical address>,<size>[,<flags:LUWXD>[,<virtual adderss>]]
<physical address>,<size>[,<flags:LUWXD>[,<virtual address>]]
where flags can be empty or combination of:
L - Large page (2MB or 4MB),
U - Userspace accessible,

2
arch/x86/include/ia32/exception.h
View file

@ -33,7 +33,7 @@
/* Unfortunately, GCC extended asm doesn't work at toplevel so we need
* to stringify stuff.
*
* What we are doing here is generating entires in the .intList section
* What we are doing here is generating entries in the .intList section
* and also the assembly language stubs for the exception. We use
* .gnu.linkonce section prefix so that the linker only includes the
* first one of these it encounters for a particular vector. In this

2
arch/x86/timing.c
View file

@ -30,7 +30,7 @@ void arch_timing_x86_init(void)
/*
* cycles are in 32-bit, and delta must be
* calculated in 32-bit percision. Or it would
* calculated in 32-bit precision. Or it would be
* wrapping around in 64-bit.
*/
dcyc = (uint32_t)cyc_end - (uint32_t)cyc_start;

2
arch/x86/zefi/README.txt
View file

@ -46,7 +46,7 @@ Linux toolchain. EFI binaries are relocatable PE-COFF files --
basically Windows DLLs. But our compiler only generates code for ELF
targets.
These environments differ in the way they implemenqt position
These environments differ in the way they implement position
independent code. Non-static global variables and function addresses
in ELF get found via GOT and PLT tables that are populated at load
time by a system binary (ld-linux.so). But there is no ld-linux.so in

2
arch/xtensa/include/xtensa-asm2-s.h
View file

@ -38,7 +38,7 @@
* context.
*
* - If the WOE bit is not enabled (for example, in code written for
* the CALL0 ABI), this becomes a silent noop and operates compatbily.
* the CALL0 ABI), this becomes a silent noop and operates compatibly.
*
* - In memory protection situations, this relies on the existing
* exception handlers (and thus their use of the L/S32E

2
boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.dts
View file

@ -124,7 +124,7 @@ zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
};
// All PWM's should be enaled
// All PWM's should be enabled
&pwm0 {
status = "okay";
};

2
boards/arm/bl654_sensor_board/doc/bl654_sensor_board.rst
View file

@ -121,7 +121,7 @@ The sensor can be powered directly from a coin cell or from a voltage supplied
on the UART pins, the board accepts voltage from 1.8v-3.3v. Note that if using a
battery with a UART/debugger connected, the voltage of the UART/debugger (if it
does not automatically sense/adjust) must be within 0.3v of the voltage of the
coin cell to prevent supression diodes in the nRF52840 silicon being activated
coin cell to prevent suppression diodes in the nRF52840 silicon being activated
or possible back-powering of the battery.
To power the board from an external source via UART, the solder bridge SB1 must

2
boards/arm/ip_k66f/linker.ld
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021 DENX Software Engineeering GmbH
* Copyright (c) 2021 DENX Software Engineering GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/

2
boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts
View file

@ -161,7 +161,7 @@
/* LM75ADP temperature sensor on addr 0x48 */
};
/* Attention!: the spi-sck pin is in confict with the boot_button on pb13 */
/* Attention!: the spi-sck pin is in conflict with the boot_button on pb13 */
&spi2 {
pinctrl-0 = <&spi2_nss_pb9 &spi2_sck_pb13
&spi2_miso_pb14 &spi2_mosi_pa10>;

2
boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts
View file

@ -65,7 +65,7 @@
flag = <NPCX_PSL_FALLING_EDGE>;
};
/* Overwirte default device properties with overlays in board dt file here. */
/* Overwrite default device properties with overlays in board dt file here. */
&uart1 {
status = "okay";
current-speed = <115200>;

2
boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts
View file

@ -77,7 +77,7 @@
flag = <NPCX_PSL_FALLING_EDGE>;
};
/* Overwirte default device properties with overlays in board dt file here. */
/* Overwrite default device properties with overlays in board dt file here. */
&uart1 {
status = "okay";
current-speed = <115200>;

4
boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig
View file

@ -12,8 +12,8 @@ config BOARD
# To let the nRF5 bootloader load an application, the application
# must be linked after Nordic MBR, that is factory-programmed on the board.
# Nordic nRF5 booatloader exists outside of the partitions specified in the
# DTS file, so we manually override FLASH_LOAD_OFFEST to link the application
# Nordic nRF5 bootloader exists outside of the partitions specified in the
# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application
# correctly, after Nordic MBR.
# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION

2
boards/arm/nucleo_f746zg/nucleo_f746zg.dts
View file

@ -12,7 +12,7 @@
/*
* WARNING: The pin PA7 will conflict on selection of SPI_1 and ETH_STM32_HAL.
* If you require both peripherals, and you do not need Arduino Uno v3
* comaptability, the pin PB5 (also on ST Zio connector) can be used
* compatibility, the pin PB5 (also on ST Zio connector) can be used
* for the SPI_1 MOSI signal.
*/

2
boards/arm/nucleo_f756zg/nucleo_f756zg.dts
View file

@ -12,7 +12,7 @@
/*
* WARNING: The pin PA7 will conflict on selection of SPI_1 and ETH_STM32_HAL.
* If you require both peripherals, and you do not need Arduino Uno v3
* comaptability, the pin PB5 (also on ST Zio connector) can be used
* compatibility, the pin PB5 (also on ST Zio connector) can be used
* for the SPI_1 MOSI signal.
*/

2
boards/arm/nucleo_f767zi/nucleo_f767zi.dts
View file

@ -12,7 +12,7 @@
/*
* WARNING: The pin PA7 will conflict on selection of SPI_1 and ETH_STM32_HAL.
* If you require both peripherals, and you do not need Arduino Uno v3
* comaptability, the pin PB5 (also on ST Zio connector) can be used
* compatibility, the pin PB5 (also on ST Zio connector) can be used
* for the SPI_1 MOSI signal.
*/

2
boards/arm/thingy53_nrf5340/board.c
View file

@ -103,7 +103,7 @@ static int setup(const struct device *dev)
* sensors require, 2ms and 1ms power on delay respectively. In order not to sum
* delays, common delay is introduced in the board start up file. This code is
* executed after sensors are powered up and before their initialization.
* It's ensured by build asserts at the beggining of this file.
* It's ensured by build asserts at the beginning of this file.
*/
k_msleep(2);
}

2
boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig
View file

@ -1,7 +1,7 @@
# Copyright (c) 2021 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
# The Zephyr build from this defconfig is execpted to boot from
# The Zephyr build from this defconfig is expected to boot from
# Intel Arm Trusted Firmware (ATF)
# Boot Flow: BL21 -> BL31 -> Zephyr

2
boards/arm64/xenvm/xenvm.dts
View file

@ -7,7 +7,7 @@
*
* # LIBXL_DEBUG_DUMP_DTB=domu-libxl.dtb xl create zephyr.conf
*
* decompilling resulting domu-libxl.dtb and then manually aligning it
* decompiling resulting domu-libxl.dtb and then manually aligning it
* with zephyr requirements.
*/

2
boards/posix/native_posix/board_soc.h
View file

@ -7,7 +7,7 @@
* @file Extra definitions provided by the board to soc.h
*
* Background:
* The POSIC ARCH/SOC/board layering is different than in normal archs
* The POSIX ARCH/SOC/board layering is different than in normal archs
* The "SOC" does not provide almost any of the typical SOC functionality
* but that is left for the "board" to define it
* Device code may rely on the soc.h defining some things (like the interrupts

4
boards/posix/native_posix/timer_model.c
View file

@ -174,7 +174,7 @@ void hwtimer_cleanup(void)
}
/**
* Enable the HW timer tick interrupts with a period <period> in micoseconds
* Enable the HW timer tick interrupts with a period <period> in microseconds
*/
void hwtimer_enable(uint64_t period)
{
@ -373,7 +373,7 @@ void hwtimer_get_pseudohost_rtc_time(uint32_t *nsec, uint64_t *sec)
/*
* Note: long double has a 64bits mantissa in x86.
* Therefore to avoid loss of precision after 500 odd years into
* the epoc, we first calculate the offset from the last adjustment
* the epoch, we first calculate the offset from the last adjustment
* time split in us and ns. So we keep the full precision for 500 odd
* years after the last clock ratio adjustment (or native_posix boot,
* whichever is latest).

2
boards/posix/native_posix/tracing.c
View file

@ -45,7 +45,7 @@ void posix_print_trace(const char *format, ...)
}
/**
* Are stdout and stderr connectd to a tty
* Are stdout and stderr connected to a tty
* 0 = no
* 1 = yes
* -1 = we do not know yet

2
boards/riscv/m2gl025_miv/m2gl025_miv_defconfig
View file

@ -12,5 +12,5 @@ CONFIG_RISCV_MACHINE_TIMER=y
CONFIG_GPIO=n
CONFIG_XIP=y
# Workaround for incorect SYS_CLOCK_HW_CYCLES_PER_SEC
# Workaround for incorrect SYS_CLOCK_HW_CYCLES_PER_SEC
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100

2
boards/shields/x_nucleo_eeprma2/x_nucleo_eeprma2.overlay
View file

@ -71,7 +71,7 @@
/*
* All chip select pins have an on board 10k pull-up resistor to VCC,
* and are connected to their respective arduino pins via a normally
* closed solder brige.
* closed solder bridge.
*
* All hold pins are connected to VCC with a 10k pull-up, and
* have a connection to arduino pin A3 on CN8 via an open solder bridge.

2
boards/xtensa/intel_s1000_crb/support/device.py
View file

@ -7,7 +7,7 @@
# Author: Sathish Kuttan <sathish.k.kuttan@intel.com>
# This file defines device class that contains functions to
# setup/cconfigure SPI master device and GPIO pins required
# setup/configure SPI master device and GPIO pins required
# to communicate with the target.
# Member functions are provided to send and receive messages
# over the SPI bus

2
cmake/bintools/bintools_template.cmake
View file

@ -10,7 +10,7 @@
# - disassembly : Tool for disassemble the target
# - elfconvert : Tool for converting from elf into another format.
# - readelf : Tool for elf file processing
# - strip : Tool for symnbol stripping
# - strip : Tool for symbol stripping
#
# Each tool will have the following minimum properties:
# - <tool>_command : Name of executable to call

2
cmake/bintools/host-gnu/target.cmake
View file

@ -5,7 +5,7 @@
find_program(CMAKE_OBJCOPY objcopy)
find_program(CMAKE_OBJDUMP objdump)
find_program(CMAKE_AR ar )
find_program(CMAKE_RANLILB ranlib )
find_program(CMAKE_RANLIB ranlib )
find_program(CMAKE_READELF readelf)
find_program(CMAKE_GDB gdb )

2
cmake/bintools/llvm/target.cmake
View file

@ -1,6 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
# Configures binary toos as llvm binary tool set
# Configures binary tools as llvm binary tool set
if(DEFINED TOOLCHAIN_HOME)
set(find_program_clang_args PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH)

2
cmake/compiler/arcmwdt/compiler_flags.cmake
View file

@ -132,7 +132,7 @@ set_property(TARGET compiler-cpp PROPERTY dialect_cpp2a "")
set_property(TARGET compiler-cpp PROPERTY dialect_cpp20 "")
set_property(TARGET compiler-cpp PROPERTY dialect_cpp2b "")
# Disable exeptions flag in C++
# Disable exceptions flag in C++
set_property(TARGET compiler-cpp PROPERTY no_exceptions "-fno-exceptions")
# Disable rtti in C++

2
cmake/compiler/compiler_flags_template.cmake
View file

@ -65,7 +65,7 @@ set_property(TARGET compiler-cpp PROPERTY dialect_cpp2a)
set_property(TARGET compiler-cpp PROPERTY dialect_cpp20)
set_property(TARGET compiler-cpp PROPERTY dialect_cpp2b)
# Flag for disabling exeptions in C++
# Flag for disabling exceptions in C++
set_property(TARGET compiler-cpp PROPERTY no_exceptions)
# Flag for disabling rtti in C++

4
cmake/compiler/gcc/compiler_flags.cmake
View file

@ -129,7 +129,7 @@ set_property(TARGET compiler-cpp PROPERTY dialect_cpp20 "-std=c++20"
set_property(TARGET compiler-cpp PROPERTY dialect_cpp2b "-std=c++2b"
"-Wno-register" "-Wno-volatile")
# Disable exeptions flag in C++
# Disable exceptions flag in C++
set_property(TARGET compiler-cpp PROPERTY no_exceptions "-fno-exceptions")
# Disable rtti in C++
@ -159,7 +159,7 @@ endif()
# gcc flag for a hosted (no-freestanding) application
check_set_compiler_property(APPEND PROPERTY hosted -fno-freestanding)
# gcc flag for a freestandingapplication
# gcc flag for a freestanding application
set_compiler_property(PROPERTY freestanding -ffreestanding)
# Flag to enable debugging

2
cmake/compiler/gcc/target.cmake
View file

@ -96,7 +96,7 @@ endif()
# link a dummy C file.
#
# CMake checks compiler flags with check_c_compiler_flag() (Which we
# wrap with target_cc_option() in extentions.cmake)
# wrap with target_cc_option() in extensions.cmake)
foreach(isystem_include_dir ${NOSTDINC})
list(APPEND isystem_include_flags -isystem "\"${isystem_include_dir}\"")
endforeach()

2
cmake/linker/ld/gcc/linker_flags.cmake
View file

@ -2,7 +2,7 @@
# Using a config check is ok for now, but in future it would be desired if
# linker flags themselves are not depending on actual configurations.
# All flags should be described, and the caller should now the flag name to use.
# All flags should be described, and the caller should know the flag name to use.
if (NOT CONFIG_COVERAGE_GCOV)
set_property(TARGET linker PROPERTY coverage -lgcov)
endif()

2
cmake/linker/linker_flags_template.cmake
View file

@ -12,5 +12,5 @@ check_set_linker_property(TARGET linker APPEND PROPERTY sanitize_undefined)
# Set this flag if the linker supports reporting of memusage as part of link,
# such as ls --print-memory-usage flag.
# If memory reporting is a post build command, please use
# cmake/bintools/bintools.cmake insted.
# cmake/bintools/bintools.cmake instead.
check_set_linker_property(TARGET linker PROPERTY memusage)

2
cmake/linker/linker_script_common.cmake
View file

@ -495,7 +495,7 @@ endfunction()
# Tasks:
# - Apply missing settings, such as initial address for first section in a region.
# - Symbol names on sections
# - Ordered list of all sections for easier retrival on printing and configuration.
# - Ordered list of all sections for easier retrieval on printing and configuration.
function(process_region_common)
cmake_parse_arguments(REGION_COMMON "" "OBJECT" "" ${ARGN})

2
cmake/linker_script/arm/linker.cmake
View file

@ -6,7 +6,7 @@ set_ifndef(region_min_align CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE)
# to make linker section alignment comply with MPU granularity.
set_ifndef(region_min_align CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
# If building without MPU support, use default 4-byte alignment.. if not set abve.
# If building without MPU support, use default 4-byte alignment.. if not set above.
set_ifndef(region_min_align 4)
# Note, the `+ 0` in formulas below avoids errors in cases where a Kconfig

2
cmake/linker_script/common/common-rom.cmake
View file

@ -34,7 +34,7 @@ if(CONFIG_CPLUSPLUS)
#
# The compiler fills the constructor pointers table below,
# hence symbol __CTOR_LIST__ must be aligned on word
# boundary. To align with the C++ standard, the first elment
# boundary. To align with the C++ standard, the first element
# of the array contains the number of actual constructors. The
# last element is NULL.
#

26
cmake/modules/extensions.cmake
View file

@ -307,7 +307,7 @@ function(process_flags lang input output)
# $<$<OTHER_EXPRESSION:$<COMPILE_LANGUAGE:C>:something>>
string(REGEX MATCH "(\\\$<)[^\\\$]*(\\\$<)[^\\\$]*(\\\$<)" IGNORE_RESULT ${flag})
if(CMAKE_MATCH_2)
# Nested generator expressions are used, just substitue `$<COMPILE_LANGUAGE:${l}>` to `1`
# Nested generator expressions are used, just substitute `$<COMPILE_LANGUAGE:${l}>` to `1`
string(REGEX REPLACE "\\\$<COMPILE_LANGUAGE:${l}>" "1" updated_flag ${flag})
endif()
list(APPEND tmp_list ${updated_flag})
@ -317,7 +317,7 @@ function(process_flags lang input output)
endforeach()
if(NOT is_compile_lang_generator_expression)
# SHELL is used to avoid de-deplucation, but when process flags
# SHELL is used to avoid de-duplication, but when process flags
# then this tag must be removed to return real compile/linker flags.
if(flag MATCHES "SHELL:[ ]*(.*)")
separate_arguments(flag UNIX_COMMAND ${CMAKE_MATCH_1})
@ -436,7 +436,7 @@ endmacro()
# ZEPHYR_MODULE/drivers/entropy/CMakeLists.txt
# with content:
# zephyr_library_amend()
# zephyr_libray_add_sources(...)
# zephyr_library_add_sources(...)
#
# It is also possible to use generator expression when amending to Zephyr
# libraries.
@ -524,7 +524,7 @@ endfunction()
# Add the existing CMake library 'library' to the global list of
# Zephyr CMake libraries. This is done automatically by the
# constructor but must called explicitly on CMake libraries that do
# constructor but must be called explicitly on CMake libraries that do
# not use a zephyr library constructor.
function(zephyr_append_cmake_library library)
if(TARGET zephyr_prebuilt)
@ -555,7 +555,7 @@ endfunction()
# The partition argument is the name of the partition where the library shall
# be placed.
#
# Note: Ensure the given partition has been define using
# Note: Ensure the given partition has been defined using
# K_APPMEM_PARTITION_DEFINE in source code.
function(zephyr_library_app_memory partition)
set_property(TARGET zephyr_property_target
@ -595,7 +595,7 @@ endfunction()
# files of this library will be accessible to the 'app' library.
#
# This is done because when a user uses Kconfig to enable a library he
# expects to be able to include it's header files and call it's
# expects to be able to include its header files and call its
# functions out-of-the box.
#
# A Zephyr interface library should be used when there exists some
@ -2073,7 +2073,7 @@ endfunction()
# zephyr_file(<mode> <arg> ...)
#
# Zephyr file function extension.
# This function currently support the following <modes>
# This function currently supports the following <modes>
#
# APPLICATION_ROOT <path>: Check all paths in provided variable, and convert
# those paths that are defined with `-D<path>=<val>`
@ -3798,8 +3798,8 @@ endfunction()
# Configure an output section with additional input sections.
# An output section can be configured with additional input sections besides its
# default section.
# For example, adding the input section `foo` to the output section bar, with KEEP
# attribute, then call:
# For example, to add the input section `foo` to the output section bar, with KEEP
# attribute, call:
# zephyr_linker_section_configure(SECTION bar INPUT foo KEEP)
#
# ALIGN <alignment> : Will align the input section placement inside the load
@ -3808,14 +3808,14 @@ endfunction()
# first section in output.
# SORT <NAME> : Sort the input sections according to <type>.
# Currently only `NAME` is supported.
# KEEP : Do no eliminate input section during linking
# KEEP : Do not eliminate input section during linking
# PRIO : The priority of the input section. Per default, input
# sections order is not guaranteed by all linkers, but
# using priority, then Zephyr CMake linker will create
# sections so order can be guaranteed. All unprioritized
# using priority Zephyr CMake linker will create sections
# such that order can be guaranteed. All unprioritized
# sections will internally be given a CMake process order
# priority counting from 100, so first unprioritized section
# is handles internal pri0 100, next 101, and so on.
# is handled internal prio 100, next 101, and so on.
# To ensure a specific input section come before those,
# you may use `PRIO 50`, `PRIO 20` and so on.
# To ensure an input section is at the end, it is advised

2
cmake/modules/verify-toolchain.cmake
View file

@ -100,7 +100,7 @@ if(NOT DEFINED ZEPHYR_TOOLCHAIN_VARIANT)
set(error_msg "ZEPHYR_TOOLCHAIN_VARIANT not specified and no Zephyr SDK is installed.\n")
string(APPEND error_msg "Please set ZEPHYR_TOOLCHAIN_VARIANT to the toolchain to use or install the Zephyr SDK.")
else()
# Note: When CMake mimimun version becomes >= 3.17, change this loop into:
# Note: When CMake minimum version becomes >= 3.17, change this loop into:
# foreach(version config IN ZIP_LISTS Zephyr-sdk_CONSIDERED_VERSIONS Zephyr-sdk_CONSIDERED_CONFIGS)
set(error_msg "The Zephyr SDK version you are using is not supported, please update your SDK.\n")
set(missing_version "You need SDK version ${TOOLCHAIN_ZEPHYR_MINIMUM_REQUIRED_VERSION} or newer.")

6
cmake/target_toolchain_flags.cmake
View file

@ -1,4 +1,4 @@
# Uniquely identify the toolchain wrt. it's capabilities.
# Uniquely identify the toolchain wrt. its capabilities.
#
# What we are looking for, is a signature definition that is defined
# like this:
@ -29,9 +29,9 @@ set(TOOLCHAIN_SIGNATURE ${TOOLCHAIN_SIGNATURE}_${COMPILER_SIGNATURE})
# Zephyr Kconfig settings or the CSTD global property.
include(${CMAKE_CURRENT_LIST_DIR}/compiler/compiler_features.cmake)
# Loading of templates are strictly not needed as they does not set any
# Loading of templates are strictly not needed as they do not set any
# properties.
# They purely provides an overview as well as a starting point for supporting
# They purely provide an overview as well as a starting point for supporting
# a new toolchain.
include(${CMAKE_CURRENT_LIST_DIR}/compiler/compiler_flags_template.cmake)
include(${CMAKE_CURRENT_LIST_DIR}/linker/linker_flags_template.cmake)

2
cmake/toolchain/cross-compile/generic.cmake
View file

@ -4,7 +4,7 @@
# toolchain with a single environment variable.
#
# It is a legacy mechanism that will in Zephyr translate to
# specififying ZEPHYR_TOOLCHAIN_VARIANT to 'cross-compile' with the location
# specifying ZEPHYR_TOOLCHAIN_VARIANT to 'cross-compile' with the location
# 'CROSS_COMPILE'.
#
# New users should set the env var 'ZEPHYR_TOOLCHAIN_VARIANT' to

2
doc/reference/api/design_guidelines.rst
View file

@ -118,5 +118,5 @@ not implemented or optional:
- When an API is implemented, but the particular combination of options
requested in the call cannot be satisfied by the implementation the call shall
return -ENOTSUP. (For example, a request for a level-triggered GPIO interrupt on
return ``-ENOTSUP``. (For example, a request for a level-triggered GPIO interrupt on
hardware that supports only edge-triggered interrupts)

4
drivers/adc/adc_emul.c
View file

@ -37,7 +37,7 @@ enum adc_emul_input_source {
/**
* @brief Channel of emulated ADC config
*
* This structure contains configuration of one channel of emualted ADC.
* This structure contains configuration of one channel of emulated ADC.
*/
struct adc_emul_chan_cfg {
/** Pointer to function used to obtain input mV */
@ -94,7 +94,7 @@ struct adc_emul_data {
struct adc_emul_chan_cfg *chan_cfg;
/** Structure used for acquisition thread */
struct k_thread thread;
/** Semaphore used to control acquisiton thread */
/** Semaphore used to control acquisition thread */
struct k_sem sem;
/** Mutex used to control access to channels config and ref voltages */
struct k_mutex cfg_mtx;

2
drivers/adc/adc_ite_it8xxx2.c
View file

@ -64,7 +64,7 @@ struct adc_it8xxx2_data {
};
/*
* Strcture adc_it8xxx2_cfg is about the setting of adc
* Structure adc_it8xxx2_cfg is about the setting of adc
* this config will be used at initial time
*/
struct adc_it8xxx2_cfg {

2
drivers/adc/adc_mcux_lpadc.c
View file

@ -401,7 +401,7 @@ static const struct adc_driver_api mcux_lpadc_driver_api = {
"Invalid voltage reference source"); \
ASSERT_LPADC_CALIBRATION_AVERAGE_VALID( \
DT_INST_PROP(n, calibration_average), \
"Invalid converion average number for auto-calibration time"); \
"Invalid conversion average number for auto-calibration time"); \
ASSERT_WITHIN_RANGE(DT_INST_PROP(n, power_level), 1, 4, \
"Invalid power level"); \
static const struct mcux_lpadc_config mcux_lpadc_config_##n = { \

2
drivers/adc/adc_stm32.c
View file

@ -757,7 +757,7 @@ static int adc_stm32_check_acq_time(uint16_t acq_time)
return 0;
}
LOG_ERR("Conversion time not supportted.");
LOG_ERR("Conversion time not supported.");
return -EINVAL;
}

8
drivers/audio/intel_dmic.c
View file

@ -86,7 +86,7 @@ struct dmic_configuration {
#define DMIC_HIGH_RATE_MIN_FS 64000
#define DMIC_HIGH_RATE_OSR_MIN 40
/* Used for scaling FIR coeffcients for HW */
/* Used for scaling FIR coefficients for HW */
#define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
#define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)
@ -218,7 +218,7 @@ int norm_int32(int32_t val)
/* This function returns a raw list of potential microphone clock and decimation
* modes for achieving requested sample rates. The search is constrained by
* decimation HW capabililies and setup parameters. The parameters such as
* decimation HW capabilities and setup parameters. The parameters such as
* microphone clock min/max and duty cycle requirements need be checked from
* used microphone component datasheet.
*/
@ -518,7 +518,7 @@ static int fir_coef_scale(int32_t *fir_scale, int *fir_shift, int add_shift,
* Note: If there is no filter available an error is returned. The parameters
* should be reviewed for such case. If still a filter is missing it should be
* added into the included set. FIR decimation with a high factor usually
* needs compromizes into specifications and is not desirable.
* needs compromises into specifications and is not desirable.
*/
static int select_mode(struct dmic_configuration *cfg,
struct matched_modes *modes)
@ -676,7 +676,7 @@ static int source_ipm_helper(struct pdm_chan_cfg *config, uint32_t *source_mask,
* is checked whether the controller should operate as stereo or mono
* left (A) or mono right (B) mode. Mono right mode is setup as channel
* swapped mono left. The function returns also in array source[] the
* indice of enabled pdm controllers to be used for IPM configuration.
* indices of enabled pdm controllers to be used for IPM configuration.
*/
for (chan_ix = 0U; chan_ix < config->req_num_chan; chan_ix++) {

2
drivers/audio/tlv320dac310x.c
View file

@ -268,7 +268,7 @@ static int codec_configure_clocks(const struct device *dev,
i2s->frame_clk_freq);
if (cfg->mclk_freq <= DAC_PROC_CLK_FREQ_MAX) {
/* use MCLK frequecy as the DAC processing clock */
/* use MCLK frequency as the DAC processing clock */
ndac = 1;
} else {
ndac = cfg->mclk_freq / DAC_PROC_CLK_FREQ_MAX;

4
drivers/bluetooth/hci/h5.c
View file

@ -335,7 +335,7 @@ static void retx_timeout(struct k_work *work)
k_fifo_init(&tmp_queue);
/* Queue to temperary queue */
/* Queue to temporary queue */
while ((buf = net_buf_get(&h5.tx_queue, K_NO_WAIT))) {
net_buf_put(&tmp_queue, buf);
}
@ -446,7 +446,7 @@ static void bt_uart_isr(const struct device *unused, void *user_data)
}
break;
case HEADER:
/* In a case we confuse ending slip delimeter
/* In a case we confuse ending slip delimiter
* with starting one.
*/
if (byte == SLIP_DELIMITER) {

2
drivers/can/Kconfig.rcar
View file

@ -1,4 +1,4 @@
# Reneas R-Car CAN configuration options
# Renesas R-Car CAN configuration options
# Copyright (c) 2021 IoT.bzh
# SPDX-License-Identifier: Apache-2.0

4
drivers/can/can_mcan.h
View file

@ -77,7 +77,7 @@ struct can_mcan_tx_buffer_hdr {
union {
struct {
volatile uint32_t ext_id : 29; /* Identifier */
volatile uint32_t rtr : 1; /* Retmote Transmission Request*/
volatile uint32_t rtr : 1; /* Remote Transmission Request*/
volatile uint32_t xtd : 1; /* Extended identifier */
volatile uint32_t esi : 1; /* Error state indicator */
};
@ -109,7 +109,7 @@ struct can_mcan_tx_buffer {
struct can_mcan_tx_event_fifo {
volatile uint32_t id : 29; /* Identifier */
volatile uint32_t rtr : 1; /* Retmote Transmission Request*/
volatile uint32_t rtr : 1; /* Remote Transmission Request*/
volatile uint32_t xtd : 1; /* Extended identifier */
volatile uint32_t esi : 1; /* Error state indicator */

2
drivers/can/can_mcan_int.h
View file

@ -42,7 +42,7 @@
#define CAN_MCAN_CREL_REL CAN_MCAN_CREL_REL_MSK
/**************** Bit definition for CAN_MCAN_ENDN register *****************/
/* Endiannes Test Value */
/* Endianness Test Value */
#define CAN_MCAN_ENDN_ETV_POS (0U)
#define CAN_MCAN_ENDN_ETV_MSK (0xFFFFFFFFUL << CAN_MCAN_ENDN_ETV_POS)
#define CAN_MCAN_ENDN_ETV CAN_MCAN_ENDN_ETV_MSK

2
drivers/can/can_stm32.c
View file

@ -1123,7 +1123,7 @@ void can_stm32_remove_rx_filter(const struct device *dev, int filter_id)
if (!CAN_BANK_IS_EMPTY(data->filter_usage, bank_nr)) {
can->FA1R |= bank_bit;
} else {
LOG_DBG("Bank number %d is empty -> deakivate", bank_nr);
LOG_DBG("Bank number %d is empty -> deactivate", bank_nr);
}
can->FMR &= ~(CAN_FMR_FINIT);

2
drivers/console/xtensa_sim_console.c
View file

@ -69,7 +69,7 @@ static int xt_sim_console_init(const struct device *arg)
return 0;
}
/* UART consloe initializes after the UART device itself */
/* UART console initializes after the UART device itself */
SYS_INIT(xt_sim_console_init,
#if defined(CONFIG_EARLY_CONSOLE)
PRE_KERNEL_1,

4
drivers/counter/counter_cmos.c
View file

@ -23,7 +23,7 @@
/*
* A snapshot of the RTC state, or at least the state we're
* interested in. This struct should not be modified without
* serious consideraton, for two reasons:
* serious consideration, for two reasons:
*
* 1. Order of the element is important, and must correlate
* with addrs[] and NR_BCD_VALS (see below), and
@ -44,7 +44,7 @@ struct state {
/*
* If the clock is in BCD mode, the first NR_BCD_VALS
* valies in 'struct state' are BCD-encoded.
* values in 'struct state' are BCD-encoded.
*/
#define NR_BCD_VALS 6

2
drivers/counter/counter_mcux_pit.c
View file

@ -149,7 +149,7 @@ static int mcux_pit_set_alarm(const struct device *dev, uint8_t chan_id,
}
if (ticks > mcux_pit_get_top_value(dev)) {
LOG_ERR("Invalid tciks");
LOG_ERR("Invalid ticks");
return -EINVAL;
}

2
drivers/counter/counter_xlnx_axi_timer.c
View file

@ -292,7 +292,7 @@ static int xlnx_axi_timer_init(const struct device *dev)
const struct xlnx_axi_timer_config *config = dev->config;
LOG_DBG("max top value = 0x%08x", config->info.max_top_value);
LOG_DBG("freqency = %d", config->info.freq);
LOG_DBG("frequency = %d", config->info.freq);
LOG_DBG("channels = %d", config->info.channels);
xlnx_axi_timer_write32(dev, config->info.max_top_value, TLR0_OFFSET);

2
drivers/counter/rtc_mcp7940n.c
View file

@ -204,7 +204,7 @@ static int read_register(const struct device *dev, uint8_t addr, uint8_t *val)
*
* @param dev the MCP7940N device pointer.
* @param unix_time pointer to time_t value that will contain unix time if
* sucessful.
* successful.
*
* @retval return 0 on success, or a negative error code from an I2C
* transaction.

2
drivers/crypto/crypto_ataes132a_priv.h
View file

@ -24,7 +24,7 @@
#define ATAES_MANUFACTID_REG 0xF02B
#define ATAES_PERMCONFIG_REG 0xF02D
/* Configuarion Pre-Lock Writable Registers */
/* Configuration Pre-Lock Writable Registers */
#define ATAES_I2CADDR_REG 0xF040
#define ATAES_CHIPCONFIG_REG 0xF042
#define ATAES_FREESPACE_ADDR 0xF180

6
drivers/disk/sdmmc_sdhc.h
View file

@ -324,13 +324,13 @@ enum sd_max_current {
enum sd_voltage {
SD_VOL_NONE = 0U,
/*!< indicate current voltage setting is not setting bu suser*/
/*!< indicate current voltage setting is not set by user*/
SD_VOL_3_3_V = 1U,
/*!< card operation voltage around 3.3v */
SD_VOL_3_0_V = 2U,
/*!< card operation voltage around 3.0v */
SD_VOL_1_8_V = 3U,
/*!< card operation voltage around 31.8v */
/*!< card operation voltage around 1.8v */
};
#define SDMMC_DEFAULT_BLOCK_SIZE (512U)
@ -529,7 +529,7 @@ static inline int sdhc_map_r1_status(int status)
return sdhc_map_flags(sdhc_r1_flags, status);
}
/* Converts an eary stage idle mode R1 code into an error code */
/* Converts an early stage idle mode R1 code into an error code */
static inline int sdhc_map_r1_idle_status(int status)
{
if (status < 0) {

2
drivers/disk/sdmmc_spi.c
View file

@ -661,7 +661,7 @@ static int sdhc_spi_detect(const struct device *dev)
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], sys_get_be32(&buf[9]));
/* Initilisation complete */
/* Initialisation complete */
sdhc_spi_set_status(dev, DISK_STATUS_OK);
return 0;

12
drivers/disk/usdhc.c
View file

@ -762,7 +762,7 @@ static int usdhc_adma2_descriptor_cfg(
min_entries = ((data_size /
USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);
}
/* calcucate the start entry for multiple descriptor mode,
/* calculate the start entry for multiple descriptor mode,
* ADMA engine is not stop, so update the descriptor
* data address and data size is enough
*/
@ -1537,7 +1537,7 @@ int usdhc_adjust_tuning_timing(USDHC_Type *base, uint32_t delay)
/* load the delay setting */
base->CLK_TUNE_CTRL_STATUS = clk_tune_ctrl;
/* check delat setting error */
/* check delay setting error */
if (base->CLK_TUNE_CTRL_STATUS &
(USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK |
USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK))
@ -1628,7 +1628,7 @@ static int usdhc_vol_switch(struct usdhc_priv *priv)
/*enable force clock on*/
usdhc_force_clk_on(base, true);
/* dealy 1ms,not exactly correct when use while */
/* delay 1ms,not exactly correct when use while */
usdhc_millsec_delay(20000U);
/*disable force clock on*/
usdhc_force_clk_on(base, false);
@ -1834,7 +1834,7 @@ uint32_t usdhc_set_sd_clk(USDHC_Type *base, uint32_t src_clk_hz, uint32_t sd_clk
}
}
} else {
/* in this situation , divsior and SDCLKFS
/* in this situation , divisor and SDCLKFS
* can generate same clock
* use SDCLKFS
*/
@ -1851,7 +1851,7 @@ uint32_t usdhc_set_sd_clk(USDHC_Type *base, uint32_t src_clk_hz, uint32_t sd_clk
} else {
/* in this condition , src_clk_hz = busClock_Hz, */
/* in DDR mode , set SDCLKFS to 0, divisor = 0, actually the
* totoal divider = 2U
* total divider = 2U
*/
divisor = 0U;
prescaler = 0U;
@ -2676,7 +2676,7 @@ APP_SEND_OP_COND_AGAIN:
}
if (ret) {
LOG_ERR("USDHC bus device initalization failed!");
LOG_ERR("USDHC bus device initialization failed!");
}
return ret;

2
drivers/display/ssd1306_regs.h
View file

@ -78,7 +78,7 @@
/*
* Timming and Driving Scheme Setting Command Table
* Timing and Driving Scheme Setting Command Table
*/
#define SSD1306_SET_CLOCK_DIV_RATIO 0xd5 /* double byte command */

2
drivers/dma/dma_iproc_pax_v1.c
View file

@ -62,7 +62,7 @@ static inline void rm_write_header_desc(void *desc, uint32_t toggle,
struct rm_header *r = (struct rm_header *)desc;
r->opq = opq;
/* DMA descriptor count init vlaue */
/* DMA descriptor count init value */
r->bdcount = bdcount;
r->prot = 0x0;
/* No packet extension, start and end set to '1' */

4
drivers/dma/dma_iproc_pax_v2.c
View file

@ -65,7 +65,7 @@ static inline void rm_write_header_desc(void *desc, uint32_t toggle,
r->opq = opq;
r->bdf = 0x0;
r->res1 = 0x0;
/* DMA descriptor count init vlaue */
/* DMA descriptor count init value */
r->bdcount = bdcount;
r->prot = 0x0;
r->res2 = 0x0;
@ -105,7 +105,7 @@ static inline void rm_write_pcie_desc(void *desc,
}
/**
* @brief Populate src/destionation descriptor
* @brief Populate src/destination descriptor
*/
static inline void rm_write_src_dst_desc(void *desc_ptr,
bool is_mega,

2
drivers/dma/dma_stm32_v1.c
View file

@ -399,7 +399,7 @@ uint32_t stm32_dma_get_pburst(struct dma_config *config, bool source_periph)
/*
* This function checks if the msize, mburst and fifo level is
* compitable. If they are not compitable, refer to the 'FIFO'
* compatible. If they are not compatible, refer to the 'FIFO'
* section in the 'DMA' chapter in the Reference Manual for more
* information.
* break is emitted since every path of the code has 'return'.

2
drivers/dma/dmamux_stm32.c
View file

@ -247,7 +247,7 @@ static const struct dma_driver_api dma_funcs = {
};
/*
* Each dmamux channel is hardwired to one dma controlers dma channel.
* Each dmamux channel is hardwired to one dma controllers dma channel.
* DMAMUX_CHANNEL_INIT_X macros resolve this mapping at build time for each
* dmamux channel using the dma dt properties dma_offset and dma_requests,
* such that it can be stored in dmamux_stm32_channels_X configuration.

2
drivers/ec_host_cmd_periph/ec_host_cmd_periph_handlers.c
View file

@ -30,7 +30,7 @@ z_vrfy_ec_host_cmd_periph_send(const struct device *dev,
Z_OOPS(Z_SYSCALL_OBJ(dev, K_OBJ_DRIVER_EC_HOST_CMD_PERIPH_API));
Z_OOPS(z_user_from_copy(&local_tx_buf, tx_buf, sizeof(*tx_buf)));
/* Ensure that user thread has acces to read buffer since
/* Ensure that user thread has access to read buffer since
* device will read from this memory location.
*/
Z_OOPS(Z_SYSCALL_MEMORY_READ(local_tx_buf.buf, local_tx_buf.size));

2
drivers/eeprom/eeprom_lpc11u6x.c
View file

@ -13,7 +13,7 @@
* This driver supports the on-chip EEPROM found on NXP LPC11U6x MCUs.
*
* @note This driver is only a wrapper for the IAP (In-Application Programming)
* EEPROM funcions.
* EEPROM functions.
*/
#include <drivers/eeprom.h>

2
drivers/eeprom/eeprom_simulator.c
View file

@ -51,7 +51,7 @@ static struct k_sem sem_lock;
#define SYNC_UNLOCK()
#endif
/* simulator statistcs */
/* simulator statistics */
STATS_SECT_START(eeprom_sim_stats)
STATS_SECT_ENTRY32(bytes_read) /* total bytes read */
STATS_SECT_ENTRY32(bytes_written) /* total bytes written */

4
drivers/entropy/entropy_cc13xx_cc26xx.c
View file

@ -158,8 +158,8 @@ static void entropy_cc13xx_cc26xx_isr(const void *arg)
k_sem_give(&data->sync);
}
/* Change the shutdown FROs' oscillating frequncy in an attempt to
* prevent further locking on to the sampling clock frequncy.
/* Change the shutdown FROs' oscillating frequency in an attempt to
* prevent further locking on to the sampling clock frequency.
*/
if (src & TRNG_FRO_SHUTDOWN) {
handle_shutdown_ovf();

8
drivers/espi/espi_mchp_xec.c
View file

@ -17,7 +17,7 @@
#define ESPI_XEC_VWIRE_ACK_DELAY 10ul
/* Maximum timeout to transmit a virtual wire packet.
* 10 ms expresed in multiples of 100us
* 10 ms expressed in multiples of 100us
*/
#define ESPI_XEC_VWIRE_SEND_TIMEOUT 100ul
@ -109,7 +109,7 @@ enum mchp_smvw_regs {
MCHP_SMVW08,
};
/* Microchip cannonical virtual wire mapping
/* Microchip canonical virtual wire mapping
* ------------------------------------------------------------------------|
* VW Idx | VW reg | SRC_ID3 | SRC_ID2 | SRC_ID1 | SRC_ID0 |
* ------------------------------------------------------------------------|
@ -255,7 +255,7 @@ static int espi_xec_configure(const struct device *dev, struct espi_cfg *cfg)
cap1 |= (iomode << MCHP_ESPI_GBL_CAP1_IO_MODE_POS);
}
/* Validdate and translate eSPI API channels to MEC capabilities */
/* Validate and translate eSPI API channels to MEC capabilities */
cap0 &= ~MCHP_ESPI_GBL_CAP0_MASK;
if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) {
if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_CHANNEL)) {
@ -1209,7 +1209,7 @@ static void ibf_kbc_isr(const struct device *dev)
struct espi_xec_data *data = (struct espi_xec_data *)(dev->data);
/* The high byte contains information from the host,
* and the lower byte speficies if the host sent
* and the lower byte specifies if the host sent
* a command or data. 1 = Command.
*/
uint32_t isr_data = ((KBC_REGS->EC_DATA & 0xFF) << E8042_ISR_DATA_POS) |

6
drivers/espi/espi_mchp_xec_v2.c
View file

@ -24,7 +24,7 @@
#define ESPI_XEC_VWIRE_ACK_DELAY 10ul
/* Maximum timeout to transmit a virtual wire packet.
* 10 ms expresed in multiples of 100us
* 10 ms expressed in multiples of 100us
*/
#define ESPI_XEC_VWIRE_SEND_TIMEOUT 100ul
@ -72,7 +72,7 @@ LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
#define XEC_PCR_REG_BASE \
((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
/* Microchip cannonical virtual wire mapping
/* Microchip canonical virtual wire mapping
* ------------------------------------------------------------------------|
* VW Idx | VW reg | SRC_ID3 | SRC_ID2 | SRC_ID1 | SRC_ID0 |
* ------------------------------------------------------------------------|
@ -236,7 +236,7 @@ static int espi_xec_configure(const struct device *dev, struct espi_cfg *cfg)
cap1 |= (iomode << MCHP_ESPI_GBL_CAP1_IO_MODE_POS);
}
/* Validdate and translate eSPI API channels to MEC capabilities */
/* Validate and translate eSPI API channels to MEC capabilities */
cap0 &= ~MCHP_ESPI_GBL_CAP0_MASK;
if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) {
if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_CHANNEL)) {

4
drivers/espi/espi_npcx.c
View file

@ -171,7 +171,7 @@ static void espi_init_wui_callback(const struct device *dev,
npcx_miwu_init_dev_callback(callback, wui, handler, dev);
npcx_miwu_manage_dev_callback(callback, 1);
/* Congiure MIWU setting and enable its interrupt */
/* Configure MIWU setting and enable its interrupt */
npcx_miwu_interrupt_configure(wui, NPCX_MIWU_MODE_EDGE,
NPCX_MIWU_TRIG_BOTH);
npcx_miwu_irq_enable(wui);
@ -390,7 +390,7 @@ static void espi_vw_notify_plt_rst(const struct device *dev)
if (wire) {
/* Set Peripheral Channel ready when PLTRST is de-asserted */
inst->ESPICFG |= BIT(NPCX_ESPICFG_PCHANEN);
/* Configure all host sub-modules in host doamin */
/* Configure all host sub-modules in host domain */
npcx_host_init_subs_host_domain();
}

2
drivers/espi/espi_saf_mchp_xec.c
View file

@ -659,7 +659,7 @@ static int check_ecp_access_size(uint32_t reqlen)
}
/*
* EC access (read/erase/write) to SAF atttached flash array
* EC access (read/erase/write) to SAF attached flash array
* cmd 0 = read
* 1 = write
* 2 = erase

2
drivers/ethernet/eth_dwmac.c
View file

@ -45,7 +45,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
*/
#define TX_AVAIL_WAIT K_MSEC(1)
/* descriptor index itterators */
/* descriptor index iterators */
#define INC_WRAP(idx, size) ({ idx = (idx + 1) % size; })
#define DEC_WRAP(idx, size) ({ idx = (idx + size - 1) % size; })

2
drivers/ethernet/eth_gecko.c
View file

@ -148,7 +148,7 @@ static struct net_pkt *frame_get(const struct device *dev)
__ASSERT_NO_MSG(dev_data != NULL);
__ASSERT_NO_MSG(cfg != NULL);
/* Preset indeces and total frame length */
/* Preset indices and total frame length */
sofIdx = UINT32_MAX;
eofIdx = UINT32_MAX;
total_len = 0;

2
drivers/ethernet/eth_mcux.c
View file

@ -421,7 +421,7 @@ void eth_mcux_phy_stop(struct eth_context *context)
break;
case eth_mcux_phy_state_wait:
k_work_cancel_delayable(&context->delayed_phy_work);
/* @todo, actually power downt he PHY ? */
/* @todo, actually power down the PHY ? */
context->phy_state = eth_mcux_phy_state_initial;
break;
case eth_mcux_phy_state_closing:

2
drivers/ethernet/eth_sam_gmac.c
View file

@ -1,6 +1,6 @@
/*
* Copyright (c) 2016 Piotr Mienkowski
* Copyringt (c) 2018 Antmicro Ltd
* Copyright (c) 2018 Antmicro Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/

2
drivers/ethernet/eth_xlnx_gem.c
View file

@ -768,7 +768,7 @@ static void eth_xlnx_gem_configure_clocks(const struct device *dev)
}
/*
* Caclculate the divisors for the target frequency.
* Calculate the divisors for the target frequency.
* The frequency of the PLL to which the divisors shall be applied are
* provided in the respective GEM's device tree data.
*/

2
drivers/ethernet/phy_xlnx_gem.c
View file

@ -250,7 +250,7 @@ static void phy_xlnx_gem_marvell_alaska_cfg(const struct device *dev)
if ((dev_data->phy_id & PHY_MRVL_PHY_ID_MODEL_MASK) ==
PHY_MRVL_PHY_ID_MODEL_88E151X) {
/*
* 88E151x only: onfigure the system interface and media type
* 88E151x only: configure the system interface and media type
* (i.e. "RGMII to Copper", 0x0). On the 88E1111, this setting
* is configured using I/O pins on the device.
* TODO: Make this value configurable via KConfig or DT?

2
drivers/flash/flash_ite_it8xxx2.c
View file

@ -60,7 +60,7 @@ struct flash_it8xxx2_dev_data {
/* page program command */
#define FLASH_CMD_PAGE_WRITE 0x2
/* ector erase command (erase size is 4KB) */
/* sector erase command (erase size is 4KB) */
#define FLASH_CMD_SECTOR_ERASE 0x20
/* command for flash write */
#define FLASH_CMD_WRITE FLASH_CMD_PAGE_WRITE

4
drivers/flash/flash_sam0.c
View file

@ -291,7 +291,7 @@ static int flash_sam0_write(const struct device *dev, off_t offset,
}
if ((offset % FLASH_PAGE_SIZE) != 0) {
LOG_WRN("0x%lx: not on a write block boundrary", (long)offset);
LOG_WRN("0x%lx: not on a write block boundary", (long)offset);
return -EINVAL;
}
@ -352,7 +352,7 @@ static int flash_sam0_erase(const struct device *dev, off_t offset,
}
if ((offset % ROW_SIZE) != 0) {
LOG_WRN("0x%lx: not on a page boundrary", (long)offset);
LOG_WRN("0x%lx: not on a page boundary", (long)offset);
return -EINVAL;
}

2
drivers/flash/flash_stm32.h
View file

@ -52,7 +52,7 @@ struct flash_stm32_priv {
#define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs)
/* Redefintions of flags and masks to harmonize stm32 series: */
/* Redefinitions of flags and masks to harmonize stm32 series: */
#if defined(CONFIG_SOC_SERIES_STM32G0X)
#if defined(FLASH_FLAG_BSY2)
#define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY1 | FLASH_FLAG_BSY2);

2
drivers/flash/flash_stm32f4x.c
View file

@ -38,7 +38,7 @@ static inline void flush_cache(FLASH_TypeDef *regs)
if (regs->ACR & FLASH_ACR_DCEN) {
regs->ACR &= ~FLASH_ACR_DCEN;
/* Datasheet: DCRST: Data cache reset
* This bit can be written only when thes data cache is disabled
* This bit can be written only when the data cache is disabled
*/
regs->ACR |= FLASH_ACR_DCRST;
regs->ACR &= ~FLASH_ACR_DCRST;

2
drivers/flash/flash_stm32f7x.c
View file

@ -27,7 +27,7 @@ static inline void flush_cache(FLASH_TypeDef *regs)
{
if (regs->ACR & FLASH_ACR_ARTEN) {
regs->ACR &= ~FLASH_ACR_ARTEN;
/* Refernce manual:
/* Reference manual:
* The ART cache can be flushed only if the ART accelerator
* is disabled (ARTEN = 0).
*/

2
drivers/flash/flash_stm32g4x.c
View file

@ -51,7 +51,7 @@ static inline void flush_cache(FLASH_TypeDef *regs)
if (regs->ACR & FLASH_ACR_DCEN) {
regs->ACR &= ~FLASH_ACR_DCEN;
/* Datasheet: DCRST: Data cache reset
* This bit can be written only when thes data cache is disabled
* This bit can be written only when the data cache is disabled
*/
regs->ACR |= FLASH_ACR_DCRST;
regs->ACR &= ~FLASH_ACR_DCRST;

2
drivers/flash/flash_stm32l4x.c
View file

@ -45,7 +45,7 @@ static inline void flush_cache(FLASH_TypeDef *regs)
if (regs->ACR & FLASH_ACR_DCEN) {
regs->ACR &= ~FLASH_ACR_DCEN;
/* Datasheet: DCRST: Data cache reset
* This bit can be written only when thes data cache is disabled
* This bit can be written only when the data cache is disabled
*/
regs->ACR |= FLASH_ACR_DCRST;
regs->ACR &= ~FLASH_ACR_DCRST;

8
drivers/flash/flash_stm32wbx.c
View file

@ -50,7 +50,7 @@ static inline void flush_cache(FLASH_TypeDef *regs)
if (regs->ACR & FLASH_ACR_DCEN) {
regs->ACR &= ~FLASH_ACR_DCEN;
/* Datasheet: DCRST: Data cache reset
* This bit can be written only when thes data cache is disabled
* This bit can be written only when the data cache is disabled
*/
regs->ACR |= FLASH_ACR_DCRST;
regs->ACR &= ~FLASH_ACR_DCRST;
@ -145,7 +145,7 @@ static int write_dword(const struct device *dev, off_t offset, uint64_t val)
* get/release the semaphore.
*
* However, keeping that code make it compatible with
* bothmechanisms.
* both mechanisms.
* The protection by semaphore is enabled on CPU2 side
* with the command SHCI_C2_SetFlashActivityControl()
*
@ -281,7 +281,7 @@ static int erase_page(const struct device *dev, uint32_t page)
* get/release the semaphore.
*
* However, keeping that code make it compatible with
* bothmechanisms.
* both mechanisms.
* The protection by semaphore is enabled on CPU2 side
* with the command SHCI_C2_SetFlashActivityControl()
*
@ -418,7 +418,7 @@ int flash_stm32_check_status(const struct device *dev)
error = (regs->SR & FLASH_FLAG_SR_ERRORS);
error |= (regs->ECCR & FLASH_FLAG_ECCC);
/* Clear systematic Option and Enginneering bits validity error */
/* Clear systematic Option and Engineering bits validity error */
if (error & FLASH_FLAG_OPTVERR) {
regs->SR |= FLASH_FLAG_SR_ERRORS;
return 0;

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