boards: arm64: add imx8mn board support

i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano
applications processor, composed of a quad Cortex®-A53 cluster
and a single Cortex®-M47 core.

Zephyr OS is ported to run on the Cortex®-A53 core.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>

boards/arm64/mimx8mn_evk/Kconfig.board

@@ -0,0 +1,7 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MIMX8MN_EVK_A53
+	bool "NXP i.MX8M Nano EVK A53"
+	depends on SOC_SERIES_MIMX8M_A53
+	select SOC_PART_NUMBER_MIMX8MN6DVTJZ

boards/arm64/mimx8mn_evk/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MIMX8MN_EVK_A53
+
+config BOARD
+	default "mimx8mn_evk_a53"
+
+endif # BOARD_MIMX8MN_EVK_A53

boards/arm64/mimx8mn_evk/board.cmake

@@ -0,0 +1 @@
+# SPDX-License-Identifier: Apache-2.0

boards/arm64/mimx8mn_evk/doc/index.rst

@@ -0,0 +1,131 @@
+.. _imx8mn_evk:
+
+NXP i.MX8MN EVK (Cortex-A53)
+############################
+
+Overview
+********
+
+i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano applications
+processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M47 core.
+Zephyr OS is ported to run on the Cortex®-A53 core.
+
+- Board features:
+
+  - RAM: 2GB LPDDR4
+  - Storage:
+
+    - SanDisk 16GB eMMC5.1
+    - Micron 32MB QSPI NOR
+    - microSD Socket
+  - Wireless:
+
+    - WiFi: 2.4/5GHz IEEE 802.11b/g/n
+    - Bluetooth: v4.1
+  - USB:
+
+    - OTG - 2x type C
+  - Ethernet
+  - PCI-E M.2
+  - Connectors:
+
+    - 40-Pin Dual Row Header
+  - LEDs:
+
+    - 1x Power status LED
+    - 1x UART LED
+  - Debug
+
+    - JTAG 20-pin connector
+    - MicroUSB for UART debug, two COM ports for A53 and M7
+
+More information about the board can be found at the
+`NXP website`_.
+
+Supported Features
+==================
+
+The Zephyr mimx8mn_evk board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| GIC-v3    | on-chip    | interrupt controller                |
++-----------+------------+-------------------------------------+
+| ARM TIMER | on-chip    | system clock                        |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port                         |
++-----------+------------+-------------------------------------+
+
+Devices
+========
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 8 MHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+CPU's UART4.
+
+Programming and Debugging
+*************************
+
+Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
+plug the SD card into the board. Power it up and stop the u-boot execution at
+prompt.
+
+Use U-Boot to load and kick zephyr.bin:
+
+.. code-block:: console
+
+    mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000
+
+Or kick SMP zephyr.bin:
+
+.. code-block:: console
+
+    mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu release 2 0x93c00000
+
+
+Use this configuration to run basic Zephyr applications and kernel tests,
+for example, with the :ref:`synchronization_sample`:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: mimx8mn_evk_a53
+   :goals: run
+
+This will build an image with the synchronization sample app, boot it and
+display the following ram console output:
+
+.. code-block:: console
+
+    *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883  ***
+    thread_a: Hello World from cpu 0 on mimx8mn_evk_a53!
+    thread_b: Hello World from cpu 0 on mimx8mn_evk_a53!
+    thread_a: Hello World from cpu 0 on mimx8mn_evk_a53!
+    thread_b: Hello World from cpu 0 on mimx8mn_evk_a53!
+    thread_a: Hello World from cpu 0 on mimx8mn_evk_a53!
+
+Use Jailhouse hypervisor, after root cell linux is up:
+
+.. code-block:: console
+
+    #jailhouse enable imx8mn.cell
+    #jailhouse cell create imx8mn-zephyr.cell
+    #jailhouse cell load 1 zephyr.bin -a 0x93c00000
+    #jailhouse cell start 1
+
+References
+==========
+
+.. _NXP website:
+   https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-nano-applications-processor:8MNANOD4-EVK
+
+.. _i.MX 8M Applications Processor Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=IMX8MNRM

boards/arm64/mimx8mn_evk/mimx8mn_evk-pinctrl.dtsi

@@ -0,0 +1,28 @@
+/*
+ * Copyright 2022 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <nxp/nxp_imx/mimx8mn6dvtjz-pinctrl.dtsi>
+
+&pinctrl {
+	uart2_default: uart2_default {
+		group0 {
+			pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx>,
+				<&iomuxc_uart2_txd_uart_tx_uart2_tx>;
+			slew-rate = "fast";
+			drive-strength = "40-ohm";
+		};
+	};
+
+	uart4_default: uart4_default {
+		group0 {
+			pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
+				<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
+			slew-rate = "fast";
+			drive-strength = "40-ohm";
+		};
+	};
+
+};

boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.dts

@@ -0,0 +1,44 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mimx8mn_a53.dtsi>
+#include "mimx8mn_evk-pinctrl.dtsi"
+
+/ {
+	model = "NXP i.MX8MN A53";
+	compatible = "fsl,mimx8mn";
+
+	chosen {
+		zephyr,console = &uart4;
+		zephyr,shell-uart = &uart4;
+		zephyr,sram = &sram0;
+	};
+
+	cpus {
+		cpu@0 {
+			status = "disabled";
+		};
+		cpu@1 {
+			status = "disabled";
+		};
+		cpu@2 {
+			status = "disabled";
+		};
+	};
+
+	sram0: memory@93c00000 {
+		reg = <0x93c00000 DT_SIZE_M(1)>;
+	};
+};
+
+&uart4 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart4_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};

boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.yaml

@@ -0,0 +1,12 @@
+identifier: mimx8mn_evk_a53
+name: NXP i.MX8M Nano EVK A53
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram:  1024
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_defconfig

@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# ARM Options
+CONFIG_AARCH64_IMAGE_HEADER=y
+CONFIG_ARMV8_A_NS=y
+CONFIG_ARM64_VA_BITS_40=y
+CONFIG_ARM64_PA_BITS_40=y
+
+# Cache Options
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_DCACHE_LINE_SIZE_DETECT=y
+CONFIG_ICACHE_LINE_SIZE_DETECT=y
+
+# Platform Configuration
+CONFIG_SOC_SERIES_MIMX8M_A53=y
+CONFIG_SOC_MIMX8MN_A53=y
+CONFIG_BOARD_MIMX8MN_EVK_A53=y
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_PA_BITS_48=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_CLOCK_CONTROL=y
+CONFIG_PINCTRL=y

boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.dts

@@ -0,0 +1,46 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mimx8mn_a53.dtsi>
+#include "mimx8mn_evk-pinctrl.dtsi"
+
+/ {
+	model = "NXP i.MX8MN A53";
+	compatible = "fsl,mimx8mn";
+
+	chosen {
+		zephyr,console = &uart4;
+		zephyr,shell-uart = &uart4;
+		zephyr,sram = &sram0;
+	};
+
+	cpus {
+		cpu@0 {
+			status = "disabled";
+		};
+		cpu@1 {
+			status = "disabled";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	sram0: memory@93c00000 {
+		reg = <0x93c00000 DT_SIZE_M(1)>;
+	};
+};
+
+&uart4 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart4_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};

boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.yaml

@@ -0,0 +1,12 @@
+identifier: mimx8mn_evk_a53_smp
+name: NXP i.MX8M Nano EVK A53 with SMP kernel
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram:  1024
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp_defconfig

@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# ARM Options
+CONFIG_AARCH64_IMAGE_HEADER=y
+CONFIG_ARMV8_A_NS=y
+CONFIG_ARM64_VA_BITS_40=y
+CONFIG_ARM64_PA_BITS_40=y
+
+# Cache Options
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_DCACHE_LINE_SIZE_DETECT=y
+CONFIG_ICACHE_LINE_SIZE_DETECT=y
+
+# Platform Configuration
+CONFIG_SOC_SERIES_MIMX8M_A53=y
+CONFIG_SOC_MIMX8MN_A53=y
+CONFIG_BOARD_MIMX8MN_EVK_A53=y
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_PA_BITS_48=y
+
+# SMP
+CONFIG_SMP=y
+CONFIG_MP_NUM_CPUS=2
+CONFIG_PM_CPU_OPS=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_CLOCK_CONTROL=y
+CONFIG_PINCTRL=y

dts/arm64/nxp/nxp_mimx8mn_a53.dtsi

@@ -0,0 +1,115 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <arm64/armv8-a.dtsi>
+#include <zephyr/dt-bindings/clock/imx_ccm.h>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &uart2;
+		zephyr,shell-uart = &uart2;
+		zephyr,sram = &sram0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <3>;
+		};
+
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	gic: interrupt-controller@38800000 {
+		compatible = "arm,gic";
+		reg = <0x38800000 0x10000>, /* GIC Dist */
+		      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		status = "okay";
+	};
+
+	iomuxc: iomuxc@30330000 {
+		compatible = "nxp,imx-iomuxc";
+		reg = <0x30330000 DT_SIZE_K(64)>;
+		status = "okay";
+		pinctrl: pinctrl {
+			status = "okay";
+			compatible = "nxp,imx8m-pinctrl";
+		};
+	};
+
+	ana_pll: ana_pll@30360000 {
+		compatible = "nxp,imx-ana";
+		reg = <0x30360000 DT_SIZE_K(64)>;
+	};
+
+	ccm: ccm@30380000 {
+		compatible = "nxp,imx-ccm";
+		reg = <0x30380000 DT_SIZE_K(64)>;
+		#clock-cells = <3>;
+	};
+
+	uart2: serial@30890000 {
+		compatible = "nxp,imx-iuart";
+		reg = <0x30890000 DT_SIZE_K(64)>;
+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>;
+		status = "disabled";
+	};
+
+	uart4: serial@30a60000 {
+		compatible = "nxp,imx-iuart";
+		reg = <0x30a60000 DT_SIZE_K(64)>;
+		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
+		status = "disabled";
+	};
+};

soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mn

@@ -0,0 +1,30 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MIMX8MN_A53
+
+config SOC
+	default "mimx8mn6"
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_FLASH := zephyr,flash
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+config NUM_IRQS
+	int
+	default 240
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 8000000
+
+config PINCTRL_IMX
+	default y if HAS_MCUX_IOMUXC
+	depends on PINCTRL
+
+endif

soc/arm64/nxp_imx/mimx8m/Kconfig.soc

@@ -25,6 +25,16 @@ config SOC_MIMX8MP_A53
 	select HAS_MCUX_CCM if CLOCK_CONTROL
 	select HAS_MCUX_IOMUXC if PINCTRL
 
+config SOC_MIMX8MN_A53
+	bool "NXP i.MX8MN A53"
+	select ARM64
+	select CPU_CORTEX_A53
+	select ARM_ARCH_TIMER
+	select GIC_V3
+	select HAS_MCUX if CLOCK_CONTROL
+	select HAS_MCUX_CCM if CLOCK_CONTROL
+	select HAS_MCUX_IOMUXC if PINCTRL
+
 endchoice
 
 config SOC_PART_NUMBER_MIMX8ML8DVNLZ
@@ -53,6 +63,34 @@ config SOC_PART_NUMBER_MIMX8MM_A53
 	  that you should not set directly. The part number selection choice defines
 	  the default value for this string.
 
+if SOC_MIMX8MN_A53
+
+config SOC_PART_NUMBER_MIMX8MN6DVTJZ
+	bool
+
+config SOC_PART_NUMBER_MIMX8MN6DUCJZ
+	bool
+
+config SOC_PART_NUMBER_MIMX8MN6CVTIZ
+	bool
+
+config SOC_PART_NUMBER_MIMX8MN6CUCIZ
+	bool
+
+config SOC_PART_NUMBER_MIMX8MN_A53
+	string
+	default "MIMX8MN6DVTJZ_ca53" if  SOC_PART_NUMBER_MIMX8MN6DVTJZ
+	default "MIMX8MN6DUCJZ_ca53" if  SOC_PART_NUMBER_MIMX8MN6DUCJZ
+	default "MIMX8MN6CVTIZ_ca53" if  SOC_PART_NUMBER_MIMX8MN6CVTIZ
+	default "MIMX8MN6CUCIZ_ca53" if  SOC_PART_NUMBER_MIMX8MN6CUCIZ
+	help
+	  This string holds the full part number of the SoC. It is a hidden option
+	  that you should not set directly. The part number selection choice defines
+	  the default value for this string.
+
+endif # SOC_MIMX8MN_A53
+
 config SOC_PART_NUMBER
 	default SOC_PART_NUMBER_MIMX8MP_A53 if SOC_MIMX8MP_A53
 	default SOC_PART_NUMBER_MIMX8MM_A53 if SOC_MIMX8MM_A53
+	default SOC_PART_NUMBER_MIMX8MN_A53 if SOC_MIMX8MN_A53