board: arm64: Add FVP BaseR AEMv8R board

Add essential files to create a new board. Enable arch timer, uart,
multi-threading. Set memory map for flash and sram. The new board name
is fvp_baser_aemv8r with the fvp_aemv8r_aarch64 soc.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>

CODEOWNERS

@@ -150,6 +150,7 @@
 /boards/arm64/bcm958402m2_a72/            @abhishek-brcm
 /boards/arm64/nxp_ls1046ardb/             @JiafeiPan
 /boards/arm64/xenvm/                      @lorc
+/boards/arm64/fvp_baser_aemv8r/           @povergoing
 # All cmake related files
 /cmake/                                   @tejlmand @nashif
 /cmake/*/arcmwdt/                         @abrodkin @evgeniy-paltsev @tejlmand

boards/arm64/fvp_baser_aemv8r/Kconfig.board

@@ -0,0 +1,6 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FVP_BASER_AEMV8R
+	bool "FVP BaseR AEMv8R simulation board"
+	depends on SOC_FVP_AEMV8R_AARCH64

boards/arm64/fvp_baser_aemv8r/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_FVP_BASER_AEMV8R
+
+config BUILD_OUTPUT_BIN
+	default y
+
+config BOARD
+	default "fvp_baser_aemv8r"
+
+endif # BOARD_FVP_BASER_AEMV8R

boards/arm64/fvp_baser_aemv8r/board.cmake

@@ -0,0 +1,21 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+set(EMU_PLATFORM armfvp)
+set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R)
+
+set(ARMFVP_FLAGS
+  -C cluster0.has_aarch64=1
+  -C cluster0.VMSA_supported=0
+  -C cluster0.NUM_CORES=1
+  -C bp.dram.enable_atomic_ops=1
+  -C bp.sram.enable_atomic_ops=1
+  -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
+  -C gic_distributor.has-two-security-states=0
+  -C bp.refcounter.non_arch_start_at_default=1
+  -C bp.pl011_uart0.out_file=-
+  -C bp.pl011_uart0.unbuffered_output=1
+  -C bp.terminal_0.start_telnet=0
+  -C bp.vis.disable_visualisation=1
+  -C bp.vis.rate_limit-enable=0
+  )

boards/arm64/fvp_baser_aemv8r/doc/index.rst

@@ -0,0 +1,89 @@
+.. _fvp_baser_aemv8r:
+
+ARM AEMv8R Fixed Virtual Platforms
+##################################
+
+Overview
+********
+
+This board configuration will use ARM Fixed Virtual Platforms(FVP) to emulate
+a generic Armv8-R 64-bit hardware platform.
+
+This configuration provides support for a generic Armv8-R 64-bit CPU and
+these devices:
+
+* GICv3 interrupt controller
+* ARM architected (Generic) timer
+* PL011 UART controller
+
+Hardware
+********
+
+Supported Features
+==================
+
+The following hardware features are supported:
+
++-----------------------+------------+----------------------+
+| Interface             | Controller | Driver/Component     |
++=======================+============+======================+
+| GICv3                 | on-chip    | interrupt controller |
++-----------------------+------------+----------------------+
+| PL011 UART            | on-chip    | serial port          |
++-----------------------+------------+----------------------+
+| ARM GENERIC TIMER     | on-chip    | system clock         |
++-----------------------+------------+----------------------+
+
+The kernel currently does not support other hardware features on this platform.
+
+Devices
+========
+
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 100 MHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+UART0.
+
+Known Problems or Limitations
+==============================
+
+Programming and Debugging
+*************************
+
+Use this configuration to build basic Zephyr applications and kernel tests in the
+ARM FVP emulated environment, for example, with the :ref:`synchronization_sample`:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: fvp_baser_aemv8r
+   :goals: build
+
+This will build an image with the synchronization sample app.
+
+Run with FVP:
+Set env ARMFVP_BIN_PATH before using it,
+e.g. export ARMFVP_BIN_PATH=<path/to/fvp/dir>
+NOTE: ARMFVP_BIN_PATH is the dir path.
+ninja run or west build -t run
+
+Debugging
+=========
+
+Refer to the detailed overview about :ref:`application_debugging`.
+
+Networking
+==========
+
+References
+**********
+
+1. Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch64 architecture profile
+2. AArch64 Exception and Interrupt Handling
+3. https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms

boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts

@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+#include <arm64/armv8-r.dtsi>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "FVP BaseR AEMv8R";
+
+	chosen {
+		/*
+		 * The SRAM node is actually located in the
+		 * DRAM region of the FVP BaseR AEMv8R.
+		 */
+		zephyr,sram = &dram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r82";
+			reg = <0>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+		label = "arch_timer";
+	};
+
+	uartclk: apb-pclk {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@af000000 {
+			compatible = "arm,gic";
+			reg = <0xaf000000 0x1000>,
+			      <0xaf100000 0x100>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			label = "GIC";
+			status = "okay";
+		};
+
+		uart0: uart@9c090000 {
+			compatible = "arm,pl011";
+			reg = <0x9c090000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 1 0 IRQ_TYPE_LEVEL>;
+			interrupt-names = "irq_0";
+			label = "UART_0";
+			clocks = <&uartclk>;
+		};
+
+		flash0: flash@0 {
+			compatible = "soc-nv-flash";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		dram0: memory@10000000 {
+			compatible = "mmio-dram";
+			reg = <0x10000000 DT_SIZE_K(2048)>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+};

boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.yaml

@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: fvp_baser_aemv8r
+name: FVP Emulation FVP_BaseR_AEMv8R
+arch: arm64
+type: sim
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 2048
+flash: 64
+testing:
+  default: true

boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_defconfig

@@ -0,0 +1,28 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_FVP_AEMV8R=y
+CONFIG_SOC_FVP_AEMV8R_AARCH64=y
+CONFIG_BOARD_FVP_BASER_AEMV8R=y
+
+CONFIG_XIP=n
+
+CONFIG_ISR_STACK_SIZE=1024
+CONFIG_THREAD_STACK_INFO=y
+
+# Enable Timer and Sys clock
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_SYS_CLOCK_EXISTS=y
+CONFIG_MULTITHREADING=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable serial port
+CONFIG_UART_PL011=y
+CONFIG_UART_PL011_PORT0=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y