boards: mimxrt1060_evk: Enable lpuart3 for bluetooth hci

Enables instance 3 of the lpuart driver and configures pinmuxes to use
bluetooth hci on the mimxrt1060_evk board. Updates board documentation
accordingly.

Tested with samples/bluetooth/peripheral_hr, with frdm_kw41z attached as
an arduino shield running the nxp hci controller application.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2019-01-14 15:17:07 -06:00
parent 2ec2ac16d5
commit 9a165c9460
4 changed files with 27 additions and 1 deletions

View file

@ -26,6 +26,9 @@ if UART_MCUX_LPUART
config UART_MCUX_LPUART_1
default y
config UART_MCUX_LPUART_3
default y if BT_UART
endif # UART_MCUX_LPUART
endif # BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVK_HYPERFLASH

View file

@ -118,6 +118,10 @@ The MIMXRT1060 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_13 | LPUART1_RX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI |
+---------------+-----------------+---------------------------+
| WAKEUP | GPIO | SW0 |
+---------------+-----------------+---------------------------+
@ -130,7 +134,8 @@ board with the on-chip PLL to generate a 600 MHz core clock.
Serial Port
===========
The MIMXRT1060 SoC has eight UARTs. One is configured for the console and the
The MIMXRT1060 SoC has eight UARTs. ``LPUART1`` is configured for the console,
``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the
remaining are not used.
Programming and Debugging

View file

@ -57,6 +57,8 @@
};
};
arduino_serial: &uart3 {};
&flexspi0 {
reg = <0x402a8000 0x4000>, <0x60000000 0x800000>;
is25wp064: is25wp064@0 {

View file

@ -41,6 +41,22 @@ static int mimxrt1060_evk_init(struct device *dev)
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
#ifdef CONFIG_UART_MCUX_LPUART_3
/* LPUART3 TX/RX */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
return 0;
}