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driver: clock-control: st: allow PLL1Q support for G0 and WL

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LL name for PLL1Q is not the same across STM32G0, STM32WL, STM32H5 and
STM32H7 families. This allows to choose the proper definition depending on
the family.

Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
This commit is contained in:
Johan Lafon 2023-07-21 09:48:33 +02:00 committed by Fabio Baltieri
parent 34584c9e0c
commit 9c69368b1d
1 changed files with 7 additions and 1 deletions
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8
drivers/clock_control/clock_stm32_ll_mco.h
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@ -31,7 +31,13 @@
#elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLCLK
#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLCLK
#elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLQCLK
#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLL1QCLK
#if (CONFIG_SOC_SERIES_STM32G0X || CONFIG_SOC_SERIES_STM32WLX)
#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLQCLK
#elif (CONFIG_SOC_SERIES_STM32H5X || CONFIG_SOC_SERIES_STM32H7X)
#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLL1QCLK
#else
#error "PLLQCLK is not a valid clock source on your SOC"
#endif
#elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLCLK_DIV2
#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
#elif CONFIG_CLOCK_STM32_MCO1_SRC_PLL2CLK