diff --git a/CODEOWNERS b/CODEOWNERS index ef5f8a01c2..7a19b09979 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -208,6 +208,7 @@ /drivers/pcie/ @andrewboie /drivers/pinmux/stm32/ @idlethread /drivers/pinmux/*hsdk* @iriszzw +/drivers/pinmux/*npcx* @MulinChao /drivers/pwm/*litex* @mateusz-holenko @kgugala @pgielda /drivers/pwm/*sam0* @nzmichaelh /drivers/sensor/ @MaureenHelm diff --git a/drivers/pinmux/CMakeLists.txt b/drivers/pinmux/CMakeLists.txt index 73cf012be9..fe09448d5a 100644 --- a/drivers/pinmux/CMakeLists.txt +++ b/drivers/pinmux/CMakeLists.txt @@ -8,6 +8,7 @@ zephyr_sources_ifdef(CONFIG_PINMUX_INTEL_S1000 pinmux_intel_s1000.c) zephyr_sources_ifdef(CONFIG_PINMUX_LPC11U6X pinmux_lpc11u6x.c) zephyr_sources_ifdef(CONFIG_PINMUX_MCUX pinmux_mcux.c) zephyr_sources_ifdef(CONFIG_PINMUX_MCUX_LPC pinmux_mcux_lpc.c) +zephyr_sources_ifdef(CONFIG_PINMUX_NPCX pinmux_npcx.c) zephyr_sources_ifdef(CONFIG_PINMUX_RV32M1 pinmux_rv32m1.c) zephyr_sources_ifdef(CONFIG_PINMUX_SAM0 pinmux_sam0.c) zephyr_sources_ifdef(CONFIG_PINMUX_SIFIVE pinmux_sifive.c) diff --git a/drivers/pinmux/Kconfig b/drivers/pinmux/Kconfig index c4a9bee453..8e36efa7b0 100644 --- a/drivers/pinmux/Kconfig +++ b/drivers/pinmux/Kconfig @@ -56,4 +56,6 @@ source "drivers/pinmux/Kconfig.stm32" source "drivers/pinmux/Kconfig.xec" +source "drivers/pinmux/Kconfig.npcx" + endif # PINMUX diff --git a/drivers/pinmux/Kconfig.npcx b/drivers/pinmux/Kconfig.npcx new file mode 100644 index 0000000000..ed45b7e504 --- /dev/null +++ b/drivers/pinmux/Kconfig.npcx @@ -0,0 +1,12 @@ +# NPCX PINMUX driver configuration options + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config PINMUX_NPCX + bool "Nuvoton NPCX embedd controller (EC) pinmux driver" + depends on SOC_FAMILY_NPCX + help + This option enables the pin-mux driver for NPCX family + of processors. + Say y if you wish to use pin-mux module on NPCX MCU. diff --git a/drivers/pinmux/pinmux_npcx.c b/drivers/pinmux/pinmux_npcx.c new file mode 100644 index 0000000000..722e1050bc --- /dev/null +++ b/drivers/pinmux/pinmux_npcx.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2020 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include +LOG_MODULE_REGISTER(pimux_npcx, LOG_LEVEL_ERR); + +/* Driver config */ +struct npcx_pinctrl_config { + /* scfg device base address */ + uint32_t base; +}; + +/* Default io list which default functionality are not IOs */ +#define DT_DRV_COMPAT nuvoton_npcx_pinctrl_def +static const struct npcx_alt def_alts[] = DT_NPCX_ALT_ITEMS_LIST(0); + +static const struct npcx_pinctrl_config npcx_pinctrl_cfg = { + .base = DT_REG_ADDR(DT_NODELABEL(scfg)), +}; + +/* Driver convenience defines */ +#define DRV_CONFIG(dev) \ + ((const struct npcx_pinctrl_config *)(dev)->config) + +#define HAL_INSTANCE(dev) \ + (struct scfg_reg_t *)(DRV_CONFIG(dev)->base) + +/* Pin-control local functions */ +static void npcx_pinctrl_alt_sel(const struct npcx_alt *alt, int alt_func) +{ + uint32_t scfg_base = npcx_pinctrl_cfg.base; + uint8_t alt_mask = BIT(alt->bit); + + /* + * alt_fun == 0 means select GPIO, otherwise Alternate Func. + * inverted == 0: + * Set devalt bit to select Alternate Func. + * inverted == 1: + * Clear devalt bit to select Alternate Func. + */ + if (!!alt_func != !!alt->inverted) + NPCX_DEVALT(scfg_base, alt->group) |= alt_mask; + else + NPCX_DEVALT(scfg_base, alt->group) &= ~alt_mask; +} + +/* Soc specific pin-control functions */ +void soc_pinctrl_mux_configure(const struct npcx_alt *alts_list, + uint8_t alts_size, int altfunc) +{ + int i; + + for (i = 0; i < alts_size; i++, alts_list++) { + npcx_pinctrl_alt_sel(alts_list, altfunc); + } +} + +/* Pin-control driver registration */ +static int npcx_pinctrl_init(struct device *dev) +{ + struct scfg_reg_t *inst = HAL_INSTANCE(dev); + +#if defined(CONFIG_SOC_SERIES_NPCX7) + /* + * Set bit 7 of DEVCNT again for npcx7 series. Please see Errata + * for more information. It will be fixed in next chip. + */ + inst->DEVCNT |= BIT(7); +#endif + + /* Change all pads whose default functionality isn't IO to GPIO */ + soc_pinctrl_mux_configure(def_alts, ARRAY_SIZE(def_alts), 0); + + return 0; +} + +DEVICE_AND_API_INIT(npcx_pinctrl, + DT_LABEL(DT_NODELABEL(scfg)), + &npcx_pinctrl_init, + NULL, &npcx_pinctrl_cfg, + PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, + NULL); diff --git a/dts/arm/nuvoton/npcx/npcx7-alts-map.dtsi b/dts/arm/nuvoton/npcx/npcx7-alts-map.dtsi new file mode 100644 index 0000000000..0923b2b328 --- /dev/null +++ b/dts/arm/nuvoton/npcx/npcx7-alts-map.dtsi @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2020 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + npcx7_alts_map { + compatible = "nuvoton,npcx-pinctrl-conf"; + + /******** SCFG device alternative table *******/ + /* SCFG DEVALT 0 */ + alt0_spip_sl: alt00 { alts = <&scfg 0x00 0x0 0>; }; + alt0_gpio_no_spip: alt03_inv { alts = <&scfg 0x00 0x3 1>; }; + + /* SCFG DEVALT 1 */ + alt1_kbrst_sl: alt10 { alts = <&scfg 0x01 0x0 0>; }; + alt1_a20m_sl: alt11 { alts = <&scfg 0x01 0x1 0>; }; + alt1_smi_sl: alt12 { alts = <&scfg 0x01 0x2 0>; }; + alt1_ec_sci_sl: alt13 { alts = <&scfg 0x01 0x3 0>; }; + alt1_no_pwrgd: alt14_inv { alts = <&scfg 0x01 0x4 1>; }; + alt1_pwroff: alt15 { alts = <&scfg 0x01 0x5 0>; }; + alt1_clkrn_sl: alt16 { alts = <&scfg 0x01 0x6 0>; }; + alt1_no_lpc_espi: alt17_inv { alts = <&scfg 0x01 0x7 1>; }; + + /* SCFG DEVALT 2 */ + alt2_i2c0_0_sl: alt20 { alts = <&scfg 0x02 0x0 0>; }; + alt2_i2c7_0_sl: alt21 { alts = <&scfg 0x02 0x1 0>; }; + alt2_i2c1_0_sl: alt22 { alts = <&scfg 0x02 0x2 0>; }; + alt2_i2c6_0_sl: alt23 { alts = <&scfg 0x02 0x3 0>; }; + alt2_i2c2_0_sl: alt24 { alts = <&scfg 0x02 0x4 0>; }; + alt2_i2c5_0_sl: alt25 { alts = <&scfg 0x02 0x5 0>; }; + alt2_i2c3_0_sl: alt26 { alts = <&scfg 0x02 0x6 0>; }; + + /* SCFG DEVALT 3 */ + alt3_ps2_0_sl: alt30 { alts = <&scfg 0x03 0x0 0>; }; + alt3_ps2_1_sl: alt31 { alts = <&scfg 0x03 0x1 0>; }; + alt3_ps2_2_sl: alt32 { alts = <&scfg 0x03 0x2 0>; }; + alt3_ta1_sl1: alt34 { alts = <&scfg 0x03 0x4 0>; }; + alt3_tb1_sl1: alt35 { alts = <&scfg 0x03 0x5 0>; }; + alt3_ta2_sl1: alt36 { alts = <&scfg 0x03 0x6 0>; }; + + /* SCFG DEVALT 4 */ + alt4_pwm0_sl: alt40 { alts = <&scfg 0x04 0x0 0>; }; + alt4_pwm1_sl: alt41 { alts = <&scfg 0x04 0x1 0>; }; + alt4_pwm2_sl: alt42 { alts = <&scfg 0x04 0x2 0>; }; + alt4_pwm3_sl: alt43 { alts = <&scfg 0x04 0x3 0>; }; + alt4_pwm4_sl: alt44 { alts = <&scfg 0x04 0x4 0>; }; + alt4_pwm5_sl: alt45 { alts = <&scfg 0x04 0x5 0>; }; + alt4_pwm6_sl: alt46 { alts = <&scfg 0x04 0x6 0>; }; + alt4_pwm7_sl: alt47 { alts = <&scfg 0x04 0x7 0>; }; + + /* SCFG DEVALT 5 */ + alt5_trace_en: alt50 { alts = <&scfg 0x05 0x0 0>; }; + alt5_njen1_en: alt51 { alts = <&scfg 0x05 0x1 0>; }; + alt5_njen0_en: alt52 { alts = <&scfg 0x05 0x2 0>; }; + alt5_strace_en: alt54 { alts = <&scfg 0x05 0x4 0>; }; + + /* SCFG DEVALT 6 */ + alt6_adc0_sl: alt60 { alts = <&scfg 0x06 0x0 0>; }; + alt6_adc1_sl: alt61 { alts = <&scfg 0x06 0x1 0>; }; + alt6_adc2_sl: alt62 { alts = <&scfg 0x06 0x2 0>; }; + alt6_adc3_sl: alt63 { alts = <&scfg 0x06 0x3 0>; }; + alt6_adc4_sl: alt64 { alts = <&scfg 0x06 0x4 0>; }; + alt6_i2c6_1_sl: alt65 { alts = <&scfg 0x06 0x5 0>; }; + alt6_i2c5_1_sl: alt66 { alts = <&scfg 0x06 0x6 0>; }; + alt6_i2c4_1_sl: alt67 { alts = <&scfg 0x06 0x7 0>; }; + + /* SCFG DEVALT 7 */ + alt7_no_ksi0_sl: alt70_inv { alts = <&scfg 0x07 0x0 1>; }; + alt7_no_ksi1_sl: alt71_inv { alts = <&scfg 0x07 0x1 1>; }; + alt7_no_ksi2_sl: alt72_inv { alts = <&scfg 0x07 0x2 1>; }; + alt7_no_ksi3_sl: alt73_inv { alts = <&scfg 0x07 0x3 1>; }; + alt7_no_ksi4_sl: alt74_inv { alts = <&scfg 0x07 0x4 1>; }; + alt7_no_ksi5_sl: alt75_inv { alts = <&scfg 0x07 0x5 1>; }; + alt7_no_ksi6_sl: alt76_inv { alts = <&scfg 0x07 0x6 1>; }; + alt7_no_ksi7_sl: alt77_inv { alts = <&scfg 0x07 0x7 1>; }; + + /* SCFG DEVALT 8 */ + alt8_no_kso00_sl: alt80_inv { alts = <&scfg 0x08 0x0 1>; }; + alt8_no_kso01_sl: alt81_inv { alts = <&scfg 0x08 0x1 1>; }; + alt8_no_kso02_sl: alt82_inv { alts = <&scfg 0x08 0x2 1>; }; + alt8_no_kso03_sl: alt83_inv { alts = <&scfg 0x08 0x3 1>; }; + alt8_no_kso04_sl: alt84_inv { alts = <&scfg 0x08 0x4 1>; }; + alt8_no_kso05_sl: alt85_inv { alts = <&scfg 0x08 0x5 1>; }; + alt8_no_kso06_sl: alt86_inv { alts = <&scfg 0x08 0x6 1>; }; + alt8_no_kso07_sl: alt87_inv { alts = <&scfg 0x08 0x7 1>; }; + + /* SCFG DEVALT 9 */ + alt9_no_kso08_sl: alt90_inv { alts = <&scfg 0x09 0x0 1>; }; + alt9_no_kso09_sl: alt91_inv { alts = <&scfg 0x09 0x1 1>; }; + alt9_no_kso10_sl: alt92_inv { alts = <&scfg 0x09 0x2 1>; }; + alt9_no_kso11_sl: alt93_inv { alts = <&scfg 0x09 0x3 1>; }; + alt9_no_kso12_sl: alt94_inv { alts = <&scfg 0x09 0x4 1>; }; + alt9_no_kso13_sl: alt95_inv { alts = <&scfg 0x09 0x5 1>; }; + alt9_no_kso14_sl: alt96_inv { alts = <&scfg 0x09 0x6 1>; }; + alt9_no_kso15_sl: alt97_inv { alts = <&scfg 0x09 0x7 1>; }; + + /* SCFG DEVALT A */ + alta_no_kso16_sl: alta0_inv { alts = <&scfg 0x0A 0x0 1>; }; + alta_no_kso17_sl: alta1_inv { alts = <&scfg 0x0A 0x1 1>; }; + alta_32k_out_sl: alta2 { alts = <&scfg 0x0A 0x2 0>; }; + alta_32kclkin_sl: alta3 { alts = <&scfg 0x0A 0x3 0>; }; + alta_no_vcc1_rst: alta4_inv { alts = <&scfg 0x0A 0x4 1>; }; + alta_uart2_sl: alta5 { alts = <&scfg 0x0A 0x5 0>; }; + alta_no_peci_en: alta6_inv { alts = <&scfg 0x0A 0x6 1>; }; + alta_uart1_sl1: alta7 { alts = <&scfg 0x0A 0x7 0>; }; + + /* SCFG DEVALT B */ + altb_rxd_sl: altb0 { alts = <&scfg 0x0B 0x0 0>; }; + altb_txd_sl: altb1 { alts = <&scfg 0x0B 0x1 0>; }; + altb_rts_sl: altb2 { alts = <&scfg 0x0B 0x2 0>; }; + altb_cts_sl: altb3 { alts = <&scfg 0x0B 0x3 0>; }; + altb_ri_sl: altb4 { alts = <&scfg 0x0B 0x4 0>; }; + altb_dtr_bout_sl: altb5 { alts = <&scfg 0x0B 0x5 0>; }; + altb_dcd_sl: altb6 { alts = <&scfg 0x0B 0x6 0>; }; + altb_dsr_sl: altb7 { alts = <&scfg 0x0B 0x7 0>; }; + + /* SCFG DEVALT C */ + altc_uart1_sl2: altc0 { alts = <&scfg 0x0C 0x0 0>; }; + altc_shi_sl: altc1 { alts = <&scfg 0x0C 0x1 0>; }; + altc_ps2_3_sl2: altc3 { alts = <&scfg 0x0C 0x3 0>; }; + altc_ta1_sl2: altc4 { alts = <&scfg 0x0C 0x4 0>; }; + altc_tb1_sl2: altc5 { alts = <&scfg 0x0C 0x5 0>; }; + altc_ta2_sl2: altc6 { alts = <&scfg 0x0C 0x6 0>; }; + altc_tb2_sl2: altc7 { alts = <&scfg 0x0C 0x7 0>; }; + + /* SCFG DEVALT D */ + altd_psl_in1_ahi: altd0 { alts = <&scfg 0x0D 0x0 0>; }; + altd_npsl_in1_sl: altd1 { alts = <&scfg 0x0D 0x1 0>; }; + altd_psl_in2_ahi: altd2 { alts = <&scfg 0x0D 0x2 0>; }; + altd_npsl_in2_sl: altd3 { alts = <&scfg 0x0D 0x3 0>; }; + altd_psl_in3_ahi: altd4 { alts = <&scfg 0x0D 0x4 0>; }; + altd_psl_in3_sl: altd5 { alts = <&scfg 0x0D 0x5 0>; }; + altd_psl_in4_ahi: altd6 { alts = <&scfg 0x0D 0x6 0>; }; + altd_psl_in4_sl: altd7 { alts = <&scfg 0x0D 0x7 0>; }; + + /* SCFG DEVALT E */ + alte_wov_sl: alte0 { alts = <&scfg 0x0E 0x0 0>; }; + alte_i2s_sl: alte1 { alts = <&scfg 0x0E 0x1 0>; }; + alte_dmclk_fast: alte2 { alts = <&scfg 0x0E 0x2 0>; }; + + /* SCFG DEVALT F */ + altf_adc5_sl: altf0 { alts = <&scfg 0x0F 0x0 0>; }; + altf_adc6_sl: altf1 { alts = <&scfg 0x0F 0x1 0>; }; + altf_adc7_sl: altf2 { alts = <&scfg 0x0F 0x2 0>; }; + altf_adc8_sl: altf3 { alts = <&scfg 0x0F 0x3 0>; }; + altf_adc9_sl: altf4 { alts = <&scfg 0x0F 0x4 0>; }; + altf_f_shi_new: altf7 { alts = <&scfg 0x0F 0x7 0>; }; + }; +}; diff --git a/dts/arm/nuvoton/npcx7m6fb.dtsi b/dts/arm/nuvoton/npcx7m6fb.dtsi index 0b0c0ec366..a5075af388 100644 --- a/dts/arm/nuvoton/npcx7m6fb.dtsi +++ b/dts/arm/nuvoton/npcx7m6fb.dtsi @@ -8,6 +8,9 @@ /* Macros for device tree declarations */ #include +/* NPCX7 series pinmux mapping table */ +#include "npcx/npcx7-alts-map.dtsi" + / { cpus { #address-cells = <1>; @@ -28,7 +31,15 @@ compatible = "mmio-sram"; reg = <0x200C0000 0x10000>; }; - + + def_io_conf: def_io_conf_list { + compatible = "nuvoton,npcx-pinctrl-def"; + pinctrl = <&alt0_gpio_no_spip + &alt1_no_pwrgd + &alt1_no_lpc_espi + &alta_no_peci_en>; + }; + soc { pcc: clock-controller@4000d000 { compatible = "nuvoton,npcx-pcc"; @@ -41,6 +52,14 @@ reg-names = "pmc", "cdcg"; label = "PMC_CDCG"; }; + + scfg: pin-controller@400c3000 { + compatible = "nuvoton,npcx-pinctrl"; + reg = <0x400c3000 0x2000>; + #alt-cells = <3>; + #lvol-cells = <2>; + label = "SCFG"; + }; }; }; diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-conf.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-conf.yaml new file mode 100644 index 0000000000..59cfeb00ed --- /dev/null +++ b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-conf.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +description: Nuvoton NPCX7 Pin-Mux Configuration + Configuration map from Nuvoton NPCX GPIO to pinmux controller + (SCFG) driver instances. + +compatible: "nuvoton,npcx-pinctrl-conf" +child-binding: + description: NPCX Pinmux configuration child node + properties: + alts: + type: phandle-array + required: true + description: A SCFG ALT (Alternative controllers) specifier for pinmuxing of npcx ec diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-def.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-def.yaml new file mode 100644 index 0000000000..f13690346d --- /dev/null +++ b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-def.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +description: Nuvoton, NPCX Default Pins Configurations + +compatible: "nuvoton,npcx-pinctrl-def" + +include: [base.yaml] + +properties: + pinctrl: + type: phandles + required: true + description: list of configurations of pinmux controllers need to set diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl.yaml new file mode 100644 index 0000000000..d1dabc6d0c --- /dev/null +++ b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl.yaml @@ -0,0 +1,28 @@ +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +description: Nuvoton, NPCX Pin-Controller (Pinmux, 1.8V support and so on) node + +compatible: "nuvoton,npcx-pinctrl" + +include: [base.yaml] + +properties: + reg: + required: true + + "#alt-cells": + type: int + required: true + description: Number of items to expect in a SCFG ALT (Alternative controllers) specifier + + "#lvol-cells": + type: int + required: false + const: 2 + description: Number of items to expect in a SCFG LV_GPIO_CTL (Low level IO controllers) specifier + +alt-cells: + - group + - bit + - inv diff --git a/soc/arm/nuvoton_npcx/common/reg/reg_def.h b/soc/arm/nuvoton_npcx/common/reg/reg_def.h index 4a8b0f5178..6e4a96fb7c 100644 --- a/soc/arm/nuvoton_npcx/common/reg/reg_def.h +++ b/soc/arm/nuvoton_npcx/common/reg/reg_def.h @@ -118,6 +118,70 @@ struct pmc_reg_t { #define NPCX_ENIDL_CTL_PECI_ENI 2 #define NPCX_ENIDL_CTL_ADC_ACC_DIS 1 +/* + * System Configuration (SCFG) device registers + */ +struct scfg_reg_t { + /* 0x000: Device Control */ + volatile uint8_t DEVCNT; + /* 0x001: Straps Status */ + volatile uint8_t STRPST; + /* 0x002: Reset Control and Status */ + volatile uint8_t RSTCTL; + volatile uint8_t reserved1[3]; + /* 0x006: Device Control 4 */ + volatile uint8_t DEV_CTL4; + volatile uint8_t reserved2[9]; + /* 0x010 - 1F: Device Alternate Function 0 - F */ + volatile uint8_t DEVALT0[16]; + volatile uint8_t reserved3[6]; + /* 0x026: Low-Voltage GPIO Pins Control 5 */ + volatile uint8_t LV_GPIO_CTL5[1]; + volatile uint8_t reserved4; + /* 0x028: Pull-Up/Pull-Down Enable 0 */ + volatile uint8_t PUPD_EN0; + /* 0x029: Pull-Up/Pull-Down Enable 1 */ + volatile uint8_t PUPD_EN1; + /* 0x02A - 2E: Low-Voltage GPIO Pins Control 0 - 4 */ + volatile uint8_t LV_GPIO_CTL0[5]; +}; + +/* SCFG multi-registers */ +#define NPCX_DEVALT_OFFSET(n) (0x010 + (n)) +#define NPCX_DEVALT(base, n) (*(volatile uint8_t *)(base + \ + NPCX_DEVALT_OFFSET(n))) + +#define NPCX_LV_GPIO_CTL_OFFSET(n) (((n) < 5) ? (0x02A + (n)) \ + : (0x026 + (n - 5))) +#define NPCX_LV_GPIO_CTL(base, n) (*(volatile uint8_t *)(base + \ + NPCX_LV_GPIO_CTL_OFFSET(n))) + +/* SCFG register fields */ +#define NPCX_DEVCNT_F_SPI_TRIS 6 +#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) +#define NPCX_DEVCNT_JEN1_HEN 5 +#define NPCX_DEVCNT_JEN0_HEN 4 +#define NPCX_STRPST_TRIST 1 +#define NPCX_STRPST_TEST 2 +#define NPCX_STRPST_JEN1 4 +#define NPCX_STRPST_JEN0 5 +#define NPCX_STRPST_SPI_COMP 7 +#define NPCX_RSTCTL_VCC1_RST_STS 0 +#define NPCX_RSTCTL_DBGRST_STS 1 +#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3 +#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5 +#define NPCX_RSTCTL_HIPRST_MODE 6 +#define NPCX_DEV_CTL4_F_SPI_SLLK 2 +#define NPCX_DEV_CTL4_SPI_SP_SEL 4 +#define NPCX_DEV_CTL4_WP_IF 5 +#define NPCX_DEV_CTL4_VCC1_RST_LK 6 +#define NPCX_DEVPU0_I2C0_0_PUE 0 +#define NPCX_DEVPU0_I2C0_1_PUE 1 +#define NPCX_DEVPU0_I2C1_0_PUE 2 +#define NPCX_DEVPU0_I2C2_0_PUE 4 +#define NPCX_DEVPU0_I2C3_0_PUE 6 +#define NPCX_DEVPU1_F_SPI_PUD_EN 7 + #endif /* _NUVOTON_NPCX_REG_DEF_H */ diff --git a/soc/arm/nuvoton_npcx/common/soc_dt.h b/soc/arm/nuvoton_npcx/common/soc_dt.h index 8724327bd4..eac6397240 100644 --- a/soc/arm/nuvoton_npcx/common/soc_dt.h +++ b/soc/arm/nuvoton_npcx/common/soc_dt.h @@ -18,4 +18,29 @@ .bit = DT_PHA(DT_DRV_INST(inst), clocks, bit), \ } +/* Get phandle from "pinctrl" prop which type is 'phandles' at index 'i' */ +#define DT_PHANDLE_FROM_PINCTRL(inst, i) \ + DT_INST_PHANDLE_BY_IDX(inst, pinctrl, i) + +/* Construct a npcx_alt structure from pinctrl property at index 'i' */ +#define DT_NPCX_ALT_ITEM_BY_IDX(inst, i) \ + { \ + .group = DT_PHA(DT_PHANDLE_FROM_PINCTRL(inst, i), alts, group), \ + .bit = DT_PHA(DT_PHANDLE_FROM_PINCTRL(inst, i), alts, bit), \ + .inverted = DT_PHA(DT_PHANDLE_FROM_PINCTRL(inst, i), alts, inv), \ + }, + +/* Length of npcx_alt structures in pinctrl property */ +#define DT_NPCX_ALT_ITEMS_LEN(inst) DT_INST_PROP_LEN(inst, pinctrl) + +/* Macro function to construct a list of npcx_alt items by UTIL_LISTIFY */ +#define DT_NPCX_ALT_ITEMS_FUC(idx, inst) DT_NPCX_ALT_ITEM_BY_IDX(inst, idx) + +#define DT_NPCX_ALT_ITEMS_LIST(inst) { \ + UTIL_LISTIFY(DT_NPCX_ALT_ITEMS_LEN(inst), \ + DT_NPCX_ALT_ITEMS_FUC, \ + inst) \ + } + + #endif /* _NUVOTON_NPCX_SOC_DT_H_ */ diff --git a/soc/arm/nuvoton_npcx/common/soc_pins.h b/soc/arm/nuvoton_npcx/common/soc_pins.h new file mode 100644 index 0000000000..59597647bf --- /dev/null +++ b/soc/arm/nuvoton_npcx/common/soc_pins.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2020 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _NUVOTON_NPCX_SOC_PINS_H_ +#define _NUVOTON_NPCX_SOC_PINS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief NPCX pin-mux configuration structure + * + * Used to indicate the device's corresponding DEVALT register/bit for + * pin-muxing and its polarity to enable alternative functionality. + */ +struct npcx_alt { + uint8_t group:4; + uint8_t bit:3; + uint8_t inverted:1; +}; + +/** + * @brief Select device pin-mux to I/O or its alternative functionality + * + * @param alts_list Pointer to pin-mux configuration list for specific device + * @param alts_size Pin-mux configuration list size + * @param altfunc 0: set pin-mux to GPIO, otherwise specific functionality + */ +void soc_pinctrl_mux_configure(const struct npcx_alt *alts_list, + uint8_t alts_size, int altfunc); + +#ifdef __cplusplus +} +#endif + +#endif /* _NUVOTON_NPCX_SOC_PINS_H_ */ diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series b/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series index 39a077fcb8..51b595ee38 100644 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series +++ b/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series @@ -16,7 +16,13 @@ config CLOCK_CONTROL_NPCX depends on CLOCK_CONTROL help Enable support for NPCX clock controller driver. - + +config PINMUX_NPCX + default y + depends on PINMUX + help + Enable support for NPCX pinmux controller driver. + source "soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7*" endif # SOC_SERIES_NPCX7 diff --git a/soc/arm/nuvoton_npcx/npcx7/soc.c b/soc/arm/nuvoton_npcx/npcx7/soc.c index f69d77b68c..11ad9dc17b 100644 --- a/soc/arm/nuvoton_npcx/npcx7/soc.c +++ b/soc/arm/nuvoton_npcx/npcx7/soc.c @@ -31,3 +31,9 @@ NPCX_REG_OFFSET_CHECK(pmc_reg_t, ENIDL_CTL, 0x003); NPCX_REG_OFFSET_CHECK(pmc_reg_t, PWDWN_CTL1, 0x008); NPCX_REG_OFFSET_CHECK(pmc_reg_t, PWDWN_CTL7, 0x024); +/* SCFG register structure check */ +NPCX_REG_SIZE_CHECK(scfg_reg_t, 0x02F); +NPCX_REG_OFFSET_CHECK(scfg_reg_t, DEV_CTL4, 0x006); +NPCX_REG_OFFSET_CHECK(scfg_reg_t, DEVALT0, 0x010); +NPCX_REG_OFFSET_CHECK(scfg_reg_t, LV_GPIO_CTL0, 0x02A); + diff --git a/soc/arm/nuvoton_npcx/npcx7/soc.h b/soc/arm/nuvoton_npcx/npcx7/soc.h index 4353f57924..4ef4de9811 100644 --- a/soc/arm/nuvoton_npcx/npcx7/soc.h +++ b/soc/arm/nuvoton_npcx/npcx7/soc.h @@ -18,5 +18,6 @@ #include #include #include +#include #endif /* _NUVOTON_NPCX_SOC_H_ */