drivers: spi: introduce gd32 spi driver
Add a simple gd32 spi driver. Signed-off-by: HaiLong Yang <cameledyang@pm.me>
This commit is contained in:
HaiLong Yang
Maureen Helm
parent
2e53071006
commit
9d2425c186
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@ -28,5 +28,6 @@ zephyr_library_sources_ifdef(CONFIG_SPI_PSOC6 spi_psoc6.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_NPCX_FIU spi_npcx_fiu.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_BITBANG spi_bitbang.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_XEC_QMSPI_LDMA spi_xec_qmspi_ldma.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_GD32 spi_gd32.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE spi_handlers.c)
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@ -99,4 +99,6 @@ source "drivers/spi/Kconfig.bitbang"
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source "drivers/spi/Kconfig.xec_qmspi_ldma"
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source "drivers/spi/Kconfig.gd32"
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endif # SPI
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12
drivers/spi/Kconfig.gd32
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12
drivers/spi/Kconfig.gd32
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@ -0,0 +1,12 @@
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# Copyright (c) 2021 BrainCo Inc.
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# SPDX-License-Identifier: Apache-2.0
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# Workaround for not being able to have commas in macro arguments
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DT_COMPAT_GD_GD32_SPI := gd,gd32-spi
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config SPI_GD32
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bool "Gigadevice GD32 SPI driver"
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depends on (SOC_FAMILY_GD32 || SOC_SERIES_GD32VF103)
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default $(dt_compat_enabled,$(DT_COMPAT_GD_GD32_SPI))
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help
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Enables Gigadevice GD32 SPI driver.
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294
drivers/spi/spi_gd32.c
Normal file
294
drivers/spi/spi_gd32.c
Normal file
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@ -0,0 +1,294 @@
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/*
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* Copyright (c) 2021 BrainCo Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT gd_gd32_spi
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#include <errno.h>
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#include <kernel.h>
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#include <drivers/pinctrl.h>
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#include <drivers/spi.h>
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#include <soc.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_gd32);
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#include "spi_context.h"
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/* SPI error status mask. */
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#define SPI_GD32_ERR_MASK (SPI_STAT_RXORERR | SPI_STAT_CONFERR | SPI_STAT_CRCERR)
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#define GD32_SPI_PSC_MAX 0x7U
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#if defined(CONFIG_SOC_SERIES_GD32F4XX) || \
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defined(CONFIG_SOC_SERIES_GD32F403) || \
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defined(CONFIG_SOC_SERIES_GD32VF103) || \
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defined(CONFIG_SOC_SERIES_GD32E10X)
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#define RCU_APB1EN_OFFSET APB1EN_REG_OFFSET
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#elif defined(CONFIG_SOC_SERIES_GD32F3X0)
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#define RCU_APB1EN_OFFSET IDX_APB1EN
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#else
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#error Unknown GD32 soc series
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#endif
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/* Obtain RCU register offset from RCU clock value */
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#define RCU_CLOCK_OFFSET(rcu_clock) ((rcu_clock) >> 6U)
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struct spi_gd32_config {
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uint32_t reg;
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uint32_t rcu_periph_clock;
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const struct pinctrl_dev_config *pcfg;
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};
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struct spi_gd32_data {
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struct spi_context ctx;
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};
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static int spi_gd32_get_err(const struct spi_gd32_config *cfg)
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{
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uint32_t stat = SPI_STAT(cfg->reg);
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if (stat & SPI_GD32_ERR_MASK) {
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LOG_ERR("spi%u error status detected, err = %u",
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cfg->reg, stat & (uint32_t)SPI_GD32_ERR_MASK);
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return -EIO;
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}
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return 0;
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}
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static bool spi_gd32_transfer_ongoing(struct spi_gd32_data *data)
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{
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return spi_context_tx_on(&data->ctx) ||
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spi_context_rx_on(&data->ctx);
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}
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static uint32_t spi_gd32_bus_freq_get(uint32_t rcu_periph_clock)
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{
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uint32_t rcu_bus;
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if (RCU_CLOCK_OFFSET(rcu_periph_clock) == RCU_APB1EN_OFFSET) {
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rcu_bus = CK_APB1;
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} else {
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rcu_bus = CK_APB2;
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}
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return rcu_clock_freq_get(rcu_bus);
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}
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static int spi_gd32_configure(const struct device *dev,
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const struct spi_config *config)
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{
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struct spi_gd32_data *data = dev->data;
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const struct spi_gd32_config *cfg = dev->config;
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uint32_t bus_freq;
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if (spi_context_configured(&data->ctx, config)) {
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return 0;
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}
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if (SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_SLAVE) {
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LOG_ERR("Slave mode not supported");
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return -ENOTSUP;
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}
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SPI_CTL0(cfg->reg) &= ~SPI_CTL0_SPIEN;
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SPI_CTL0(cfg->reg) |= SPI_MASTER;
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SPI_CTL0(cfg->reg) &= ~SPI_TRANSMODE_BDTRANSMIT;
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if (SPI_WORD_SIZE_GET(config->operation) == 8) {
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SPI_CTL0(cfg->reg) |= SPI_FRAMESIZE_8BIT;
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} else {
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SPI_CTL0(cfg->reg) |= SPI_FRAMESIZE_16BIT;
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}
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/* Reset to hardware NSS mode. */
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SPI_CTL0(cfg->reg) &= ~SPI_CTL0_SWNSSEN;
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if (config->cs != NULL) {
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SPI_CTL0(cfg->reg) |= SPI_CTL0_SWNSSEN;
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} else {
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/*
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* For single master env,
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* hardware NSS mode also need to set the NSSDRV bit.
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*/
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SPI_CTL1(cfg->reg) |= SPI_CTL1_NSSDRV;
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}
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SPI_CTL0(cfg->reg) &= ~SPI_CTL0_LF;
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if (config->operation & SPI_TRANSFER_LSB) {
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SPI_CTL0(cfg->reg) |= SPI_CTL0_LF;
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}
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SPI_CTL0(cfg->reg) &= ~SPI_CTL0_CKPL;
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if (config->operation & SPI_MODE_CPOL) {
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SPI_CTL0(cfg->reg) |= SPI_CTL0_CKPL;
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}
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SPI_CTL0(cfg->reg) &= ~SPI_CTL0_CKPH;
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if (config->operation & SPI_MODE_CPHA) {
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SPI_CTL0(cfg->reg) |= SPI_CTL0_CKPH;
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}
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bus_freq = spi_gd32_bus_freq_get(cfg->rcu_periph_clock);
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for (uint8_t i = 0U; i <= GD32_SPI_PSC_MAX; i++) {
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bus_freq = bus_freq >> 1U;
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if (bus_freq <= config->frequency) {
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SPI_CTL0(cfg->reg) &= ~SPI_CTL0_PSC;
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SPI_CTL0(cfg->reg) |= CTL0_PSC(i);
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break;
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}
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}
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data->ctx.config = config;
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return 0;
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}
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static int spi_gd32_frame_exchange(const struct device *dev)
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{
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struct spi_gd32_data *data = dev->data;
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const struct spi_gd32_config *cfg = dev->config;
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struct spi_context *ctx = &data->ctx;
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uint16_t tx_frame = 0U, rx_frame = 0U;
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if (SPI_WORD_SIZE_GET(ctx->config->operation) == 8) {
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if (spi_context_tx_buf_on(ctx)) {
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tx_frame = UNALIGNED_GET((uint8_t *)(data->ctx.tx_buf));
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}
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/* For 8 bits mode, spi will forced SPI_DATA[15:8] to 0. */
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SPI_DATA(cfg->reg) = tx_frame;
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spi_context_update_tx(ctx, 1, 1);
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} else {
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if (spi_context_tx_buf_on(ctx)) {
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tx_frame = UNALIGNED_GET((uint8_t *)(data->ctx.tx_buf));
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}
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SPI_DATA(cfg->reg) = tx_frame;
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spi_context_update_tx(ctx, 2, 1);
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}
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while ((SPI_STAT(cfg->reg) & SPI_STAT_RBNE) == 0) {
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/* NOP */
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}
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if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
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/* For 8 bits mode, spi will forced SPI_DATA[15:8] to 0. */
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rx_frame = SPI_DATA(cfg->reg);
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if (spi_context_rx_buf_on(ctx)) {
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UNALIGNED_PUT(rx_frame, (uint8_t *)data->ctx.rx_buf);
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}
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spi_context_update_rx(ctx, 1, 1);
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} else {
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rx_frame = SPI_DATA(cfg->reg);
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if (spi_context_rx_buf_on(ctx)) {
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UNALIGNED_PUT(rx_frame, (uint16_t *)data->ctx.rx_buf);
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}
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spi_context_update_rx(ctx, 2, 1);
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}
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return spi_gd32_get_err(cfg);
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}
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static int spi_gd32_transceive(const struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct spi_gd32_data *data = dev->data;
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const struct spi_gd32_config *cfg = dev->config;
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int ret;
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spi_context_lock(&data->ctx, false, NULL, config);
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ret = spi_gd32_configure(dev, config);
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if (ret < 0) {
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goto error;
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}
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SPI_CTL0(cfg->reg) |= SPI_CTL0_SPIEN;
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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spi_context_cs_control(&data->ctx, true);
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do {
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ret = spi_gd32_frame_exchange(dev);
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if (ret < 0) {
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break;
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}
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} while (spi_gd32_transfer_ongoing(data));
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spi_context_cs_control(&data->ctx, false);
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SPI_CTL0(cfg->reg) &= ~SPI_CTL0_SPIEN;
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error:
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spi_context_release(&data->ctx, ret);
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return ret;
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}
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static int spi_gd32_release(const struct device *dev,
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const struct spi_config *config)
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{
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struct spi_gd32_data *data = dev->data;
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static struct spi_driver_api spi_gd32_driver_api = {
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.transceive = spi_gd32_transceive,
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.release = spi_gd32_release
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};
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int spi_gd32_init(const struct device *dev)
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{
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struct spi_gd32_data *data = dev->data;
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const struct spi_gd32_config *cfg = dev->config;
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int ret;
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rcu_periph_clock_enable(cfg->rcu_periph_clock);
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret) {
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LOG_ERR("Failed to apply pinctrl state");
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return ret;
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}
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ret = spi_context_cs_configure_all(&data->ctx);
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if (ret < 0) {
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return ret;
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}
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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#define GD32_SPI_INIT(idx) \
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PINCTRL_DT_INST_DEFINE(idx); \
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static struct spi_gd32_data spi_gd32_data_##idx = { \
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SPI_CONTEXT_INIT_LOCK(spi_gd32_data_##idx, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_gd32_data_##idx, ctx), \
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SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(idx), ctx) \
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}; \
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static struct spi_gd32_config spi_gd32_config_##idx = { \
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.reg = DT_INST_REG_ADDR(idx), \
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.rcu_periph_clock = DT_INST_PROP(idx, rcu_periph_clock), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
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}; \
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DEVICE_DT_INST_DEFINE(idx, &spi_gd32_init, NULL, &spi_gd32_data_##idx, \
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&spi_gd32_config_##idx, POST_KERNEL, \
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CONFIG_SPI_INIT_PRIORITY, &spi_gd32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(GD32_SPI_INIT)
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