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soc/intel_adsp: Correct LP-SRAM sizes in DTS

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Everything I can find as a reference says that the LP-SRAM block on
these devices is 64kb, and direct experimentation with cAVS 1.5 and
2.5 agrees.  Access to areas beyond 64k hangs the DSP (it should cause
a PIF fault I guess, but the exception never gets trapped, that's
probably a different problem).

Fix this in devicetree to reflect what actually works.  It's not clear
where the 128k values came from; if they're not typos we can correct
that when we find better docs.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-12-13 15:31:15 -08:00 committed by Maureen Helm
parent 35f906e65c
commit 9eca65deca
3 changed files with 3 additions and 3 deletions
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2
dts/xtensa/intel/intel_cavs18.dtsi
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@ -47,7 +47,7 @@
sram1: memory@be800000 { sram1: memory@be800000 {
device_type = "memory"; device_type = "memory";
compatible = "mmio-sram"; compatible = "mmio-sram";
reg = <0xbe800000 DT_SIZE_K(128)>; reg = <0xbe800000 DT_SIZE_K(64)>;
}; };
soc { soc {

2
dts/xtensa/intel/intel_cavs20.dtsi
View file

@ -47,7 +47,7 @@
sram1: memory@be800000 { sram1: memory@be800000 {
device_type = "memory"; device_type = "memory";
compatible = "mmio-sram"; compatible = "mmio-sram";
reg = <0xbe800000 DT_SIZE_K(128)>; reg = <0xbe800000 DT_SIZE_K(64)>;
}; };
soc { soc {

2
dts/xtensa/intel/intel_cavs25.dtsi
View file

@ -47,7 +47,7 @@
sram1: memory@be800000 { sram1: memory@be800000 {
device_type = "memory"; device_type = "memory";
compatible = "mmio-sram"; compatible = "mmio-sram";
reg = <0xbe800000 DT_SIZE_K(128)>; reg = <0xbe800000 DT_SIZE_K(64)>;
}; };
soc { soc {