dts/bindings/riscv: don't enforce riscv,isa values with enum array

This commit removes the enum array with allowed values for the `riscv,isa`
field. There are many ways in which RISC-V ISA extension string can be
represented, and listing them all is futile. In addition, custom extensions
can be implemented, meaning every extension would have to be listed in the
enum array as well.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>

dts/bindings/riscv/riscv,cpus.yaml

@@ -17,10 +17,3 @@ properties:
     description: RISC-V instruction set architecture
     required: true
     type: string
-    enum:
-      - rv32emc
-      - rv32imac
-      - rv32imafc
-      - rv32imafcb
-      - rv64imac
-      - rv64imafdc