drivers: bbram: Add bbram driver for mec device

Add bbram driver for Microchip mec device

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>

drivers/bbram/CMakeLists.txt

@@ -6,3 +6,4 @@ zephyr_library()
 zephyr_library_sources_ifdef(CONFIG_BBRAM_NPCX bbram_npcx.c)
 zephyr_library_sources_ifdef(CONFIG_BBRAM_IT8XXX2 bbram_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_BBRAM_EMUL bbram_emul.c)
+zephyr_library_sources_ifdef(CONFIG_BBRAM_XEC bbram_xec.c)

drivers/bbram/Kconfig

@@ -24,4 +24,6 @@ source "drivers/bbram/Kconfig.it8xxx2"
 
 source "drivers/bbram/Kconfig.bbram_emul"
 
+source "drivers/bbram/Kconfig.xec"
+
 endif # BBRAM

drivers/bbram/Kconfig.xec

@@ -0,0 +1,13 @@
+# Copyright (c) 2021 Google Inc
+# Copyright (c) 2022 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+DT_COMPAT_ST_BBRAM_XEC := microchip,xec-bbram
+
+config BBRAM_XEC
+	bool "Microchip XEC Battery-backed RAM drivers"
+	depends on SOC_FAMILY_MEC
+	default $(dt_compat_enabled,$(DT_COMPAT_ST_BBRAM_XEC))
+	help
+	  This option enables the BBRAM driver for Microchip XEC family of
+	  processors.

drivers/bbram/bbram_xec.c

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2021 Microchip Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT microchip_xec_bbram
+
+#include <drivers/bbram.h>
+#include <errno.h>
+#include <soc.h>
+#include <sys/util.h>
+
+#include <logging/log.h>
+LOG_MODULE_REGISTER(bbram, CONFIG_BBRAM_LOG_LEVEL);
+
+/** Device config */
+struct bbram_xec_config {
+	/** BBRAM base address */
+	uint8_t *base;
+	/** BBRAM size (Unit:bytes) */
+	int size;
+};
+
+static int bbram_xec_check_invalid(const struct device *dev)
+{
+	struct vbatr_regs *const regs = (struct vbatr_regs *)(DT_REG_ADDR_BY_NAME(
+					DT_INST(0, microchip_xec_pcr), vbatr));
+
+	if (regs->PFRS & BIT(MCHP_VBATR_PFRS_VBAT_RST_POS)) {
+		regs->PFRS |= BIT(MCHP_VBATR_PFRS_VBAT_RST_POS);
+		LOG_ERR("VBAT power rail failure");
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+static int bbram_xec_get_size(const struct device *dev, size_t *size)
+{
+	const struct bbram_xec_config *dcfg = dev->config;
+
+	*size = dcfg->size;
+	return 0;
+}
+
+static int bbram_xec_read(const struct device *dev, size_t offset, size_t size,
+			  uint8_t *data)
+{
+	const struct bbram_xec_config *dcfg = dev->config;
+
+	if (size < 1 || offset + size > dcfg->size) {
+		LOG_ERR("Invalid params");
+		return -EFAULT;
+	}
+
+	bytecpy(data, dcfg->base + offset, size);
+	return 0;
+}
+
+static int bbram_xec_write(const struct device *dev, size_t offset, size_t size,
+			       const uint8_t *data)
+{
+	const struct bbram_xec_config *dcfg = dev->config;
+
+	if (size < 1 || offset + size > dcfg->size) {
+		LOG_ERR("Invalid params");
+		return -EFAULT;
+	}
+
+	bytecpy(dcfg->base + offset, data, size);
+	return 0;
+}
+
+static const struct bbram_driver_api bbram_xec_driver_api = {
+	.check_invalid = bbram_xec_check_invalid,
+	.get_size = bbram_xec_get_size,
+	.read = bbram_xec_read,
+	.write = bbram_xec_write,
+};
+
+static int bbram_xec_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+#define BBRAM_INIT(inst)						\
+	static const struct bbram_xec_config bbram_cfg_##inst = {	\
+		.base = (uint8_t *)(DT_INST_REG_ADDR(inst)),		\
+		.size = DT_INST_REG_SIZE(inst),				\
+	};								\
+	DEVICE_DT_INST_DEFINE(inst, bbram_xec_init, NULL, NULL,		\
+			      &bbram_cfg_##inst,			\
+			      PRE_KERNEL_1, CONFIG_BBRAM_INIT_PRIORITY,	\
+			      &bbram_xec_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(BBRAM_INIT);

dts/arm/microchip/mec1501hsz.dtsi

@@ -85,6 +85,12 @@
 			label = "RTIMER";
 			girqs = <23 10>;
 		};
+		bbram: bb-ram@4000a800 {
+			compatible = "microchip,xec-bbram";
+			reg = <0x4000a800 0x80>;
+			reg-names = "memory";
+			label = "BBRAM";
+		};
 		wdog: watchdog@40000400 {
 			compatible = "microchip,xec-watchdog";
 			reg = <0x40000400 0x400>;

dts/arm/microchip/mec172xnsz.dtsi

@@ -508,9 +508,11 @@
 			label = "WEEKTMR_0";
 			status = "disabled";
 		};
-		vbm0: vbm@4000a800 {
+		bbram: bb-ram@4000a800 {
+			compatible = "microchip,xec-bbram";
 			reg = <0x4000a800 0x100>;
-			label = "VBM_0";
+			reg-names = "memory";
+			label = "BBRAM";
 		};
 		vci0: vci@4000ae00 {
 			reg = <0x4000ae00 0x40>;

dts/bindings/memory-controllers/microchip,xec-bbram.yaml

@@ -0,0 +1,12 @@
+# Copyright (c) 2021 Microchip Technologies Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip, XEC family Battery Backed RAM node
+
+compatible: "microchip,xec-bbram"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true