dts/arm/st/u5: Support for STM32U59x
Added support for STM32U595 and STM32U599 with basic peripherals. Signed-off-by: Balthazar Deliers <balthazar.deliers@psicontrol.com>
This commit is contained in:
Balthazar Deliers
Carles Cufí
parent
ef697e5c4f
commit
a0ad7b7752
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@ -1,6 +1,7 @@
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/*
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* Copyright (c) 2021 The Chromium OS Authors
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* Copyright (c) 2021 Linaro Limited
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* Copyright (c) 2023 PSICONTROL nv
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -399,6 +400,87 @@
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status = "disabled";
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};
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i2c3: i2c@46002800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46002800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000080>;
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interrupts = <88 0>, <89 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c4: i2c@40008400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40008400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
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interrupts = <101 0>, <100 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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lptim1: timers@46004400 {
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compatible = "st,stm32-lptim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
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interrupts = <67 1>;
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interrupt-names = "wakeup";
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st,static-prescaler;
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status = "disabled";
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};
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lptim2: timers@40009400 {
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compatible = "st,stm32-lptim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
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interrupts = <68 0>;
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interrupt-names = "global";
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st,static-prescaler;
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status = "disabled";
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};
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lptim3: timers@46004800 {
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compatible = "st,stm32-lptim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00001000>;
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interrupts = <98 0>;
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interrupt-names = "global";
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st,static-prescaler;
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status = "disabled";
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};
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lptim4: timers@46004c00 {
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compatible = "st,stm32-lptim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00002000>;
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interrupts = <110 0>;
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interrupt-names = "global";
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st,static-prescaler;
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status = "disabled";
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};
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rtc: rtc@46007800 {
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compatible = "st,stm32-rtc";
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reg = <0x46007800 0x400>;
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interrupts = <2 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>;
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prescaler = <32768>;
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status = "disabled";
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};
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012c00 0x400>;
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@ -447,27 +529,6 @@
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};
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};
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lptim1: timers@46004400 {
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compatible = "st,stm32-lptim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
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interrupts = <67 1>;
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interrupt-names = "wakeup";
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st,static-prescaler;
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status = "disabled";
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};
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rtc: rtc@46007800 {
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compatible = "st,stm32-rtc";
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reg = <0x46007800 0x400>;
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interrupts = <2 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>;
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prescaler = <32768>;
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status = "disabled";
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};
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timers4: timers@40000800 {
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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@ -510,6 +571,38 @@
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};
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};
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
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resets = <&rctl STM32_RESET(APB1L, 4U)>;
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interrupts = <49 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
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resets = <&rctl STM32_RESET(APB1L, 5U)>;
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interrupts = <50 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers8: timers@40013400 {
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compatible = "st,stm32-timers";
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reg = <0x40013400 0x400>;
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60
dts/arm/st/u5/stm32u595.dtsi
Normal file
60
dts/arm/st/u5/stm32u595.dtsi
Normal file
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@ -0,0 +1,60 @@
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/*
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* Copyright (c) 2023 PSICONTROl nv
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u5.dtsi>
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/ {
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soc {
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pinctrl: pin-controller@42020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x42020000 0x2800>;
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gpioj: gpio@42022400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42022400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000200>;
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};
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};
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usart6: serial@40006400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40006400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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resets = <&rctl STM32_RESET(APB1L, 25U)>;
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interrupts = <126 0>;
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status = "disabled";
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};
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i2c5: i2c@40009800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000040>;
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interrupts = <128 0>, <127 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c6: i2c@40009c00 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000080>;
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interrupts = <130 0>, <129 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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};
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};
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7
dts/arm/st/u5/stm32u599.dtsi
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7
dts/arm/st/u5/stm32u599.dtsi
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@ -0,0 +1,7 @@
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/*
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* Copyright (c) 2023 PSICONTROL nv
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u5/stm32u595.dtsi>
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26
dts/arm/st/u5/stm32u599Xj.dtsi
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26
dts/arm/st/u5/stm32u599Xj.dtsi
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2023 PSICONTROL nv
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/u5/stm32u599.dtsi>
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/ {
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sram0: memory@20000000 {
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/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
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reg = <0x20000000 DT_SIZE_K(2496)>;
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};
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sram1: memory@28000000 {
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/* SRAM4 */
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reg = <0x28000000 DT_SIZE_K(16)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_M(4)>;
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};
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};
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};
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};
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14
soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u595xx
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14
soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u595xx
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@ -0,0 +1,14 @@
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# STMicroelectronics STM32U595XX MCU
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# Copyright (c) 2023 PSICONTROL nv
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# SPDX-License-Identifier: Apache-2.0
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if SOC_STM32U595XX
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config SOC
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default "stm32u595xx"
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config NUM_IRQS
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default 132
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endif # SOC_STM32U595XX
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14
soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u599xx
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14
soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u599xx
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@ -0,0 +1,14 @@
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# STMicroelectronics STM32U599XX MCU
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# Copyright (c) 2023 PSICONTROL nv
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# SPDX-License-Identifier: Apache-2.0
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if SOC_STM32U599XX
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config SOC
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default "stm32u599xx"
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config NUM_IRQS
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default 139
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endif # SOC_STM32U599XX
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@ -1,6 +1,7 @@
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# ST Microelectronics STM32U5 MCU line
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# Copyright (c) 2021 Linaro Limited
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# Copyright (c) 2023 PSICONTROL nv
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# SPDX-License-Identifier: Apache-2.0
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choice
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@ -13,4 +14,10 @@ config SOC_STM32U575XX
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config SOC_STM32U585XX
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bool "STM32U585XX"
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config SOC_STM32U595XX
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bool "STM32U595XX"
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config SOC_STM32U599XX
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bool "STM32U599XX"
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endchoice
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