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dts/arm/st/u5: Support for STM32U59x

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Added support for STM32U595 and STM32U599 with basic peripherals.

Signed-off-by: Balthazar Deliers <balthazar.deliers@psicontrol.com>
This commit is contained in:
Balthazar Deliers 2023-04-21 15:18:39 +02:00 committed by Carles Cufí
parent ef697e5c4f
commit a0ad7b7752
7 changed files with 242 additions and 21 deletions
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135
dts/arm/st/u5/stm32u5.dtsi
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@ -1,6 +1,7 @@
/*
* Copyright (c) 2021 The Chromium OS Authors
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 PSICONTROL nv
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -399,6 +400,87 @@
status = "disabled";
};
i2c3: i2c@46002800 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x46002800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000080>;
interrupts = <88 0>, <89 0>;
interrupt-names = "event", "error";
status = "disabled";
};
i2c4: i2c@40008400 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40008400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
interrupts = <101 0>, <100 0>;
interrupt-names = "event", "error";
status = "disabled";
};
lptim1: timers@46004400 {
compatible = "st,stm32-lptim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x46004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
interrupts = <67 1>;
interrupt-names = "wakeup";
st,static-prescaler;
status = "disabled";
};
lptim2: timers@40009400 {
compatible = "st,stm32-lptim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40009400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
interrupts = <68 0>;
interrupt-names = "global";
st,static-prescaler;
status = "disabled";
};
lptim3: timers@46004800 {
compatible = "st,stm32-lptim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x46004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00001000>;
interrupts = <98 0>;
interrupt-names = "global";
st,static-prescaler;
status = "disabled";
};
lptim4: timers@46004c00 {
compatible = "st,stm32-lptim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x46004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00002000>;
interrupts = <110 0>;
interrupt-names = "global";
st,static-prescaler;
status = "disabled";
};
rtc: rtc@46007800 {
compatible = "st,stm32-rtc";
reg = <0x46007800 0x400>;
interrupts = <2 0>;
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>;
prescaler = <32768>;
status = "disabled";
};
timers1: timers@40012c00 {
compatible = "st,stm32-timers";
reg = <0x40012c00 0x400>;
@ -447,27 +529,6 @@
};
};
lptim1: timers@46004400 {
compatible = "st,stm32-lptim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x46004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
interrupts = <67 1>;
interrupt-names = "wakeup";
st,static-prescaler;
status = "disabled";
};
rtc: rtc@46007800 {
compatible = "st,stm32-rtc";
reg = <0x46007800 0x400>;
interrupts = <2 0>;
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>;
prescaler = <32768>;
status = "disabled";
};
timers4: timers@40000800 {
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
@ -510,6 +571,38 @@
};
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
resets = <&rctl STM32_RESET(APB1L, 4U)>;
interrupts = <49 0>;
interrupt-names = "global";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers7: timers@40001400 {
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
resets = <&rctl STM32_RESET(APB1L, 5U)>;
interrupts = <50 0>;
interrupt-names = "global";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers8: timers@40013400 {
compatible = "st,stm32-timers";
reg = <0x40013400 0x400>;

60
dts/arm/st/u5/stm32u595.dtsi Normal file
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@ -0,0 +1,60 @@
/*
* Copyright (c) 2023 PSICONTROl nv
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u5.dtsi>
/ {
soc {
pinctrl: pin-controller@42020000 {
compatible = "st,stm32-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x42020000 0x2800>;
gpioj: gpio@42022400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42022400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000200>;
};
};
usart6: serial@40006400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40006400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
resets = <&rctl STM32_RESET(APB1L, 25U)>;
interrupts = <126 0>;
status = "disabled";
};
i2c5: i2c@40009800 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40009800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000040>;
interrupts = <128 0>, <127 0>;
interrupt-names = "event", "error";
status = "disabled";
};
i2c6: i2c@40009c00 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40009c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000080>;
interrupts = <130 0>, <129 0>;
interrupt-names = "event", "error";
status = "disabled";
};
};
};

7
dts/arm/st/u5/stm32u599.dtsi Normal file
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@ -0,0 +1,7 @@
/*
* Copyright (c) 2023 PSICONTROL nv
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u5/stm32u595.dtsi>

26
dts/arm/st/u5/stm32u599Xj.dtsi Normal file
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@ -0,0 +1,26 @@
/*
* Copyright (c) 2023 PSICONTROL nv
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/u5/stm32u599.dtsi>
/ {
sram0: memory@20000000 {
/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
reg = <0x20000000 DT_SIZE_K(2496)>;
};
sram1: memory@28000000 {
/* SRAM4 */
reg = <0x28000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_M(4)>;
};
};
};
};

14
soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u595xx Normal file
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@ -0,0 +1,14 @@
# STMicroelectronics STM32U595XX MCU
# Copyright (c) 2023 PSICONTROL nv
# SPDX-License-Identifier: Apache-2.0
if SOC_STM32U595XX
config SOC
default "stm32u595xx"
config NUM_IRQS
default 132
endif # SOC_STM32U595XX

14
soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u599xx Normal file
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@ -0,0 +1,14 @@
# STMicroelectronics STM32U599XX MCU
# Copyright (c) 2023 PSICONTROL nv
# SPDX-License-Identifier: Apache-2.0
if SOC_STM32U599XX
config SOC
default "stm32u599xx"
config NUM_IRQS
default 139
endif # SOC_STM32U599XX

7
soc/arm/st_stm32/stm32u5/Kconfig.soc
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@ -1,6 +1,7 @@
# ST Microelectronics STM32U5 MCU line
# Copyright (c) 2021 Linaro Limited
# Copyright (c) 2023 PSICONTROL nv
# SPDX-License-Identifier: Apache-2.0
choice
@ -13,4 +14,10 @@ config SOC_STM32U575XX
config SOC_STM32U585XX
bool "STM32U585XX"
config SOC_STM32U595XX
bool "STM32U595XX"
config SOC_STM32U599XX
bool "STM32U599XX"
endchoice