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drivers: pwm: imx: remove redundant DEV_BASE accessor

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The base variable type stored in config already has the right type. Such
kind of accessors have been removed in many other places.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas 2022-06-17 13:46:51 +02:00 committed by Carles Cufí
parent 6bd248d005
commit a0ff40ca4b
1 changed files with 11 additions and 17 deletions
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28
drivers/pwm/pwm_imx.c
View file

@ -19,9 +19,6 @@ LOG_MODULE_REGISTER(pwm_imx);
#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) \
<<PWM_PWMCR_SWR_SHIFT))&PWM_PWMCR_SWR_MASK)
#define DEV_BASE(dev) \
((PWM_Type *)((const struct imx_pwm_config * const)(dev)->config)->base)
struct imx_pwm_config {
PWM_Type *base;
uint16_t prescaler;
@ -41,10 +38,9 @@ static bool imx_pwm_is_enabled(PWM_Type *base)
static int imx_pwm_get_cycles_per_sec(const struct device *dev, uint32_t pwm,
uint64_t *cycles)
{
PWM_Type *base = DEV_BASE(dev);
const struct imx_pwm_config *config = dev->config;
*cycles = get_pwm_clock_freq(base) >> config->prescaler;
*cycles = get_pwm_clock_freq(config->base) >> config->prescaler;
return 0;
}
@ -53,11 +49,10 @@ static int imx_pwm_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles,
pwm_flags_t flags)
{
PWM_Type *base = DEV_BASE(dev);
const struct imx_pwm_config *config = dev->config;
struct imx_pwm_data *data = dev->data;
unsigned int period_ms;
bool enabled = imx_pwm_is_enabled(base);
bool enabled = imx_pwm_is_enabled(config->base);
int wait_count = 0, fifoav;
uint32_t cr, sr;
@ -84,23 +79,23 @@ static int imx_pwm_set_cycles(const struct device *dev, uint32_t channel,
* when the controller is enabled and the FIFO is fully loaded.
*/
if (enabled) {
sr = PWM_PWMSR_REG(base);
sr = PWM_PWMSR_REG(config->base);
fifoav = PWM_PWMSR_FIFOAV(sr);
if (fifoav == PWM_PWMSR_FIFOAV_4WORDS) {
period_ms = (get_pwm_clock_freq(base) >>
period_ms = (get_pwm_clock_freq(config->base) >>
config->prescaler) * MSEC_PER_SEC;
k_sleep(K_MSEC(period_ms));
sr = PWM_PWMSR_REG(base);
sr = PWM_PWMSR_REG(config->base);
if (fifoav == PWM_PWMSR_FIFOAV(sr)) {
LOG_WRN("there is no free FIFO slot\n");
}
}
} else {
PWM_PWMCR_REG(base) = PWM_PWMCR_SWR(1);
PWM_PWMCR_REG(config->base) = PWM_PWMCR_SWR(1);
do {
k_sleep(K_MSEC(1));
cr = PWM_PWMCR_REG(base);
cr = PWM_PWMCR_REG(config->base);
} while ((PWM_PWMCR_SWR(cr)) &&
(++wait_count < CONFIG_PWM_PWMSWR_LOOP));
@ -120,7 +115,7 @@ static int imx_pwm_set_cycles(const struct device *dev, uint32_t channel,
return -EINVAL;
}
PWM_PWMSAR_REG(base) = pulse_cycles;
PWM_PWMSAR_REG(config->base) = pulse_cycles;
if (data->period_cycles != period_cycles) {
LOG_WRN("Changing period cycles from %d to %d in %s",
@ -128,14 +123,14 @@ static int imx_pwm_set_cycles(const struct device *dev, uint32_t channel,
dev->name);
data->period_cycles = period_cycles;
PWM_PWMPR_REG(base) = period_cycles;
PWM_PWMPR_REG(config->base) = period_cycles;
}
cr = PWM_PWMCR_EN_MASK | PWM_PWMCR_PRESCALER(config->prescaler) |
PWM_PWMCR_DOZEN_MASK | PWM_PWMCR_WAITEN_MASK |
PWM_PWMCR_DBGEN_MASK | PWM_PWMCR_CLKSRC(2);
PWM_PWMCR_REG(base) = cr;
PWM_PWMCR_REG(config->base) = cr;
return 0;
}
@ -145,14 +140,13 @@ static int imx_pwm_init(const struct device *dev)
const struct imx_pwm_config *config = dev->config;
struct imx_pwm_data *data = dev->data;
int err;
PWM_Type *base = DEV_BASE(dev);
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
return err;
}
PWM_PWMPR_REG(base) = data->period_cycles;
PWM_PWMPR_REG(config->base) = data->period_cycles;
return 0;
}