drivers: sdhc: add driver support for emmc host controller
add host controller driver support for emmc version 5.1. The driver expose zephyr sdhc api interface for emmc host controller. Signed-off-by: Najumon B.A <najumon.ba@intel.com>
This commit is contained in:
Najumon B.A
Carles Cufí
parent
c5094776e9
commit
a14bc241c0
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@ -7,5 +7,5 @@ zephyr_library_sources_ifdef(CONFIG_IMX_USDHC imx_usdhc.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_SDHC sdhc_spi.c)
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zephyr_library_sources_ifdef(CONFIG_MCUX_SDIF mcux_sdif.c)
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zephyr_library_sources_ifdef(CONFIG_SAM_HSMCI sam_hsmci.c)
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zephyr_library_sources_ifdef(CONFIG_INTEL_EMMC_HOST intel_emmc_host.c)
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endif()
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@ -12,6 +12,7 @@ source "drivers/sdhc/Kconfig.imx"
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source "drivers/sdhc/Kconfig.spi"
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source "drivers/sdhc/Kconfig.mcux_sdif"
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source "drivers/sdhc/Kconfig.sam_hsmci"
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source "drivers/sdhc/Kconfig.intel"
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config SDHC_INIT_PRIORITY
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int "SDHC driver init priority"
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@ -50,5 +51,4 @@ module = SDHC
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module-str = sdhc
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source "subsys/logging/Kconfig.template.log_config"
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endif # SDHC
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58
drivers/sdhc/Kconfig.intel
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58
drivers/sdhc/Kconfig.intel
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@ -0,0 +1,58 @@
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# Copyright (c) 2023 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config INTEL_EMMC_HOST
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bool "EMMC driver"
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select SDHC_SUPPORTS_NATIVE_MODE
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select EVENTS
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default y
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depends on DT_HAS_INTEL_EMMC_HOST_ENABLED
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help
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EMMC driver support. Though this driver can be easily port to
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any HW which is complaint to eMMC spec, currently it is only
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validated using intel's EMMC host controller.
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if INTEL_EMMC_HOST
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config INTEL_EMMC_HOST_INTR
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bool "EMMC host controller interrupt mode"
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default y
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help
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EMMC host controller interrupt mode support.
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config INTEL_EMMC_HOST_DMA
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bool "EMMC host controller DMA mode"
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select DCACHE
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help
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EMMC host controller DMA mode support.
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config INTEL_EMMC_HOST_ADMA
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bool "EMMC host controller ADMA mode"
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depends on INTEL_EMMC_HOST_DMA
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help
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EMMC host controller ADMA mode support.
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config INTEL_EMMC_HOST_ADMA_DESC_SIZE
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int "EMMC host controller ADMA Descriptor size"
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depends on INTEL_EMMC_HOST_ADMA
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default 32
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help
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EMMC host controller ADMA Descriptor size.
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config INTEL_EMMC_HOST_AUTO_STOP
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bool "auto stop command mode"
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default y
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help
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Auto stop command mode support.
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config INTEL_EMMC_HOST_BLOCK_GAP
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bool "Block gap mode"
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depends on INTEL_EMMC_HOST_DMA
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help
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Block gap mode support.
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config INTEL_EMMC_HOST_TUNING
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bool "Host tuning"
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help
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Host tuning support.
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endif
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1348
drivers/sdhc/intel_emmc_host.c
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1348
drivers/sdhc/intel_emmc_host.c
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File diff suppressed because it is too large
Load diff
303
drivers/sdhc/intel_emmc_host.h
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303
drivers/sdhc/intel_emmc_host.h
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@ -0,0 +1,303 @@
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/*
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* Copyright (c) 2023 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_DISK_EMMC_HOST_H_
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#define ZEPHYR_DRIVERS_DISK_EMMC_HOST_H_
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/* Bit map for command Register */
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#define EMMC_HOST_CMD_RESP_TYPE_LOC 0
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#define EMMC_HOST_CMD_CRC_CHECK_EN_LOC 3
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#define EMMC_HOST_CMD_IDX_CHECK_EN_LOC 4
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#define EMMC_HOST_CMD_DATA_PRESENT_LOC 5
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#define EMMC_HOST_CMD_TYPE_LOC 6
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#define EMMC_HOST_CMD_INDEX_LOC 8
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/* Bit map for Transfer Mode Register */
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#define EMMC_HOST_XFER_DMA_EN_LOC 0
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#define EMMC_HOST_XFER_BLOCK_CNT_EN_LOC 1
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#define EMMC_HOST_XFER_AUTO_CMD_EN_LOC 2
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#define EMMC_HOST_XFER_DATA_DIR_LOC 4
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#define EMMC_HOST_XFER_MULTI_BLOCK_SEL_LOC 5
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#define EMMC_HOST_XFER_DMA_EN_MASK 0x01
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#define EMMC_HOST_XFER_BLOCK_CNT_EN_MASK 0x01
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#define EMMC_HOST_XFER_AUTO_CMD_EN_MASK 0x03
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#define EMMC_HOST_XFER_DATA_DIR_MASK 0x01
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#define EMMC_HOST_XFER_MULTI_BLOCK_SEL_MASK 0x01
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/* Bit map for Block Size and GAP Register */
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#define EMMC_HOST_BLOCK_SIZE_LOC 0
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#define EMMC_HOST_BLOCK_SIZE_MASK 0xFFF
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#define EMMC_HOST_DMA_BUF_SIZE_LOC 12
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#define EMMC_HOST_DMA_BUF_SIZE_MASK 0x07
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#define EMMC_HOST_BLOCK_GAP_LOC 3
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#define EMMC_HOST_BLOCK_GAP_MASK 0x01
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#define EMMC_HOST_ADMA_BUFF_ADD_LOC 32
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#define EMMC_HOST_ADMA_BUFF_LEN_LOC 16
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#define EMMC_HOST_ADMA_BUFF_LINK_NEXT (0x3 << 4)
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#define EMMC_HOST_ADMA_BUFF_LINK_LAST (0x2 << 4)
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#define EMMC_HOST_ADMA_INTR_EN BIT(2)
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#define EMMC_HOST_ADMA_BUFF_LAST BIT(1)
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#define EMMC_HOST_ADMA_BUFF_VALID BIT(0)
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/* Bit Map and length details for Clock Control Register */
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#define EMMC_HOST_CLK_SDCLCK_FREQ_SEL_LOC 8
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#define EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_LOC 6
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#define EMMC_HOST_CLK_SDCLCK_FREQ_SEL_MASK 0xFF
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#define EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_MASK 0x03
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/* Bit Map for Host Control 1 Register */
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#define EMMC_HOST_CTRL1_DAT_WIDTH_LOC 1
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#define EMMC_HOST_CTRL1_DMA_SEL_LOC 3
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#define EMMC_HOST_CTRL1_EXT_DAT_WIDTH_LOC 5
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#define EMMC_HOST_CTRL1_DMA_SEL_MASK 0x03
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#define EMMC_HOST_CTRL1_EXT_DAT_WIDTH_MASK 0x01
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#define EMMC_HOST_CTRL1_DAT_WIDTH_MASK 0x01
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/** Constants Software Reset register */
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#define EMMC_HOST_SW_RESET_REG_ALL BIT(0)
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#define EMMC_HOST_SW_RESET_REG_CMD BIT(1)
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#define EMMC_HOST_SW_RESET_REG_DATA BIT(2)
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#define EMMC_HOST_RESPONSE_SIZE 4
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#define EMMC_HOST_OCR_BUSY_BIT BIT(31)
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#define EMMC_HOST_OCR_CAPACITY_MASK 0x40000000U
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#define EMMC_HOST_DUAL_VOLTAGE_RANGE 0x40FF8080U
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#define EMMC_HOST_BLOCK_SIZE 512
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#define EMMC_HOST_RCA_SHIFT 16
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#define EMMC_HOST_EXTCSD_SEC_COUNT 53
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#define EMMC_HOST_EXTCSD_GENERIC_CMD6_TIME 62
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#define EMMC_HOST_EXTCSD_BUS_WIDTH_ADDR 0xB7
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#define EMMC_HOST_EXTCSD_HS_TIMING_ADDR 0xB9
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#define EMMC_HOST_BUS_SPEED_HIGHSPEED 1
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#define EMMC_HOST_CMD_COMPLETE_RETRY 10000
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#define EMMC_HOST_XFR_COMPLETE_RETRY 2000000
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#define EMMC_HOST_CMD1_RETRY_TIMEOUT 1000
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#define EMMC_HOST_CMD6_TIMEOUT_MULT 10
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#define EMMC_HOST_NORMAL_INTR_MASK 0x3f
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#define EMMC_HOST_ERROR_INTR_MASK 0x13ff
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#define EMMC_HOST_NORMAL_INTR_MASK_CLR 0x60ff
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#define EMMC_HOST_POWER_CTRL_SD_BUS_POWER 0x1
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#define EMMC_HOST_POWER_CTRL_SD_BUS_VOLT_SEL 0x5
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#define EMMC_HOST_UHSMODE_SDR12 0x0
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#define EMMC_HOST_UHSMODE_SDR25 0x1
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#define EMMC_HOST_UHSMODE_SDR50 0x2
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#define EMMC_HOST_UHSMODE_SDR104 0x3
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#define EMMC_HOST_UHSMODE_DDR50 0x4
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#define EMMC_HOST_UHSMODE_HS400 0x5
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#define EMMC_HOST_CTRL2_1P8V_SIG_EN 1
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#define EMMC_HOST_CTRL2_1P8V_SIG_LOC 3
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#define EMMC_HOST_CTRL2_UHS_MODE_SEL_LOC 0
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#define EMMC_HOST_CTRL2_UHS_MODE_SEL_MASK 0x07
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/* Event/command status */
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#define EMMC_HOST_CMD_COMPLETE BIT(0)
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#define EMMC_HOST_XFER_COMPLETE BIT(1)
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#define EMMC_HOST_BLOCK_GAP_INTR BIT(2)
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#define EMMC_HOST_DMA_INTR BIT(3)
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#define EMMC_HOST_BUF_WR_READY BIT(4)
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#define EMMC_HOST_BUF_RD_READY BIT(5)
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#define EMMC_HOST_CMD_TIMEOUT_ERR BIT(0)
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#define EMMC_HOST_CMD_CRC_ERR BIT(1)
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#define EMMC_HOST_CMD_END_BIT_ERR BIT(2)
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#define EMMC_HOST_CMD_IDX_ERR BIT(3)
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#define EMMC_HOST_DATA_TIMEOUT_ERR BIT(4)
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#define EMMC_HOST_DATA_CRC_ERR BIT(5)
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#define EMMC_HOST_DATA_END_BIT_ERR BIT(6)
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#define EMMC_HOST_CUR_LMT_ERR BIT(7)
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#define EMMC_HOST_DMA_TXFR_ERR BIT(12)
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#define EMMC_HOST_ERR_STATUS 0xFFF
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/** PState register bits */
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#define EMMC_HOST_PSTATE_CMD_INHIBIT BIT(0)
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#define EMMC_HOST_PSTATE_DAT_INHIBIT BIT(1)
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#define EMMC_HOST_PSTATE_DAT_LINE_ACTIVE BIT(2)
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#define EMMC_HOST_PSTATE_WR_DMA_ACTIVE BIT(8)
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#define EMMC_HOST_PSTATE_RD_DMA_ACTIVE BIT(9)
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#define EMMC_HOST_PSTATE_BUF_READ_EN BIT(11)
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#define EMMC_HOST_PSTATE_BUF_WRITE_EN BIT(10)
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#define EMMC_HOST_PSTATE_CARD_INSERTED BIT(16)
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#define EMMC_HOST_MAX_TIMEOUT 0xe
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#define EMMC_HOST_MSEC_DELAY 1000
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/** Constants for Clock Control register */
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#define EMMC_HOST_INTERNAL_CLOCK_EN BIT(0)
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#define EMMC_HOST_INTERNAL_CLOCK_STABLE BIT(1)
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#define EMMC_HOST_SD_CLOCK_EN BIT(2)
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/** Clock frequency */
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#define EMMC_HOST_CLK_FREQ_400K 0.4
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#define EMMC_HOST_CLK_FREQ_25M 25
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#define EMMC_HOST_CLK_FREQ_50M 50
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#define EMMC_HOST_CLK_FREQ_100M 100
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#define EMMC_HOST_CLK_FREQ_200M 200
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#define EMMC_HOST_TUNING_SUCCESS BIT(7)
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#define EMMC_HOST_START_TUNING BIT(6)
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#define EMMC_HOST_VOL_3_3_V_SUPPORT BIT(24)
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#define EMMC_HOST_VOL_3_3_V_SELECT (7 << 1)
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#define EMMC_HOST_VOL_3_0_V_SUPPORT BIT(25)
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#define EMMC_HOST_VOL_3_0_V_SELECT (6 << 1)
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#define EMMC_HOST_VOL_1_8_V_SUPPORT BIT(26)
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#define EMMC_HOST_VOL_1_8_V_SELECT (5 << 1)
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#define EMMC_HOST_CMD_WAIT_TIMEOUT_US 3000
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#define EMMC_HOST_CMD_CMPLETE_TIMEOUT_US 9000
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#define EMMC_HOST_XFR_CMPLETE_TIMEOUT_US 1000
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#define EMMC_HOST_SDMA_BOUNDARY 0x0
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#define EMMC_HOST_RCA_ADDRESS 0x2
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#define EMMC_HOST_RESP_MASK (0xFF000000U)
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#define EMMC_HOST_SET_RESP(resp0, resp1) (resp0 >> 1) | ((resp1 & 1) << 30)
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#define SET_BITS(reg, pos, bit_width, val) \
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reg &= ~(bit_width << pos); \
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reg |= ((val & bit_width) << pos)
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/* get value from certain bit
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*/
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#define GET_BITS(reg_name, start, width) ((reg_name) & (((1 << (width)) - 1) << (start)))
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#define ERR_INTR_STATUS_EVENT(reg_bits) reg_bits << 16
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#define ADDRESS_32BIT_MASK 0xFFFFFFFF
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struct emmc_reg {
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volatile uint32_t sdma_sysaddr; /**< SDMA System Address */
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volatile uint16_t block_size; /**< Block Size */
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volatile uint16_t block_count; /**< Block Count */
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volatile uint32_t argument; /**< Argument */
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volatile uint16_t transfer_mode; /**< Transfer Mode */
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volatile uint16_t cmd; /**< Command */
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volatile uint32_t resp_01; /**< Response Register 0 & 1 */
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volatile uint16_t resp_2; /**< Response Register 2*/
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volatile uint16_t resp_3; /**< Response Register 3 */
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volatile uint16_t resp_4; /**< Response Register 4 */
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volatile uint16_t resp_5; /**< Response Register 5 */
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volatile uint16_t resp_6; /**< Response Register 6 */
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volatile uint16_t resp_7; /**< Response Register 7 */
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volatile uint32_t data_port; /**< Buffer Data Port */
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volatile uint32_t present_state; /**< Present State */
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volatile uint8_t host_ctrl1; /**< Host Control 1 */
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volatile uint8_t power_ctrl; /**< Power Control */
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volatile uint8_t block_gap_ctrl; /**< Block Gap Control */
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volatile uint8_t wake_up_ctrl; /**< Wakeup Control */
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volatile uint16_t clock_ctrl; /**< Clock Control */
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volatile uint8_t timeout_ctrl; /**< Timeout Control */
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volatile uint8_t sw_reset; /**< Software Reset */
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volatile uint16_t normal_int_stat; /**< Normal Interrupt Status */
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volatile uint16_t err_int_stat; /**< Error Interrupt Status */
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volatile uint16_t normal_int_stat_en; /**< Normal Interrupt Status Enable */
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volatile uint16_t err_int_stat_en; /**< Error Interrupt Status Enable */
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volatile uint16_t normal_int_signal_en; /**< Normal Interrupt Signal Enable */
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volatile uint16_t err_int_signal_en; /**< Error Interrupt Signal Enable */
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volatile uint16_t auto_cmd_err_stat; /**< Auto CMD Error Status */
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volatile uint16_t host_ctrl2; /**< Host Control 2 */
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volatile uint64_t capabilities; /**< Capabilities */
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volatile uint64_t max_current_cap; /**< Max Current Capabilities */
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volatile uint16_t force_err_autocmd_stat; /**< Force Event for Auto CMD Error Status*/
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volatile uint16_t force_err_int_stat; /**< Force Event for Error Interrupt Status */
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volatile uint8_t adma_err_stat; /**< ADMA Error Status */
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volatile uint8_t reserved[3];
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volatile uint32_t adma_sys_addr1; /**< ADMA System Address1 */
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volatile uint32_t adma_sys_addr2; /**< ADMA System Address2 */
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volatile uint16_t preset_val_0; /**< Preset Value 0 */
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volatile uint16_t preset_val_1; /**< Preset Value 1 */
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volatile uint16_t preset_val_2; /**< Preset Value 2 */
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volatile uint16_t preset_val_3; /**< Preset Value 3 */
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volatile uint16_t preset_val_4; /**< Preset Value 4 */
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volatile uint16_t preset_val_5; /**< Preset Value 5 */
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volatile uint16_t preset_val_6; /**< Preset Value 6 */
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volatile uint16_t preset_val_7; /**< Preset Value 7 */
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volatile uint32_t boot_timeout; /**< Boot Timeout */
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volatile uint16_t preset_val_8; /**< Preset Value 8 */
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volatile uint16_t reserved3;
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volatile uint16_t vendor_reg; /**< Vendor Enhanced strobe */
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volatile uint16_t reserved4[56];
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volatile uint32_t reserved5[4];
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volatile uint16_t slot_intr_stat; /**< Slot Interrupt Status */
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volatile uint16_t host_cntrl_version; /**< Host Controller Version */
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volatile uint32_t reserved6[64];
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volatile uint32_t cq_ver; /**< Command Queue Version */
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volatile uint32_t cq_cap; /**< Command Queue Capabilities */
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volatile uint32_t cq_cfg; /**< Command Queue Configuration */
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volatile uint32_t cq_ctrl; /**< Command Queue Control */
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volatile uint32_t cq_intr_stat; /**< Command Queue Interrupt Status */
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volatile uint32_t cq_intr_stat_en; /**< Command Queue Interrupt Status Enable */
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volatile uint32_t cq_intr_sig_en; /**< Command Queue Interrupt Signal Enable */
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volatile uint32_t cq_intr_coalesc; /**< Command Queue Interrupt Coalescing */
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volatile uint32_t cq_tdlba; /**< Command Queue Task Desc List Base Addr */
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volatile uint32_t cq_tdlba_upr; /**< Command Queue Task Desc List Base Addr Upr */
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volatile uint32_t cq_task_db; /**< Command Queue Task DoorBell */
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volatile uint32_t cq_task_db_notify; /**< Command Queue Task DoorBell Notify */
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volatile uint32_t cq_dev_qstat; /**< Command Queue Device queue status */
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volatile uint32_t cq_dev_pend_task; /**< Command Queue Device pending tasks */
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volatile uint32_t cq_task_clr; /**< Command Queue Task Clr */
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volatile uint32_t reserved7;
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volatile uint32_t cq_ssc1; /**< Command Queue Send Status Configuration 1 */
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volatile uint32_t cq_ssc2; /**< Command Queue Send Status Configuration 2 */
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volatile uint32_t cq_crdct; /**< Command response for direct command */
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volatile uint32_t reserved8;
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volatile uint32_t cq_rmem; /**< Command response mode error mask */
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volatile uint32_t cq_terri; /**< Command Queue Task Error Information */
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volatile uint32_t cq_cri; /**< Command Queue Command response index */
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volatile uint32_t cq_cra; /**< Command Queue Command response argument */
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volatile uint32_t reserved9[425];
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};
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enum emmc_sw_reset {
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EMMC_HOST_SW_RESET_DATA_LINE = 0,
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EMMC_HOST_SW_RESET_CMD_LINE,
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EMMC_HOST_SW_RESET_ALL
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};
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enum emmc_cmd_type {
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EMMC_HOST_CMD_NORMAL = 0,
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EMMC_HOST_CMD_SUSPEND,
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EMMC_HOST_CMD_RESUME,
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EMMC_HOST_CMD_ABORT,
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};
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enum emmc_response_type {
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EMMC_HOST_RESP_NONE = 0,
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EMMC_HOST_RESP_LEN_136,
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EMMC_HOST_RESP_LEN_48,
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EMMC_HOST_RESP_LEN_48B,
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EMMC_HOST_INVAL_HOST_RESP_LEN,
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};
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struct emmc_cmd_config {
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struct sdhc_command *sdhc_cmd;
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uint32_t cmd_idx;
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enum emmc_cmd_type cmd_type;
|
||||
bool data_present;
|
||||
bool idx_check_en;
|
||||
bool crc_check_en;
|
||||
};
|
||||
|
||||
struct resp {
|
||||
uint64_t resp_48bit;
|
||||
};
|
||||
#endif /* _EMMC_HOST_HC_H_ */
|
||||
8
dts/bindings/sdhc/intel,emmc-host.yaml
Normal file
8
dts/bindings/sdhc/intel,emmc-host.yaml
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# Copyright (c) 2023 Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: eMMC host controller
|
||||
|
||||
compatible: "intel,emmc-host"
|
||||
|
||||
include: [sdhc.yaml, pcie-device.yaml]
|
||||
Loading…
Reference in a new issue