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Merge "Merge arm branch into master"

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This commit is contained in:
Anas Nashif 2017-01-12 18:23:39 +00:00
parent 016e7b2de6 78b00d70e6
commit a1ae7f565b
202 changed files with 2346 additions and 2242 deletions
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10
MAINTAINERS
View file

@ -276,11 +276,6 @@ F: include/kernel.h
F: include/legacy.h
F: tests/kernel/
KINETIS SOFTWARE DEVELOPMENT KIT (KSDK)
M: Maureen Helm <maureen.helm@nxp.com>
S: Supported
F: ext/hal/ksdk/
KNOWN ISSUES
M: Anas Nashif <anas.nashif@intel.com>
M: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
@ -304,6 +299,11 @@ F: ext/lib/crypto/mbedtls/
F: samples/net/mbedtls_sslclient/
F: tests/crypto/test_mbedtls/
MCUXPRESSO SOFTWARE DEVELOPMENT KIT (MCUX)
M: Maureen Helm <maureen.helm@nxp.com>
S: Supported
F: ext/hal/nxp/mcux/
NETWORKING
M: Jukka Rissanen <jukka.rissanen@linux.intel.com>
M: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

23
arch/arm/core/cortex_m/Kconfig
View file

@ -60,16 +60,16 @@ config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
This option signifies the CPU faults other than the hard fault, and
needs to reserve a priority for them.
config CPU_CORTEX_M0_M0PLUS
config ARMV6_M
bool
# Omit prompt to signify "hidden" option
default n
select ATOMIC_OPERATIONS_C
select ISA_THUMB2
help
This option signifies the use of either a Cortex-M0 or Cortex-M0+ CPU.
This option signifies the use of an ARMv6-M processor implementation.
config CPU_CORTEX_M3_M4
config ARMV7_M
bool
# Omit prompt to signify "hidden" option
default n
@ -78,44 +78,41 @@ config CPU_CORTEX_M3_M4
select CPU_CORTEX_M_HAS_BASEPRI
select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
help
This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
This option signifies the use of an ARMv7-M processor implementation.
config CPU_CORTEX_M0
bool
# Omit prompt to signify "hidden" option
select CPU_CORTEX_M0_M0PLUS
select ARMV6_M
help
This option signifies the use of a Cortex-M0 CPU
config CPU_CORTEX_M0PLUS
bool
# Omit prompt to signify "hidden" option
select CPU_CORTEX_M0_M0PLUS
select ARMV6_M
help
This option signifies the use of a Cortex-M0+ CPU
config CPU_CORTEX_M3
bool
# Omit prompt to signify "hidden" option
select CPU_CORTEX_M3_M4
select ARMV7_M
help
This option signifies the use of a Cortex-M3 CPU
config CPU_CORTEX_M4
bool
# Omit prompt to signify "hidden" option
select CPU_CORTEX_M3_M4
select ARMV7_M
help
This option signifies the use of a Cortex-M4 CPU
config CPU_CORTEX_M7
bool
# Omit prompt to signify "hidden" option
select ARMV7_M
default n
select ATOMIC_OPERATIONS_BUILTIN
select ISA_THUMB2
select CPU_CORTEX_M_HAS_BASEPRI
select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
help
This option signifies the use of a Cortex-M7 CPU
@ -211,7 +208,7 @@ config FLASH_BASE_ADDRESS
endmenu
menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
depends on CPU_CORTEX_M0_M0PLUS || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
depends on ARMV6_M || ARMV7_M
config IRQ_OFFLOAD
bool "Enable IRQ offload"

8
arch/arm/core/cortex_m/reset.S
View file

@ -72,12 +72,14 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
#endif
/* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
cpsid i
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_ARMV7_M)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI, r0
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
#ifdef CONFIG_WDOG_INIT
/* board-specific watchdog initialization is necessary */

7
arch/arm/core/cortex_m/scb.c
View file

@ -90,7 +90,8 @@ void sys_arch_reboot(int type)
DO_REBOOT();
}
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
/**
*
* @brief Set the number of priority groups based on the number of exception
@ -135,4 +136,6 @@ void _ScbNumPriGroupSet(unsigned int n)
__scs.scb.aircr.val = reg.val;
}
#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */

8
arch/arm/core/cortex_m/vector_table.S
View file

@ -56,7 +56,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
.word __nmi
.word __hard_fault
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
.word __reserved
.word __reserved
.word __reserved
@ -66,7 +66,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
.word __reserved
.word __reserved /* SVC not used for now (PendSV used instead) */
.word __reserved
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_ARMV7_M)
.word __mpu_fault
.word __bus_fault
.word __usage_fault
@ -76,7 +76,9 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
.word __reserved
.word __svc
.word __debug_monitor
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
.word __reserved
.word __pendsv
#if defined(CONFIG_CORTEX_M_SYSTICK)

7
arch/arm/core/cortex_m/vector_table.h
View file

@ -48,13 +48,16 @@ GTEXT(_vector_table)
GTEXT(__reset)
GTEXT(__nmi)
GTEXT(__hard_fault)
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
GTEXT(__mpu_fault)
GTEXT(__bus_fault)
GTEXT(__usage_fault)
GTEXT(__svc)
GTEXT(__debug_monitor)
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
GTEXT(__pendsv)
GTEXT(__reserved)

96
arch/arm/core/cpu_idle.S
View file

@ -57,10 +57,10 @@ GTEXT(k_cpu_atomic_idle)
*/
SECTION_FUNC(TEXT, _CpuIdleInit)
ldr r1, =_SCB_SCR
movs.n r2, #_SCR_INIT_BITS
str r2, [r1]
bx lr
ldr r1, =_SCB_SCR
movs.n r2, #_SCR_INIT_BITS
str r2, [r1]
bx lr
#ifdef CONFIG_SYS_POWER_MANAGEMENT
@ -78,9 +78,9 @@ SECTION_FUNC(TEXT, _CpuIdleInit)
*/
SECTION_FUNC(TEXT, _NanoIdleValGet)
ldr r0, =_kernel
ldr r0, [r0, #_kernel_offset_to_idle]
bx lr
ldr r0, =_kernel
ldr r0, [r0, #_kernel_offset_to_idle]
bx lr
/**
*
@ -96,10 +96,10 @@ SECTION_FUNC(TEXT, _NanoIdleValGet)
*/
SECTION_FUNC(TEXT, _NanoIdleValClear)
ldr r0, =_kernel
eors.n r1, r1
str r1, [r0, #_kernel_offset_to_idle]
bx lr
ldr r0, =_kernel
eors.n r1, r1
str r1, [r0, #_kernel_offset_to_idle]
bx lr
#endif /* CONFIG_SYS_POWER_MANAGEMENT */
@ -127,17 +127,19 @@ SECTION_FUNC(TEXT, k_cpu_idle)
mov lr, r0
#endif
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
cpsie i
#else /* CONFIG_CPU_CORTEX_M3_M4 */
/* clear BASEPRI so wfi is awakened by incoming interrupts */
eors.n r0, r0
msr BASEPRI, r0
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#if defined(CONFIG_ARMV6_M)
cpsie i
#elif defined(CONFIG_ARMV7_M)
/* clear BASEPRI so wfi is awakened by incoming interrupts */
eors.n r0, r0
msr BASEPRI, r0
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
wfi
wfi
bx lr
bx lr
/**
*
@ -169,38 +171,40 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
mov lr, r1
#endif
/*
* Lock PRIMASK while sleeping: wfe will still get interrupted by incoming
* interrupts but the CPU will not service them right away.
*/
cpsid i
/*
* Lock PRIMASK while sleeping: wfe will still get interrupted by
* incoming interrupts but the CPU will not service them right away.
*/
cpsid i
/*
* No need to set SEVONPEND, it's set once in _CpuIdleInit() and never
* touched again.
*/
/*
* No need to set SEVONPEND, it's set once in _CpuIdleInit() and never
* touched again.
*/
/* r0: interrupt mask from caller */
/* r0: interrupt mask from caller */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
wfe
#if defined(CONFIG_ARMV6_M)
/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
wfe
cmp r0, #0
bne _irq_disabled
cpsie i
cmp r0, #0
bne _irq_disabled
cpsie i
_irq_disabled:
#else /* CONFIG_CPU_CORTEX_M3_M4 */
/* r1: zero, for setting BASEPRI (needs a register) */
eors.n r1, r1
#elif defined(CONFIG_ARMV7_M)
/* r1: zero, for setting BASEPRI (needs a register) */
eors.n r1, r1
/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
msr BASEPRI, r1
/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
msr BASEPRI, r1
wfe
wfe
msr BASEPRI, r0
cpsie i
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
bx lr
msr BASEPRI, r0
cpsie i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
bx lr

36
arch/arm/core/fault.c
View file

@ -69,7 +69,8 @@ void _FaultDump(const NANO_ESF *esf, int fault)
k_current_get(),
esf->pc);
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
int escalation = 0;
if (3 == fault) { /* hard fault */
@ -100,7 +101,9 @@ void _FaultDump(const NANO_ESF *esf, int fault)
/* clear USFR sticky bits */
_ScbUsageFaultAllFaultsReset();
#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
}
#endif
@ -120,7 +123,8 @@ static void _FaultThreadShow(const NANO_ESF *esf)
k_current_get(), esf->pc);
}
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
/**
*
@ -244,7 +248,9 @@ static void _DebugMonitor(const NANO_ESF *esf)
PR_EXC("***** Debug monitor exception (not implemented) *****\n");
}
#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
/**
*
@ -258,9 +264,9 @@ static void _HardFault(const NANO_ESF *esf)
{
PR_EXC("***** HARD FAULT *****\n");
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
_FaultThreadShow(esf);
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_ARMV7_M)
if (_ScbHardFaultIsBusErrOnVectorRead()) {
PR_EXC(" Bus fault on vector table read\n");
} else if (_ScbHardFaultIsForced()) {
@ -273,7 +279,9 @@ static void _HardFault(const NANO_ESF *esf)
_UsageFault(esf);
}
}
#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
}
/**
@ -318,7 +326,8 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
case 3:
_HardFault(esf);
break;
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
case 4:
_MpuFault(esf, 0);
break;
@ -331,7 +340,9 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
case 12:
_DebugMonitor(esf);
break;
#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
default:
_ReservedException(esf, fault);
break;
@ -376,7 +387,10 @@ void _Fault(const NANO_ESF *esf)
*/
void _FaultInit(void)
{
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
_ScbDivByZeroFaultEnable();
#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
}

74
arch/arm/core/fault_s.S
View file

@ -32,12 +32,15 @@ _ASM_FILE_PROLOGUE
GTEXT(_Fault)
GTEXT(__hard_fault)
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
GTEXT(__mpu_fault)
GTEXT(__bus_fault)
GTEXT(__usage_fault)
GTEXT(__debug_monitor)
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
GTEXT(__reserved)
/**
@ -64,49 +67,58 @@ GTEXT(__reserved)
*/
SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault)
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault)
SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault)
SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault)
SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor)
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
/* force unlock interrupts */
cpsie i
#if defined(CONFIG_ARMV6_M)
/* force unlock interrupts */
cpsie i
/* Use EXC_RETURN state to find out if stack frame is on the MSP or PSP */
ldr r0, =0x4
mov r1, lr
tst r1, r0
beq _stack_frame_msp
mrs r0, PSP
bne _stack_frame_endif
/* Use EXC_RETURN state to find out if stack frame is on the
* MSP or PSP
*/
ldr r0, =0x4
mov r1, lr
tst r1, r0
beq _stack_frame_msp
mrs r0, PSP
bne _stack_frame_endif
_stack_frame_msp:
mrs r0, MSP
mrs r0, MSP
_stack_frame_endif:
#else /* CONFIG_CPU_CORTEX_M3_M4 */
/* force unlock interrupts */
eors.n r0, r0
msr BASEPRI, r0
#elif defined(CONFIG_ARMV7_M)
/* force unlock interrupts */
eors.n r0, r0
msr BASEPRI, r0
/* this reimplements _ScbIsNestedExc() */
ldr ip, =_SCS_ICSR
ldr ip, [ip]
ands.w ip, #_SCS_ICSR_RETTOBASE
ldr ip, =_SCS_ICSR
ldr ip, [ip]
ands.w ip, #_SCS_ICSR_RETTOBASE
ite eq /* is the RETTOBASE bit zero ? */
mrseq r0, MSP /* if so, we're not returning to thread mode, thus this
* is a nested exception: the stack frame is on the MSP */
mrsne r0, PSP /* if not, we are returning to thread mode, thus this is
* not a nested exception: the stack frame is on the PSP */
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
mrseq r0, MSP /* if so, we're not returning to thread mode,
* thus this is a nested exception: the stack
* frame is on the MSP */
mrsne r0, PSP /* if not, we are returning to thread mode, thus
* this is not a nested exception: the stack
* frame is on the PSP */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
push {lr}
bl _Fault
push {lr}
bl _Fault
pop {pc}
pop {pc}
.end
.end

26
arch/arm/core/isr_wrapper.S
View file

@ -80,7 +80,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
ldr r0, [r2, #_kernel_offset_to_idle]
cmp r0, #0
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
beq _idle_state_cleared
movs.n r1, #0
/* clear kernel idle state */
@ -88,39 +88,45 @@ SECTION_FUNC(TEXT, _isr_wrapper)
blx _sys_power_save_idle_exit
_idle_state_cleared:
#else
#elif defined(CONFIG_ARMV7_M)
ittt ne
movne r1, #0
/* clear kernel idle state */
strne r1, [r2, #_kernel_offset_to_idle]
blxne _sys_power_save_idle_exit
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
cpsie i /* re-enable interrupts (PRIMASK = 0) */
#endif
mrs r0, IPSR /* get exception number */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
ldr r1, =16
subs r0, r1 /* get IRQ number */
lsls r0, #3 /* table is 8-byte wide */
#else
#elif defined(CONFIG_ARMV7_M)
sub r0, r0, #16 /* get IRQ number */
lsl r0, r0, #3 /* table is 8-byte wide */
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
ldr r1, =_sw_isr_table
add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
* in thumb mode */
* in thumb mode */
ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
blx r3 /* call ISR */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
pop {r3}
mov lr, r3
#else
#elif defined(CONFIG_ARMV7_M)
pop {lr}
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
/* exception return is done in _IntExit() */
b _IntExit

46
arch/arm/core/swap.S
View file

@ -32,9 +32,12 @@
_ASM_FILE_PROLOGUE
GTEXT(_Swap)
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
GTEXT(__svc)
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
GTEXT(__pendsv)
GDATA(_k_neg_eagain)
@ -74,7 +77,7 @@ SECTION_FUNC(TEXT, __pendsv)
/* save callee-saved + psp in TCS */
mrs ip, PSP
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* Store current r4-r7 */
stmea r0!, {r4-r7}
/* copy r8-r12 into r3-r7 */
@ -85,13 +88,15 @@ SECTION_FUNC(TEXT, __pendsv)
mov r7, ip
/* store r8-12 */
stmea r0!, {r3-r7}
#else
#elif defined(CONFIG_ARMV7_M)
stmia r0, {v1-v8, ip}
#ifdef CONFIG_FP_SHARING
add r0, r2, #_thread_offset_to_preempt_float
vstmia r0, {s16-s31}
#endif /* CONFIG_FP_SHARING */
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
/*
* Prepare to clear PendSV with interrupts unlocked, but
@ -104,12 +109,14 @@ SECTION_FUNC(TEXT, __pendsv)
ldr v3, =_SCS_ICSR_UNPENDSV
/* protect the kernel state while we play with the thread lists */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
cpsid i
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_ARMV7_M)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI, r0
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
/* _kernel is still in r1 */
@ -135,7 +142,7 @@ SECTION_FUNC(TEXT, __pendsv)
movs.n r3, #0
str r3, [r2, #_thread_offset_to_basepri]
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* BASEPRI not available, previous interrupt disable state
* maps to PRIMASK.
*
@ -163,7 +170,7 @@ _thread_irq_disabled:
/* restore r4-r7, go back 9*4 bytes to the start of the stored block */
subs r0, #36
ldmia r0!, {r4-r7}
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_ARMV7_M)
/* restore BASEPRI for the incoming thread */
msr BASEPRI, r0
@ -175,14 +182,17 @@ _thread_irq_disabled:
/* load callee-saved + psp from TCS */
add r0, r2, #_thread_offset_to_callee_saved
ldmia r0, {v1-v8, ip}
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
msr PSP, ip
/* exc return */
bx lr
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
/**
*
* @brief Service call handler
@ -237,7 +247,9 @@ _context_switch:
/* handler mode exit, to PendSV */
bx lr
#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
/**
*
@ -290,7 +302,7 @@ SECTION_FUNC(TEXT, _Swap)
ldr r1, [r1]
str r1, [r2, #_thread_offset_to_swap_return_value]
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* No priority-based interrupt masking on M0/M0+,
* pending PendSV is used instead of svc
*/
@ -304,9 +316,11 @@ SECTION_FUNC(TEXT, _Swap)
* of a higher priority pending.
*/
cpsie i
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_ARMV7_M)
svc #0
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
/* coming back from exception, r2 still holds the pointer to _current */
ldr r0, [r2, #_thread_offset_to_swap_return_value]

8
arch/arm/include/cortex_m/exc.h
View file

@ -58,11 +58,13 @@ static ALWAYS_INLINE int _IsInIsr(void)
* On ARMv6-M there is no nested execution bit, so we check exception 3,
* hard fault, to a detect a nested exception.
*/
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
return (vector > 10) || (vector == 3);
#else
#elif defined(CONFIG_ARMV7_M)
return (vector > 10) || (vector && _ScbIsNestedExc());
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
}
/**

8
arch/arm/include/kernel_arch_func.h
View file

@ -67,12 +67,14 @@ _arch_switch_to_main_thread(char *main_stack, size_t main_stack_size,
"msr PSP, %0 \t\n"
/* unlock interrupts */
#ifdef CONFIG_CPU_CORTEX_M0_M0PLUS
#ifdef CONFIG_ARMV6_M
"cpsie i \t\n"
#else
#elif defined(CONFIG_ARMV7_M)
"movs %%r1, #0 \n\t"
"msr BASEPRI, %%r1 \n\t"
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
/* branch to _thread_entry(_main, 0, 0, 0) */
"mov %%r0, %1 \n\t"

19
arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.mk64f12
View file

@ -24,31 +24,24 @@ config SOC
if PINMUX
config PINMUX_KSDK
config PINMUX_MCUX
def_bool y
endif # PINMUX
if PINMUX_DEV
config PINMUX_DEV_KSDK
def_bool y
endif # PINMUX_DEV
config GPIO
def_bool y
if GPIO
config GPIO_K64
config GPIO_MCUX
def_bool y
endif # GPIO
if I2C
config I2C_KSDK
config I2C_MCUX
def_bool y
endif # I2C
@ -72,21 +65,21 @@ endif # SPI
if NET_L2_ETHERNET
config ETH_KSDK
config ETH_MCUX
def_bool y
endif # NET_L2_ETHERNET
if RANDOM_GENERATOR
config RANDOM_KSDK
config RANDOM_MCUX
def_bool y
endif # RANDOM_GENERATOR
if FLASH
config SOC_FLASH_KSDK
config SOC_FLASH_MCUX
def_bool y
endif # FLASH

2
arch/arm/soc/nxp_kinetis/k6x/Kconfig.soc
View file

@ -21,7 +21,7 @@ depends on SOC_SERIES_KINETIS_K6X
config SOC_MK64F12
bool "SOC_MK64F12"
select HAS_KSDK
select HAS_MCUX
select HAS_OSC
select HAS_MCG
select HAS_RNGA

7
arch/arm/soc/nxp_kinetis/k6x/soc.c
View file

@ -142,7 +142,7 @@ static ALWAYS_INLINE void clkInit(void)
CLOCK_SetSimConfig(&simConfig);
#if CONFIG_ETH_KSDK
#if CONFIG_ETH_MCUX
CLOCK_SetEnetTime0Clock(TIMESRC_OSCERCLK);
#endif
}
@ -168,11 +168,6 @@ static int fsl_frdm_k64f_init(struct device *arg)
/* disable interrupts */
oldLevel = irq_lock();
/* enable the port clocks */
SIM->SCGC5 |= (SIM_SCGC5_PORTA(1) | SIM_SCGC5_PORTB(1) |
SIM_SCGC5_PORTC(1) | SIM_SCGC5_PORTD(1) |
SIM_SCGC5_PORTE(1));
/* release I/O power hold to allow normal run state */
PMC->REGSC |= PMC_REGSC_ACKISO_MASK;

48
arch/arm/soc/nxp_kinetis/k6x/soc.h
View file

@ -179,45 +179,6 @@ extern "C" {
#endif /* CONFIG_UART_K20 */
/* Uart console settings */
#if defined(CONFIG_UART_CONSOLE)
#define CONFIG_UART_CONSOLE_PORT PCR_PORT_B
#define CONFIG_UART_CONSOLE_PORT_RX_PIN 16
#define CONFIG_UART_CONSOLE_PORT_TX_PIN 17
#define CONFIG_UART_CONSOLE_PORT_MUX_FUNC PCR_MUX_ALT3
#define CONFIG_UART_CONSOLE_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#endif /* CONFIG_UART_CONSOLE */
/*
* GPIO configuration settings
*/
#if defined(CONFIG_GPIO_K64)
#define GPIO_K64_A_BASE_ADDR 0x400FF000
#define GPIO_K64_A_IRQ IRQ_GPIO_PORTA
#define GPIO_K64_B_BASE_ADDR 0x400FF040
#define GPIO_K64_B_IRQ IRQ_GPIO_PORTB
#define GPIO_K64_C_BASE_ADDR 0x400FF080
#define GPIO_K64_C_IRQ IRQ_GPIO_PORTC
#define GPIO_K64_D_BASE_ADDR 0x400FF0C0
#define GPIO_K64_D_IRQ IRQ_GPIO_PORTD
#define GPIO_K64_E_BASE_ADDR 0x400FF100
#define GPIO_K64_E_IRQ IRQ_GPIO_PORTE
#endif /* CONFIG_GPIO_K64 */
#define PORT_K64_A_BASE_ADDR 0x40049000
#define PORT_K64_B_BASE_ADDR 0x4004A000
#define PORT_K64_C_BASE_ADDR 0x4004B000
#define PORT_K64_D_BASE_ADDR 0x4004C000
#define PORT_K64_E_BASE_ADDR 0x4004D000
/*
* PWM/FTM configuration settings
*/
@ -251,15 +212,6 @@ extern "C" {
#endif /* CONFIG_SPI_K64 */
/*
* PINMUX configuration settings
*/
#if defined(CONFIG_PINMUX)
#define PINMUX_NUM_PINS 160
#endif /* CONFIG_PINMUX */
#endif /* !_ASMLANGUAGE */
#ifdef __cplusplus

41
arch/arm/soc/nxp_kinetis/k6x/soc_config.c
View file

@ -39,44 +39,6 @@
#ifdef CONFIG_UART_K20
#if defined(CONFIG_UART_CONSOLE) && \
(defined(CONFIG_PRINTK) || defined(CONFIG_STDOUT_CONSOLE))
static PORT_Type *const ports[] = PORT_BASE_PTRS;
/**
* @brief Initialize K20 serial port as console
*
* Initialize the UART port for console I/O.
*
* @param dev The UART device struct
*
* @return 0 if successful, otherwise failed.
*/
static ALWAYS_INLINE int uart_k20_console_init(void)
{
PORT_Type *port;
uint32_t rxPin;
uint32_t txPin;
/* Port/pin ctrl module */
port = ports[CONFIG_UART_CONSOLE_PORT];
/* UART0 Rx and Tx pin assignments */
rxPin = CONFIG_UART_CONSOLE_PORT_RX_PIN;
txPin = CONFIG_UART_CONSOLE_PORT_TX_PIN;
/* Enable the UART Rx and Tx Pins */
port->PCR[rxPin] = PORT_PCR_MUX(CONFIG_UART_CONSOLE_PORT_MUX_FUNC);
port->PCR[txPin] = PORT_PCR_MUX(CONFIG_UART_CONSOLE_PORT_MUX_FUNC);
return 0;
}
#else
#define uart_k20_console_init(...)
#endif /* CONFIG_UART_CONSOLE && (CONFIG_PRINTK || CONFIG_STDOUT_CONSOLE) */
static int uart_k20_init(struct device *dev)
{
uint32_t scgc4;
@ -111,9 +73,6 @@ static int uart_k20_init(struct device *dev)
SIM->SCGC1 |= SIM_SCGC1_UART4(1);
#endif
/* Initialize UART port for console if needed */
uart_k20_console_init();
return 0;
}

34
arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f107xc Normal file
View file

@ -0,0 +1,34 @@
# Kconfig - ST Microelectronics STM32F107XC MCU
#
# Copyright (c) 2016 RnDity Sp. z o.o.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_STM32F107XC
config SOC
string
default stm32f107xc
config SRAM_SIZE
default 64
config FLASH_SIZE
default 256
config NUM_IRQS
int
default 68
endif # SOC_STM32F107XC

24
arch/arm/soc/st_stm32/stm32f1/Kconfig.soc
View file

@ -1,6 +1,7 @@
# Kconfig - ST Microelectronics STM32F1 MCU line
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) RnDity Sp. z o.o.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@ -21,8 +22,31 @@ depends on SOC_SERIES_STM32F1X
config SOC_STM32F103XE
bool "STM32F103XE"
select SOC_STM32F10X_DENSITY_DEVICE
config SOC_STM32F103XB
bool "STM32F103XB"
select SOC_STM32F10X_DENSITY_DEVICE
config SOC_STM32F107XC
bool "STM32F107XC"
select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
endchoice
config SOC_STM32F10X_DENSITY_DEVICE
bool
help
* Low density Value line devices
* Medium density Value line devices
* High density Value line devices
* XL-density devices Value line devices
config SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
bool
help
Connectivity line devices are STM32F105xx and STM32F107xx
microcontrollers. They are intended for applications where
connectivity and real-time performances are required such as
industrial control, control panels for security applications, UPS or
home audio. For STM32F107xx also the Ethernet MAC is available.

61
arch/arm/soc/st_stm32/stm32f1/rcc_registers.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -26,9 +27,11 @@
*
* Chapter 7: Low-, medium-, high- and XL-density reset and
* clock control
* Chapter 8: Connectivity line devices: reset and clock control (RCC)
*/
/* 8.3.1 Clock control register (RCC_CR) */
#ifdef CONFIG_SOC_STM32F10X_DENSITY_DEVICE
enum {
STM32F10X_RCC_CFG_PLL_SRC_HSI = 0x0,
STM32F10X_RCC_CFG_PLL_SRC_HSE = 0x1,
@ -38,6 +41,7 @@ enum {
STM32F10X_RCC_CFG_PLL_XTPRE_DIV_0 = 0x0,
STM32F10X_RCC_CFG_PLL_XTPRE_DIV_2 = 0x1,
};
#endif
enum {
STM32F10X_RCC_CFG_SYSCLK_SRC_HSI = 0x0,
@ -65,6 +69,37 @@ enum {
STM32F10X_RCC_CFG_SYSCLK_DIV_512 = 0xf,
};
#ifdef CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
enum {
STM32F10X_RCC_CFG_PLL_SRC_HSI = 0x0,
STM32F10X_RCC_CFG_PLL_SRC_PREDIV1 = 0x1,
};
enum {
STM32F10X_RCC_CFG2_PREDIV1_SRC_HSE = 0x0,
STM32F10X_RCC_CFG2_PREDIV1_SRC_PLL2 = 0x1,
};
enum {
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_0 = 0x0,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_2 = 0x1,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_3 = 0x2,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_4 = 0x3,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_5 = 0x4,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_6 = 0x5,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_7 = 0x6,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_8 = 0x7,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_9 = 0x8,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_10 = 0x9,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_11 = 0xa,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_12 = 0xb,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_13 = 0xc,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_14 = 0xd,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_15 = 0xe,
STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_16 = 0xf
};
#endif
/**
* @brief Reset and Clock Control
*/
@ -84,7 +119,15 @@ union __rcc_cr {
uint32_t rsvd__20_23 :4 __packed;
uint32_t pllon :1 __packed;
uint32_t pllrdy :1 __packed;
#if CONFIG_SOC_STM32F10X_DENSITY_DEVICE
uint32_t rsvd__26_31 :6 __packed;
#elif CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
uint32_t pll2on :1 __packed;
uint32_t pll2rdy :1 __packed;
uint32_t pll3on :1 __packed;
uint32_t pll3rdy :1 __packed;
uint32_t rsvd__30_31 :2 __packed;
#endif
} bit;
};
@ -107,6 +150,20 @@ union __rcc_cfgr {
} bit;
};
union __rcc_cfgr2 {
uint32_t val;
struct {
uint32_t prediv1 :4 __packed;
uint32_t prediv2 :4 __packed;
uint32_t pll2mul :4 __packed;
uint32_t pll3mul :4 __packed;
uint32_t prediv1src :1 __packed;
uint32_t i2s2sr :1 __packed;
uint32_t i2s3sr :1 __packed;
uint32_t rsvd__19_31 :13 __packed;
} bit;
};
struct stm32f10x_rcc {
union __rcc_cr cr;
union __rcc_cfgr cfgr;
@ -118,6 +175,10 @@ struct stm32f10x_rcc {
uint32_t apb1enr;
uint32_t bdcr;
uint32_t csr;
#ifdef CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
uint32_t ahbrstr;
union __rcc_cfgr2 cfgr2;
#endif
};
#endif /* _STM32F10X_CLOCK_H_ */

18
arch/arm/soc/st_stm32/stm32f4/flash_registers.h
View file

@ -72,14 +72,30 @@ static inline void __setup_flash(void)
if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 30000000) {
regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_0;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) {
}
#ifdef CONFIG_SOC_STM32F401XE
else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) {
regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 84000000) {
regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
}
#elif CONFIG_SOC_STM32F411XE
else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 64000000) {
regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) {
regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 100000000) {
regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3;
}
#else
else {
__ASSERT(0, "Flash latency not set");
}
#endif
/* Make sure latency was set */
tmpreg = regs->acr.bit.latency;
}
#endif /* _STM32F4X_FLASHREGISTERS_H_ */

3
arch/arm/soc/ti_simplelink/cc32xx/Kconfig.defconfig.cc3200
View file

@ -20,9 +20,6 @@ config FLASH_SIZE
config CC3200SDK_LIBRARY
def_bool n
config CC3200SDK_INSTALL_PATH
default ""
config NUM_IRQS
int
# must be >= the highest interrupt number used

2
boards/arm/cc3200_launchxl/cc3200_launchxl_defconfig
View file

@ -22,4 +22,4 @@ CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable CC3200 SDK driver files
CONFIG_CC3200SDK_BUILTIN=y
CONFIG_CC3200SDK_ROM_DRIVERLIB=y

40
boards/arm/frdm_k64f/Kconfig.defconfig
View file

@ -93,43 +93,43 @@ config BLUETOOTH_UART_ON_DEV_NAME
config PINMUX
def_bool y
if PINMUX_KSDK
if PINMUX_MCUX
config PINMUX_KSDK_PORTA
config PINMUX_MCUX_PORTA
def_bool y
config PINMUX_KSDK_PORTB
config PINMUX_MCUX_PORTB
def_bool y
config PINMUX_KSDK_PORTC
config PINMUX_MCUX_PORTC
def_bool y
config PINMUX_KSDK_PORTD
config PINMUX_MCUX_PORTD
def_bool y if SPI_0
config PINMUX_MCUX_PORTE
def_bool y
config PINMUX_KSDK_PORTE
endif # PINMUX_MCUX
if GPIO_MCUX
config GPIO_MCUX_PORTA
def_bool y
endif # PINMUX_KSDK
if GPIO_K64
config GPIO_K64_A
config GPIO_MCUX_PORTB
def_bool y
config GPIO_K64_B
config GPIO_MCUX_PORTC
def_bool y
config GPIO_K64_C
config GPIO_MCUX_PORTD
def_bool y
config GPIO_K64_D
config GPIO_MCUX_PORTE
def_bool y
config GPIO_K64_E
def_bool y
endif # GPIO_K64
endif # GPIO_MCUX
if I2C
@ -170,7 +170,7 @@ config FXOS8700_I2C_ADDRESS
default 0x1d
config FXOS8700_GPIO_NAME
default GPIO_K64_C_DEV_NAME
default GPIO_MCUX_PORTC_NAME
config FXOS8700_GPIO_PIN
default 13
@ -208,7 +208,7 @@ endif # SPI
if NET_L2_ETHERNET
config ETH_KSDK_0
config ETH_MCUX_0
def_bool y
endif # NET_L2_ETHERNET

2
boards/arm/frdm_k64f/Makefile
View file

@ -1,3 +1,3 @@
ccflags-y +=-I$(srctree)/drivers
obj-$(CONFIG_PINMUX_KSDK) += pinmux.o
obj-$(CONFIG_PINMUX_MCUX) += pinmux.o

10
boards/arm/frdm_k64f/board.h
View file

@ -20,23 +20,23 @@
#include <soc.h>
/* Push button switch 2 */
#define SW2_GPIO_NAME CONFIG_GPIO_K64_C_DEV_NAME
#define SW2_GPIO_NAME CONFIG_GPIO_MCUX_PORTC_NAME
#define SW2_GPIO_PIN 6
/* Push button switch 3 */
#define SW3_GPIO_NAME CONFIG_GPIO_K64_A_DEV_NAME
#define SW3_GPIO_NAME CONFIG_GPIO_MCUX_PORTA_NAME
#define SW3_GPIO_PIN 4
/* Red LED */
#define RED_GPIO_NAME CONFIG_GPIO_K64_B_DEV_NAME
#define RED_GPIO_NAME CONFIG_GPIO_MCUX_PORTB_NAME
#define RED_GPIO_PIN 22
/* Green LED */
#define GREEN_GPIO_NAME CONFIG_GPIO_K64_E_DEV_NAME
#define GREEN_GPIO_NAME CONFIG_GPIO_MCUX_PORTE_NAME
#define GREEN_GPIO_PIN 26
/* Blue LED */
#define BLUE_GPIO_NAME CONFIG_GPIO_K64_B_DEV_NAME
#define BLUE_GPIO_NAME CONFIG_GPIO_MCUX_PORTB_NAME
#define BLUE_GPIO_PIN 21
/* LED0. There is no physical LED on the board with this name, so create an

92
boards/arm/frdm_k64f/pinmux.c
View file

@ -15,69 +15,97 @@
*/
#include <init.h>
#include <pinmux/pinmux_ksdk.h>
#include <pinmux.h>
#include <fsl_port.h>
static int frdm_k64f_pinmux_init(struct device *dev)
{
ARG_UNUSED(dev);
pinmux_ksdk_init();
#ifdef CONFIG_PINMUX_MCUX_PORTA
struct device *porta =
device_get_binding(CONFIG_PINMUX_MCUX_PORTA_NAME);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTB
struct device *portb =
device_get_binding(CONFIG_PINMUX_MCUX_PORTB_NAME);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTC
struct device *portc =
device_get_binding(CONFIG_PINMUX_MCUX_PORTC_NAME);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTD
struct device *portd =
device_get_binding(CONFIG_PINMUX_MCUX_PORTD_NAME);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTE
struct device *porte =
device_get_binding(CONFIG_PINMUX_MCUX_PORTE_NAME);
#endif
#ifdef CONFIG_UART_K20_PORT_0
/* UART0 RX, TX */
pinmux_pin_set(portb, 16, PORT_PCR_MUX(kPORT_MuxAlt3));
pinmux_pin_set(portb, 17, PORT_PCR_MUX(kPORT_MuxAlt3));
#endif
#ifdef CONFIG_UART_K20_PORT_3
/* UART3 RX, TX */
pinmux_ksdk_set(PORTC, 16, PORT_PCR_MUX(kPORT_MuxAlt3));
pinmux_ksdk_set(PORTC, 17, PORT_PCR_MUX(kPORT_MuxAlt3));
pinmux_pin_set(portc, 16, PORT_PCR_MUX(kPORT_MuxAlt3));
pinmux_pin_set(portc, 17, PORT_PCR_MUX(kPORT_MuxAlt3));
#endif
/* SW2 / FXOS8700 INT1 */
pinmux_ksdk_set(PORTC, 6, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_pin_set(portc, 6, PORT_PCR_MUX(kPORT_MuxAsGpio));
/* FXOS8700 INT2 */
pinmux_pin_set(portc, 13, PORT_PCR_MUX(kPORT_MuxAsGpio));
/* SW3 */
pinmux_ksdk_set(PORTA, 4, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_pin_set(porta, 4, PORT_PCR_MUX(kPORT_MuxAsGpio));
/* Red, green, blue LEDs */
pinmux_ksdk_set(PORTB, 22, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_ksdk_set(PORTE, 26, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_ksdk_set(PORTB, 21, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_pin_set(portb, 22, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_pin_set(porte, 26, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_pin_set(portb, 21, PORT_PCR_MUX(kPORT_MuxAsGpio));
#ifdef CONFIG_SPI_0
/* SPI0 CS0, SCK, SOUT, SIN */
pinmux_ksdk_set(PORTD, 0, PORT_PCR_MUX(kPORT_MuxAlt2));
pinmux_ksdk_set(PORTD, 1, PORT_PCR_MUX(kPORT_MuxAlt2));
pinmux_ksdk_set(PORTD, 2, PORT_PCR_MUX(kPORT_MuxAlt2));
pinmux_ksdk_set(PORTD, 3, PORT_PCR_MUX(kPORT_MuxAlt2));
pinmux_pin_set(portd, 0, PORT_PCR_MUX(kPORT_MuxAlt2));
pinmux_pin_set(portd, 1, PORT_PCR_MUX(kPORT_MuxAlt2));
pinmux_pin_set(portd, 2, PORT_PCR_MUX(kPORT_MuxAlt2));
pinmux_pin_set(portd, 3, PORT_PCR_MUX(kPORT_MuxAlt2));
#endif
#if CONFIG_I2C_0
/* I2C0 SCL, SDA */
pinmux_ksdk_set(PORTE, 24, PORT_PCR_MUX(kPORT_MuxAlt5)
pinmux_pin_set(porte, 24, PORT_PCR_MUX(kPORT_MuxAlt5)
| PORT_PCR_ODE_MASK);
pinmux_ksdk_set(PORTE, 25, PORT_PCR_MUX(kPORT_MuxAlt5)
pinmux_pin_set(porte, 25, PORT_PCR_MUX(kPORT_MuxAlt5)
| PORT_PCR_ODE_MASK);
#endif
#if CONFIG_ETH_KSDK_0
pinmux_ksdk_set(PORTA, 5, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTA, 12, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTA, 13, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTA, 14, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTA, 15, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTA, 16, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTA, 17, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTA, 28, PORT_PCR_MUX(kPORT_MuxAlt4));
#if CONFIG_ETH_MCUX_0
pinmux_pin_set(porta, 5, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(porta, 12, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(porta, 13, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(porta, 14, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(porta, 15, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(porta, 16, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(porta, 17, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(porta, 28, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTB, 0, PORT_PCR_MUX(kPORT_MuxAlt4)
pinmux_pin_set(portb, 0, PORT_PCR_MUX(kPORT_MuxAlt4)
| PORT_PCR_ODE_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK);
pinmux_ksdk_set(PORTB, 1, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(portb, 1, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTC, 16, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTC, 17, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTC, 18, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_ksdk_set(PORTC, 19, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(portc, 16, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(portc, 17, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(portc, 18, PORT_PCR_MUX(kPORT_MuxAlt4));
pinmux_pin_set(portc, 19, PORT_PCR_MUX(kPORT_MuxAlt4));
#endif
return 0;
}
SYS_INIT(frdm_k64f_pinmux_init, PRE_KERNEL_1,
CONFIG_PINMUX_INIT_PRIORITY);
SYS_INIT(frdm_k64f_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY);

52
boards/arm/hexiwear_k64/Kconfig.defconfig
View file

@ -93,43 +93,43 @@ config BLUETOOTH_UART_ON_DEV_NAME
config PINMUX
def_bool y
if PINMUX_KSDK
if PINMUX_MCUX
config PINMUX_KSDK_PORTA
config PINMUX_MCUX_PORTA
def_bool n
config PINMUX_MCUX_PORTB
def_bool y if UART_K20_PORT_0
config PINMUX_MCUX_PORTC
def_bool y
config PINMUX_KSDK_PORTB
config PINMUX_MCUX_PORTD
def_bool y
config PINMUX_KSDK_PORTC
config PINMUX_MCUX_PORTE
def_bool y if UART_K20_PORT_4
endif # PINMUX_MCUX
if GPIO_MCUX
config GPIO_MCUX_PORTA
def_bool n
config GPIO_MCUX_PORTB
def_bool y
config PINMUX_KSDK_PORTD
config GPIO_MCUX_PORTC
def_bool y
config PINMUX_KSDK_PORTE
config GPIO_MCUX_PORTD
def_bool y
endif # PINMUX_KSDK
if GPIO_K64
config GPIO_K64_A
config GPIO_MCUX_PORTE
def_bool y
config GPIO_K64_B
def_bool y
config GPIO_K64_C
def_bool y
config GPIO_K64_D
def_bool y
config GPIO_K64_E
def_bool y
endif # GPIO_K64
endif # GPIO_MCUX
if I2C
@ -170,7 +170,7 @@ config FXOS8700_I2C_ADDRESS
default 0x1e
config FXOS8700_GPIO_NAME
default GPIO_K64_D_DEV_NAME
default GPIO_MCUX_PORTD_NAME
config FXOS8700_GPIO_PIN
default 13
@ -208,7 +208,7 @@ endif # SPI
if ETHERNET
config ETH_KSDK_0
config ETH_MCUX_0
def_bool y
endif # ETHERNET

2
boards/arm/hexiwear_k64/Makefile
View file

@ -17,4 +17,4 @@
ccflags-y +=-I$(srctree)/drivers
obj-$(CONFIG_PINMUX_KSDK) += pinmux.o
obj-$(CONFIG_PINMUX_MCUX) += pinmux.o

6
boards/arm/hexiwear_k64/board.h
View file

@ -20,15 +20,15 @@
#include <soc.h>
/* Red LED */
#define RED_GPIO_NAME CONFIG_GPIO_K64_C_DEV_NAME
#define RED_GPIO_NAME CONFIG_GPIO_MCUX_PORTC_NAME
#define RED_GPIO_PIN 8
/* Green LED */
#define GREEN_GPIO_NAME CONFIG_GPIO_K64_D_DEV_NAME
#define GREEN_GPIO_NAME CONFIG_GPIO_MCUX_PORTD_NAME
#define GREEN_GPIO_PIN 0
/* Blue LED */
#define BLUE_GPIO_NAME CONFIG_GPIO_K64_C_DEV_NAME
#define BLUE_GPIO_NAME CONFIG_GPIO_MCUX_PORTC_NAME
#define BLUE_GPIO_PIN 9
/* LED0. There is no physical LED on the board with this name, so create an

51
boards/arm/hexiwear_k64/pinmux.c
View file

@ -15,37 +15,62 @@
*/
#include <init.h>
#include <pinmux/pinmux_ksdk.h>
#include <pinmux.h>
#include <fsl_port.h>
static int hexiwear_k64_pinmux_init(struct device *dev)
{
ARG_UNUSED(dev);
pinmux_ksdk_init();
#ifdef CONFIG_PINMUX_MCUX_PORTA
struct device *porta =
device_get_binding(CONFIG_PINMUX_MCUX_PORTA_NAME);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTB
struct device *portb =
device_get_binding(CONFIG_PINMUX_MCUX_PORTB_NAME);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTC
struct device *portc =
device_get_binding(CONFIG_PINMUX_MCUX_PORTC_NAME);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTD
struct device *portd =
device_get_binding(CONFIG_PINMUX_MCUX_PORTD_NAME);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTE
struct device *porte =
device_get_binding(CONFIG_PINMUX_MCUX_PORTE_NAME);
#endif
/* Red, green, blue LEDs */
pinmux_ksdk_set(PORTC, 8, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_ksdk_set(PORTC, 9, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_ksdk_set(PORTD, 0, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_pin_set(portc, 8, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_pin_set(portc, 9, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_pin_set(portd, 0, PORT_PCR_MUX(kPORT_MuxAsGpio));
#if CONFIG_I2C_1
/* I2C1 SCL, SDA - accel/mag, gyro, pressure */
pinmux_ksdk_set(PORTC, 10, PORT_PCR_MUX(kPORT_MuxAlt5)
pinmux_pin_set(portc, 10, PORT_PCR_MUX(kPORT_MuxAlt2)
| PORT_PCR_ODE_MASK);
pinmux_ksdk_set(PORTC, 11, PORT_PCR_MUX(kPORT_MuxAlt5)
pinmux_pin_set(portc, 11, PORT_PCR_MUX(kPORT_MuxAlt2)
| PORT_PCR_ODE_MASK);
#endif
/* FXOS8700 INT1 */
pinmux_ksdk_set(PORTC, 1, PORT_PCR_MUX(kPORT_MuxAsGpio));
/* FXOS8700 INT2 */
pinmux_pin_set(portd, 13, PORT_PCR_MUX(kPORT_MuxAsGpio));
#ifdef CONFIG_UART_K20_PORT_0
/* UART0 RX, TX */
pinmux_pin_set(portb, 16, PORT_PCR_MUX(kPORT_MuxAlt3));
pinmux_pin_set(portb, 17, PORT_PCR_MUX(kPORT_MuxAlt3));
#endif
#ifdef CONFIG_UART_K20_PORT_4
/* UART4 RX, TX - BLE */
pinmux_ksdk_set(PORTE, 24, PORT_PCR_MUX(kPORT_MuxAlt3));
pinmux_ksdk_set(PORTE, 25, PORT_PCR_MUX(kPORT_MuxAlt3));
pinmux_pin_set(porte, 24, PORT_PCR_MUX(kPORT_MuxAlt3));
pinmux_pin_set(porte, 25, PORT_PCR_MUX(kPORT_MuxAlt3));
#endif
return 0;
}
SYS_INIT(hexiwear_k64_pinmux_init, PRE_KERNEL_1,
CONFIG_PINMUX_INIT_PRIORITY);
SYS_INIT(hexiwear_k64_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY);

18
boards/arm/nucleo_f103rb/board.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2015 Intel Corporation
* Copyright (c) 2017 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -19,13 +20,18 @@
#include <soc.h>
/* Push button switch 0 */
#define SW0_GPIO_PIN 13
#define SW0_GPIO_NAME "GPIOC"
/* USER push button */
#define USER_PB_GPIO_PORT "GPIOC"
#define USER_PB_GPIO_PIN 13
/* LD2 green LED */
#define LD2_GPIO_PORT "GPIOA"
#define LD2_GPIO_PIN 5
/* Onboard LED */
#define LED0_GPIO_PORT "GPIOA"
#define LED0_GPIO_PIN 5
/* Create aliases to make the basic samples work */
#define SW0_GPIO_NAME USER_PB_GPIO_PORT
#define SW0_GPIO_PIN USER_PB_GPIO_PIN
#define LED0_GPIO_PORT LD2_GPIO_PORT
#define LED0_GPIO_PIN LD2_GPIO_PIN
#endif /* __INC_BOARD_H */

14
boards/arm/nucleo_f401re/board.h
View file

@ -19,4 +19,18 @@
#include <soc.h>
/* USER push button */
#define USER_PB_GPIO_PORT "GPIOC"
#define USER_PB_GPIO_PIN 13
/* LD2 green LED */
#define LD2_GPIO_PORT "GPIOA"
#define LD2_GPIO_PIN 5
/* Create aliases to make the basic samples work */
#define SW0_GPIO_NAME USER_PB_GPIO_PORT
#define SW0_GPIO_PIN USER_PB_GPIO_PIN
#define LED0_GPIO_PORT LD2_GPIO_PORT
#define LED0_GPIO_PIN LD2_GPIO_PIN
#endif /* __INC_BOARD_H */

15
boards/arm/nucleo_f411re/board.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016 Matthias Boesl
* Copyright (c) 2017 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -19,4 +20,18 @@
#include <soc.h>
/* USER push button */
#define USER_PB_GPIO_PORT "GPIOC"
#define USER_PB_GPIO_PIN 13
/* LD2 green LED */
#define LD2_GPIO_PORT "GPIOA"
#define LD2_GPIO_PIN 5
/* Create aliases to make the basic samples work */
#define SW0_GPIO_NAME USER_PB_GPIO_PORT
#define SW0_GPIO_PIN USER_PB_GPIO_PIN
#define LED0_GPIO_PORT LD2_GPIO_PORT
#define LED0_GPIO_PIN LD2_GPIO_PIN
#endif /* __INC_BOARD_H */

15
boards/arm/nucleo_l476rg/board.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2015 Intel Corporation
* Copyright (c) 2017 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -19,4 +20,18 @@
#include <soc.h>
/* USER push button */
#define USER_PB_GPIO_PORT "GPIOC"
#define USER_PB_GPIO_PIN 13
/* LD2 green LED */
#define LD2_GPIO_PORT "GPIOA"
#define LD2_GPIO_PIN 5
/* Create aliases to make the basic samples work */
#define SW0_GPIO_NAME USER_PB_GPIO_PORT
#define SW0_GPIO_PIN USER_PB_GPIO_PIN
#define LED0_GPIO_PORT LD2_GPIO_PORT
#define LED0_GPIO_PIN LD2_GPIO_PIN
#endif /* __INC_BOARD_H */

20
boards/arm/stm3210c_eval/Kconfig.board Normal file
View file

@ -0,0 +1,20 @@
# Kconfig - STM3210C-EVAL board configuration
#
# Copyright (c) 2016 RnDity Sp. z o.o.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
config BOARD_STM3210C_EVAL
bool "STM3210C-EVAL Evaluation Board"
depends on SOC_STM32F107XC

23
boards/arm/stm3210c_eval/Kconfig.defconfig Normal file
View file

@ -0,0 +1,23 @@
# Kconfig - STM3210C-EVAL board configuration
#
# Copyright (c) 2016 RnDity Sp. z o.o.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if BOARD_STM3210C_EVAL
config BOARD
default stm3210c_eval
endif # BOARD_STM3210C_EVAL

2
boards/arm/stm3210c_eval/Makefile Normal file
View file

@ -0,0 +1,2 @@
# No C files (yet)
obj- += dummy.o

6
boards/arm/stm3210c_eval/Makefile.board Normal file
View file

@ -0,0 +1,6 @@
FLASH_SCRIPT = openocd.sh
OPENOCD_LOAD_CMD = "flash write_image erase ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
export FLASH_SCRIPT OPENOCD_LOAD_CMD OPENOCD_VERIFY_CMD

42
boards/arm/stm3210c_eval/board.h Normal file
View file

@ -0,0 +1,42 @@
/*
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __INC_BOARD_H
#define __INC_BOARD_H
#include <soc.h>
/* User Button. */
#define BTN_USER_GPIO_NAME "GPIOB"
#define BTN_USER_GPIO_PIN 9
/* Push button switch 0. Create an alias to tamper button
* to make the basic button sample work.
*/
#define SW0_GPIO_NAME BTN_USER_GPIO_NAME
#define SW0_GPIO_PIN BTN_USER_GPIO_PIN
/* LED 2 */
#define LED2_GPIO_NAME "GPIOD"
#define LED2_GPIO_PIN 13
/* LED0. Create an alias to the LED2 to make the basic
* blinky sample work.
*/
#define LED0_GPIO_PORT LED2_GPIO_NAME
#define LED0_GPIO_PIN LED2_GPIO_PIN
#endif /* __INC_BOARD_H */

61
boards/arm/stm3210c_eval/stm3210c_eval_defconfig Normal file
View file

@ -0,0 +1,61 @@
# Zephyr Kernel Configuration
CONFIG_ARM=y
CONFIG_ARCH="arm"
CONFIG_SOC_SERIES="stm32f1"
CONFIG_SOC_FAMILY="st_stm32"
CONFIG_BOARD="stm3210c_eval"
CONFIG_SOC_SERIES_STM32F1X=y
# Platform Configuration
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_STM32F107XC=y
CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE=y
CONFIG_BOARD_STM3210C_EVAL=y
# General Kernel Options
CONFIG_CORTEX_M_SYSTICK=y
# 72MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_SERIAL_HAS_DRIVER=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_STM32=y
# enable USART2 - passthrough to STLINK v2 connector
CONFIG_UART_STM32_PORT_2=y
CONFIG_UART_STM32_PORT_2_BAUD_RATE=115200
# enable console on this port by default
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_2"
# Pinmux Driver
CONFIG_PINMUX=y
CONFIG_PINMUX_STM32=y
# GPIO Controller
CONFIG_GPIO=y
CONFIG_GPIO_STM32=y
CONFIG_GPIO_STM32_PORTA=y
CONFIG_GPIO_STM32_PORTB=y
CONFIG_GPIO_STM32_PORTC=y
# RCC configuration
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_STM32F10X=n
CONFIG_CLOCK_CONTROL_STM32F10X_CONN_LINE=y
CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK=y
# use PREDIV1 as PLL input
CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1=y
# however, the board does not have an external oscillator, so just use
# the 8MHz clock signal coming from integrated STLink
CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE=y
CONFIG_CLOCK_STM32F10X_CONN_LINE_HSE_BYPASS=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1=0
CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER=0
# APB1 clock must not to exceed 36MHz limit
CONFIG_CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER=2
CONFIG_CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER=0

12
boards/arm/stm3210c_eval/support/openocd.cfg Normal file
View file

@ -0,0 +1,12 @@
source [find board/st3210c_eval.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}

12
doc/LICENSING.rst
View file

@ -46,18 +46,18 @@ licensing in this document.
*Licensing*: :download:`CMSIS_END_USER_LICENCE_AGREEMENT <../ext/hal/cmsis/CMSIS_END_USER_LICENCE_AGREEMENT.pdf>`
- *ext/hal/ksdk/*
*Origin:* http://kex.nxp.com
*Licensing*: 3-clause BSD (see :download:`source <../ext/hal/ksdk/drivers/fsl_rtc.h>`)
- *ext/hal/nordic/*
*Origin:*
*Licensing*: 3-clause BSD (see :download:`source <../ext/hal/nordic/mdk/nrf51.h>`)
- *ext/hal/nxp/mcux/*
*Origin:* http://mcux.nxp.com
*Licensing*: 3-clause BSD (see :download:`source <../ext/hal/nxp/mcux/drivers/fsl_rtc.h>`)
- *ext/hal/qmsi/*
*Origin:* https://github.com/quark-mcu/qmsi/releases

6
drivers/clock_control/Kconfig
View file

@ -50,13 +50,15 @@ config SYS_LOG_CLOCK_CONTROL_LEVEL
- 4 DEBUG, write SYS_LOG_DBG in adition to previous levels
source "drivers/clock_control/Kconfig.nrf5"
source "drivers/clock_control/Kconfig.quark_se"
source "drivers/clock_control/Kconfig.stm32f10x"
source "drivers/clock_control/Kconfig.stm32f4x"
source "drivers/clock_control/Kconfig.stm32f107xx"
source "drivers/clock_control/Kconfig.nrf5"
source "drivers/clock_control/Kconfig.stm32f4x"
source "drivers/clock_control/Kconfig.stm32l4x"

157
drivers/clock_control/Kconfig.stm32f107xx Normal file
View file

@ -0,0 +1,157 @@
# Kconfig - STM32F1X Connectivity Line MCU clock control driver config
#
# Copyright (c) 2016 RnDity Sp. z o.o.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
menuconfig CLOCK_CONTROL_STM32F10X_CONN_LINE
bool
prompt "STM32F107x Reset & Clock Control"
default y if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
help
Enable driver for Reset & Clock Control subsystem found
in STM32F105/STM32F107 family of MCUs
config CLOCK_CONTROL_STM32F10X_CONN_LINE_DEVICE_INIT_PRIORITY
int "Clock Control Device Priority"
default 1
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
help
This option controls the priority of clock control
device initialization. Higher priority ensures that the device
is initialized earlier in the startup cycle. If unsure, leave
at default value 1
choice
prompt "STM32F10x Connectivity Line System Clock Source"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
config CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSI
bool "HSI"
help
Use HSI as source of SYSCLK
config CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSE
bool "HSE"
help
Use HSE as source of SYSCLK
config CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK
bool "PLLCLK"
help
Use PLLCLK as source of SYSCLK
endchoice
choice
prompt "STM32F10x Connectivity Line PLL Clock Source"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK
config CLOCK_STM32F10X_CONN_LINE_PLL_SRC_HSI
bool "HSI"
help
Use HSI divided by 2 as source of PLL
config CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1
bool "PREDIV1"
help
Use clock from PREDIV1 as source of PLL
endchoice
choice
prompt "STM32F10x Connectivity Line PREDIV1 entry clock source"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1
config CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE
bool "HSE"
help
Use HSE as source of PREDIV1
config CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK
bool "PLL2CLK"
help
Use clock from PLL2CLK as source of PLL
endchoice
config CLOCK_STM32F10X_CONN_LINE_HSE_BYPASS
bool "HSE bypass"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && (CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSE || CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE)
help
Enable this option to bypass external high-speed clock (HSE).
config CLOCK_STM32F10X_CONN_LINE_PREDIV1
int "PREDIV1 Prescler"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1
default 0
range 0 16
help
PREDIV1 is PREDIV1SCR clock signal prescaler, allowed values: 0 - 16.
config CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER
int "PLL multiplier"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK
default 9
range 4 13
help
PLL multiplier, allowed values: 4 - 9 and 13 (in fact the multiplication factor is 6.5).
Values in range 10-12 are reserved. PLL output must not exceed 72MHz.
config CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER
int "PLL2 multiplier"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK
default 8
range 8 20
help
PLL2 multiplier, allowed values: 8 - 20. PLL2 output must not exceed 72MHz.
config CLOCK_STM32F10X_CONN_LINE_PREDIV2
int "PREDIV2 Prescler"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK
default 0
range 0 16
help
PREDIV2 is HSE prescaler, allowed values: 0 - 16.
config CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER
int "AHB prescaler"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
default 0
range 0 512
help
AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
256, 512.
config CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER
int "APB1 prescaler"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
default 0
range 0 16
help
APB1 Low speed clock (PCLK1) prescaler, allowed values:
0, 2, 4, 8, 16. The APB1 clock must not exceed 36MHz.
config CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER
int "APB2 prescaler"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
default 0
range 0 16
help
APB2 High speed clock (PCLK2) prescaler, allowed values:
0, 2, 4, 8, 16
endif

4
drivers/clock_control/Kconfig.stm32f10x
View file

@ -15,12 +15,12 @@
# limitations under the License.
#
if SOC_SERIES_STM32F1X
if SOC_STM32F10X_DENSITY_DEVICE
menuconfig CLOCK_CONTROL_STM32F10X
bool
prompt "STM32F10x Reset & Clock Control"
default y if SOC_SERIES_STM32F1X
default y if SOC_STM32F10X_DENSITY_DEVICE
help
Enable driver for Reset & Clock Control subsystem found
in STM32F1 family of MCUs

3
drivers/clock_control/Makefile
View file

@ -1,6 +1,7 @@
obj-$(CONFIG_CLOCK_CONTROL_NRF5) += nrf5_power_clock.o
obj-$(CONFIG_CLOCK_CONTROL_QUARK_SE) += quark_se_clock_control.o
obj-$(CONFIG_CLOCK_CONTROL_STM32F10X) += stm32f10x_clock.o
obj-$(CONFIG_CLOCK_CONTROL_STM32F10X_CONN_LINE) += stm32f107xx_clock.o
obj-$(CONFIG_CLOCK_CONTROL_STM32F4X) += stm32f4x_clock.o
obj-$(CONFIG_CLOCK_CONTROL_NRF5) += nrf5_power_clock.o
obj-$(CONFIG_CLOCK_CONTROL_STM32L4X) += stm32l4x_clock.o
obj-$(CONFIG_CLOCK_CONTROL_BEETLE) += beetle_clock_control.o

426
drivers/clock_control/stm32f107xx_clock.c Normal file
View file

@ -0,0 +1,426 @@
/*
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @brief Driver for Reset & Clock Control of STM32F10x family processor.
*
* Based on reference manual:
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
* advanced ARM ® -based 32-bit MCUs
*
* Chapter 8: Connectivity line devices: reset and clock control (RCC)
*/
#include <soc.h>
#include <soc_registers.h>
#include <clock_control.h>
#include <misc/util.h>
#include <clock_control/stm32_clock_control.h>
struct stm32f10x_rcc_data {
uint8_t *base;
};
static inline int stm32f10x_clock_control_on(struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32f10x_rcc_data *data = dev->driver_data;
volatile struct stm32f10x_rcc *rcc =
(struct stm32f10x_rcc *)(data->base);
uint32_t subsys = POINTER_TO_UINT(sub_system);
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
subsys &= ~(STM32F10X_CLOCK_APB2_BASE);
rcc->apb2enr |= subsys;
} else {
rcc->apb1enr |= subsys;
}
return 0;
}
static inline int stm32f10x_clock_control_off(struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32f10x_rcc_data *data = dev->driver_data;
volatile struct stm32f10x_rcc *rcc =
(struct stm32f10x_rcc *)(data->base);
uint32_t subsys = POINTER_TO_UINT(sub_system);
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
subsys &= ~(STM32F10X_CLOCK_APB2_BASE);
rcc->apb2enr &= ~subsys;
} else {
rcc->apb1enr &= ~subsys;
}
return 0;
}
/**
* @brief helper for mapping a setting to register value
*/
struct regval_map {
int val;
int reg;
};
static int map_reg_val(const struct regval_map *map, size_t cnt, int val)
{
for (int i = 0; i < cnt; i++) {
if (map[i].val == val) {
return map[i].reg;
}
}
return 0;
}
/**
* @brief map APB prescaler setting to register value
*/
static int apb_prescaler(int prescaler)
{
if (prescaler == 0) {
return STM32F10X_RCC_CFG_HCLK_DIV_0;
}
const struct regval_map map[] = {
{0, STM32F10X_RCC_CFG_HCLK_DIV_0},
{2, STM32F10X_RCC_CFG_HCLK_DIV_2},
{4, STM32F10X_RCC_CFG_HCLK_DIV_4},
{8, STM32F10X_RCC_CFG_HCLK_DIV_8},
{16, STM32F10X_RCC_CFG_HCLK_DIV_16},
};
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
}
/**
* @brief map AHB prescaler setting to register value
*/
static int ahb_prescaler(int prescaler)
{
if (prescaler == 0) {
return STM32F10X_RCC_CFG_SYSCLK_DIV_0;
}
const struct regval_map map[] = {
{0, STM32F10X_RCC_CFG_SYSCLK_DIV_0},
{2, STM32F10X_RCC_CFG_SYSCLK_DIV_2},
{4, STM32F10X_RCC_CFG_SYSCLK_DIV_4},
{8, STM32F10X_RCC_CFG_SYSCLK_DIV_8},
{16, STM32F10X_RCC_CFG_SYSCLK_DIV_16},
{64, STM32F10X_RCC_CFG_SYSCLK_DIV_64},
{128, STM32F10X_RCC_CFG_SYSCLK_DIV_128},
{256, STM32F10X_RCC_CFG_SYSCLK_DIV_256},
{512, STM32F10X_RCC_CFG_SYSCLK_DIV_512},
};
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
}
/**
* @brief select PREDIV division factor
*/
static int prediv_prescaler(int prescaler)
{
if (prescaler == 0) {
return STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_0;
}
const struct regval_map map[] = {
{0, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_0},
{2, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_2},
{3, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_3},
{4, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_4},
{5, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_5},
{6, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_6},
{7, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_7},
{8, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_8},
{9, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_9},
{10, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_10},
{11, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_11},
{12, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_12},
{13, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_13},
{14, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_14},
{15, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_15},
{16, STM32F10X_CONN_LINE_RCC_CFGR2_PREDIV_DIV_16},
};
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
}
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER
/**
* @brief map PLL multiplier setting to register value
*/
static int pllmul(int mul)
{
/* x4 -> 0x2
* x5 -> 0x3
* x6 -> 0x4
* x7 -> 0x5
* x8 -> 0x6
* x9 -> 0x7
* x6.5 -> 0xd
*/
if (mul == 13) {
/* ToDo: do something with 6.5 multiplication */
return 0xd;
} else {
return mul - 2;
}
}
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER
static int pll2mul(int mul)
{
/* x8 -> 0x6
* x9 -> 0x7
* x10 -> 0x8
* x11 -> 0x9
* x12 -> 0xa
* x13 -> 0xb
* x14 -> 0xc
* x16 -> 0xe
* x20 -> 0xf
*/
if (mul == 20) {
return 0xf;
} else {
return mul - 2;
}
}
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER */
static uint32_t get_ahb_clock(uint32_t sysclk)
{
/* AHB clock is generated based on SYSCLK */
uint32_t sysclk_div =
CONFIG_CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER;
if (sysclk_div == 0) {
sysclk_div = 1;
}
return sysclk / sysclk_div;
}
static uint32_t get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
{
if (prescaler == 0) {
prescaler = 1;
}
return ahb_clock / prescaler;
}
static
int stm32f10x_clock_control_get_subsys_rate(struct device *clock,
clock_control_subsys_t sub_system,
uint32_t *rate)
{
ARG_UNUSED(clock);
uint32_t subsys = POINTER_TO_UINT(sub_system);
uint32_t prescaler =
CONFIG_CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER;
/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
uint32_t ahb_clock =
get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
prescaler =
CONFIG_CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER;
}
*rate = get_apb_clock(ahb_clock, prescaler);
return 0;
}
static const struct clock_control_driver_api stm32f10x_clock_control_api = {
.on = stm32f10x_clock_control_on,
.off = stm32f10x_clock_control_off,
.get_rate = stm32f10x_clock_control_get_subsys_rate,
};
/**
* @brief setup embedded flash controller
*
* Configure flash access time latency depending on SYSCLK.
*/
static inline void setup_flash(void)
{
volatile struct stm32f10x_flash *flash =
(struct stm32f10x_flash *)(FLASH_R_BASE);
if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 24000000) {
flash->acr.bit.latency = STM32F10X_FLASH_LATENCY_0;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 48000000) {
flash->acr.bit.latency = STM32F10X_FLASH_LATENCY_1;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 72000000) {
flash->acr.bit.latency = STM32F10X_FLASH_LATENCY_2;
}
}
static int stm32f10x_clock_control_init(struct device *dev)
{
struct stm32f10x_rcc_data *data = dev->driver_data;
volatile struct stm32f10x_rcc *rcc =
(struct stm32f10x_rcc *)(data->base);
/* SYSCLK source defaults to HSI */
int sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSI;
uint32_t hpre =
ahb_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER);
uint32_t ppre1 =
apb_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER);
uint32_t ppre2 =
apb_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER);
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER
uint32_t pll_mul =
pllmul(CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER
uint32_t pll2mul =
pllmul(CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1
uint32_t prediv1 =
prediv_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1 */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2
uint32_t prediv2 =
prediv_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2);
#endif /* CLOCK_STM32F10X_CONN_LINE_PREDIV2 */
/* disable PLLs */
rcc->cr.bit.pllon = 0;
rcc->cr.bit.pll2on = 0;
rcc->cr.bit.pll3on = 0;
/* disable HSE */
rcc->cr.bit.hseon = 0;
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_HSE_BYPASS
/* HSE is disabled, HSE bypass can be enabled*/
rcc->cr.bit.hsebyp = 1;
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_HSE_BYPASS */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_HSI
/* enable HSI clock */
rcc->cr.bit.hsion = 1;
/* this should end after one test */
while (rcc->cr.bit.hsirdy != 1) {
}
/* HSI oscillator clock / 2 selected as PLL input clock */
rcc->cfgr.bit.pllsrc = STM32F10X_RCC_CFG_PLL_SRC_HSI;
#endif /* CONFIG_CLOCK_STM32F10X_PLL_SRC_HSI */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1
/* wait for to become ready */
rcc->cr.bit.hseon = 1;
while (rcc->cr.bit.hserdy != 1) {
}
rcc->cfgr2.bit.prediv1 = prediv1;
/* Clock from PREDIV1 selected as PLL input clock */
rcc->cfgr.bit.pllsrc = STM32F10X_RCC_CFG_PLL_SRC_PREDIV1;
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE
/* HSE oscillator clock selected as PREDIV1 clock entry */
rcc->cfgr2.bit.prediv1src = STM32F10X_RCC_CFG2_PREDIV1_SRC_HSE;
#else
/* PLL2 selected as PREDIV1 clock entry */
rcc->cfgr2.bit.prediv1src = STM32F10X_RCC_CFG2_PREDIV1_SRC_PLL2;
rcc->cfgr2.bit.prediv2 = prediv2;
rcc->cfgr2.bit.pll2mul = pll2mul;
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE */
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1 */
/* setup AHB prescaler */
rcc->cfgr.bit.hpre = hpre;
/* setup APB1, must not exceed 36MHz */
rcc->cfgr.bit.ppre1 = ppre1;
/* setup APB2 */
rcc->cfgr.bit.ppre2 = ppre2;
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSI
/* enable HSI clock */
rcc->cr.bit.hsion = 1;
/* this should end after one test */
while (rcc->cr.bit.hsirdy != 1) {
}
sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSI;
#elif defined(CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_HSE)
/* enable HSE clock */
rcc->cr.bit.hseon = 1;
/* wait for to become ready */
while (rcc->cr.bit.hserdy != 1) {
}
sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSE;
#elif defined(CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK)
/* setup PLL multiplication (PLL must be disabled) */
rcc->cfgr.bit.pllmul = pll_mul;
/* enable PLL */
rcc->cr.bit.pllon = 1;
/* wait for PLL to become ready */
while (rcc->cr.bit.pllrdy != 1) {
}
sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_PLL;
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSI */
/* configure flash access latency before SYSCLK source
* switch
*/
setup_flash();
/* set SYSCLK clock value */
rcc->cfgr.bit.sw = sysclk_src;
/* wait for SYSCLK to switch the source */
while (rcc->cfgr.bit.sws != sysclk_src) {
}
return 0;
}
static struct stm32f10x_rcc_data stm32f10x_rcc_data = {
.base = (uint8_t *)RCC_BASE,
};
/* FIXME: move prescaler/multiplier defines into device config */
/**
* @brief RCC device, note that priority is intentionally set to 1 so
* that the device init runs just after SOC init
*/
DEVICE_AND_API_INIT(rcc_stm32f10x, STM32_CLOCK_CONTROL_NAME,
&stm32f10x_clock_control_init,
&stm32f10x_rcc_data, NULL,
PRE_KERNEL_1,
CONFIG_CLOCK_CONTROL_STM32F10X_CONN_LINE_DEVICE_INIT_PRIORITY,
&stm32f10x_clock_control_api);

2
drivers/ethernet/Kconfig
View file

@ -44,7 +44,7 @@ config ETH_INIT_PRIORITY
so that it can start before the networking sub-system.
source "drivers/ethernet/Kconfig.enc28j60"
source "drivers/ethernet/Kconfig.ksdk"
source "drivers/ethernet/Kconfig.mcux"
source "drivers/ethernet/Kconfig.dw"
endmenu

52
drivers/ethernet/Kconfig.ksdk → drivers/ethernet/Kconfig.mcux
View file

@ -1,4 +1,4 @@
# Kconfig - ETH_KSDK Ethernet driver configuration options
# Kconfig - ETH_MCUX Ethernet driver configuration options
# Copyright (c) 2016 ARM Ltd
#
@ -14,75 +14,75 @@
# See the License for the specific language governing permissions and
# limitations under the License.
menuconfig ETH_KSDK
menuconfig ETH_MCUX
bool
prompt "KSDK Ethernet driver"
depends on NET_L2_ETHERNET && HAS_KSDK
prompt "MCUX Ethernet driver"
depends on NET_L2_ETHERNET && HAS_MCUX
default n
help
Enable KSDK Ethernet driver. Note, this driver performs one shot PHY
Enable MCUX Ethernet driver. Note, this driver performs one shot PHY
setup. There is no support for PHY disconnect, reconnect or
configuration change.
if ETH_KSDK
config ETH_KSDK_RX_BUFFERS
int "Number of KSDK RX buffers"
depends on ETH_KSDK
if ETH_MCUX
config ETH_MCUX_RX_BUFFERS
int "Number of MCUX RX buffers"
depends on ETH_MCUX
default 2
range 1 16
help
Set the number of RX buffers provided to the KSDK driver.
Set the number of RX buffers provided to the MCUX driver.
config ETH_KSDK_TX_BUFFERS
int "Number of KSDK TX buffers"
depends on ETH_KSDK
config ETH_MCUX_TX_BUFFERS
int "Number of MCUX TX buffers"
depends on ETH_MCUX
default 2
range 1 16
help
Set the number of TX buffers provided to the KSDK driver.
Set the number of TX buffers provided to the MCUX driver.
config ETH_KSDK_0
bool "KSDK Ethernet port 0"
config ETH_MCUX_0
bool "MCUX Ethernet port 0"
default n
help
Include port 0 driver
config ETH_KSDK_0_NAME
config ETH_MCUX_0_NAME
string "Driver name"
depends on ETH_KSDK_0
depends on ETH_MCUX_0
default "ETH_0"
config ETH_KSDK_0_IRQ_PRI
config ETH_MCUX_0_IRQ_PRI
int "Controller interrupt priority"
depends on ETH_KSDK_0
depends on ETH_MCUX_0
default 0
help
IRQ priority
config ETH_KSDK_0_RANDOM_MAC
config ETH_MCUX_0_RANDOM_MAC
bool "Random MAC address"
depends on ETH_KSDK_0 && RANDOM_GENERATOR
depends on ETH_MCUX_0 && RANDOM_GENERATOR
default y
help
Generate a random MAC address dynamically.
if ETH_KSDK_0 && ! ETH_KSDK_0_RANDOM_MAC
if ETH_MCUX_0 && ! ETH_MCUX_0_RANDOM_MAC
config ETH_KSDK_0_MAC3
config ETH_MCUX_0_MAC3
hex "MAC Address Byte 3"
default 0
range 0 ff
help
This is the byte 3 of the MAC address.
config ETH_KSDK_0_MAC4
config ETH_MCUX_0_MAC4
hex "MAC Address Byte 4"
default 0
range 0 ff
help
This is the byte 4 of the MAC address.
config ETH_KSDK_0_MAC5
config ETH_MCUX_0_MAC5
hex "MAC Address Byte 5"
default 0
range 0 ff

2
drivers/ethernet/Makefile
View file

@ -1,5 +1,5 @@
ccflags-y += -I${srctree}
obj-$(CONFIG_ETH_DW) += eth_dw.o
obj-$(CONFIG_ETH_KSDK) += eth_ksdk.o
obj-$(CONFIG_ETH_ENC28J60) += eth_enc28j60.o
obj-$(CONFIG_ETH_MCUX) += eth_mcux.o

66
drivers/ethernet/eth_ksdk.c → drivers/ethernet/eth_mcux.c
View file

@ -1,4 +1,4 @@
/* KSDK Ethernet Driver
/* MCUX Ethernet Driver
*
* Copyright (c) 2016 ARM Ltd
* Copyright (c) 2016 Linaro Ltd
@ -18,14 +18,14 @@
/* The driver performs one shot PHY setup. There is no support for
* PHY disconnect, reconnect or configuration change. The PHY setup,
* implemented via KSDK contains polled code that can block the
* implemented via MCUX contains polled code that can block the
* initialization thread for a few seconds.
*
* There is no statistics collection for either normal operation or
* error behaviour.
*/
#define SYS_LOG_DOMAIN "dev/eth_ksdk"
#define SYS_LOG_DOMAIN "dev/eth_mcux"
#define SYS_LOG_LEVEL SYS_LOG_LEVEL_DEBUG
#include <logging/sys_log.h>
@ -46,14 +46,14 @@ struct eth_context {
struct k_sem tx_buf_sem;
uint8_t mac_addr[6];
/* TODO: FIXME. This Ethernet frame sized buffer is used for
* interfacing with KSDK. How it works is that hardware uses
* interfacing with MCUX. How it works is that hardware uses
* DMA scatter buffers to receive a frame, and then public
* KSDK call gathers them into this buffer (there's no other
* MCUX call gathers them into this buffer (there's no other
* public interface). All this happens only for this driver
* to scatter this buffer again into Zephyr fragment buffers.
* This is not efficient, but proper resolution of this issue
* depends on introduction of zero-copy networking support
* in Zephyr, and adding needed interface to KSDK (or
* in Zephyr, and adding needed interface to MCUX (or
* bypassing it and writing a more complex driver working
* directly with hardware).
*/
@ -63,22 +63,22 @@ struct eth_context {
static void eth_0_config_func(void);
static enet_rx_bd_struct_t __aligned(ENET_BUFF_ALIGNMENT)
rx_buffer_desc[CONFIG_ETH_KSDK_TX_BUFFERS];
rx_buffer_desc[CONFIG_ETH_MCUX_TX_BUFFERS];
static enet_tx_bd_struct_t __aligned(ENET_BUFF_ALIGNMENT)
tx_buffer_desc[CONFIG_ETH_KSDK_TX_BUFFERS];
tx_buffer_desc[CONFIG_ETH_MCUX_TX_BUFFERS];
/* Use ENET_FRAME_MAX_VALNFRAMELEN for VLAN frame size
* Use ENET_FRAME_MAX_FRAMELEN for ethernet frame size
*/
#define ETH_KSDK_BUFFER_SIZE \
#define ETH_MCUX_BUFFER_SIZE \
ROUND_UP(ENET_FRAME_MAX_VALNFRAMELEN, ENET_BUFF_ALIGNMENT)
static uint8_t __aligned(ENET_BUFF_ALIGNMENT)
rx_buffer[CONFIG_ETH_KSDK_RX_BUFFERS][ETH_KSDK_BUFFER_SIZE];
rx_buffer[CONFIG_ETH_MCUX_RX_BUFFERS][ETH_MCUX_BUFFER_SIZE];
static uint8_t __aligned(ENET_BUFF_ALIGNMENT)
tx_buffer[CONFIG_ETH_KSDK_TX_BUFFERS][ETH_KSDK_BUFFER_SIZE];
tx_buffer[CONFIG_ETH_MCUX_TX_BUFFERS][ETH_MCUX_BUFFER_SIZE];
static int eth_tx(struct net_if *iface, struct net_buf *buf)
{
@ -98,7 +98,7 @@ static int eth_tx(struct net_if *iface, struct net_buf *buf)
imask = irq_lock();
/* Gather fragment buffers into flat Ethernet frame buffer
* which can be fed to KSDK Ethernet functions. First
* which can be fed to MCUX Ethernet functions. First
* fragment is special - it contains link layer (Ethernet
* in our case) headers and must be treated specially.
*/
@ -256,7 +256,7 @@ static void eth_callback(ENET_Type *base, enet_handle_t *handle,
}
}
#if defined(CONFIG_ETH_KSDK_0_RANDOM_MAC)
#if defined(CONFIG_ETH_MCUX_0_RANDOM_MAC)
static void generate_mac(uint8_t *mac_addr)
{
uint32_t entropy;
@ -279,10 +279,10 @@ static int eth_0_init(struct device *dev)
bool link;
status_t status;
enet_buffer_config_t buffer_config = {
.rxBdNumber = CONFIG_ETH_KSDK_RX_BUFFERS,
.txBdNumber = CONFIG_ETH_KSDK_TX_BUFFERS,
.rxBuffSizeAlign = ETH_KSDK_BUFFER_SIZE,
.txBuffSizeAlign = ETH_KSDK_BUFFER_SIZE,
.rxBdNumber = CONFIG_ETH_MCUX_RX_BUFFERS,
.txBdNumber = CONFIG_ETH_MCUX_TX_BUFFERS,
.rxBuffSizeAlign = ETH_MCUX_BUFFER_SIZE,
.txBuffSizeAlign = ETH_MCUX_BUFFER_SIZE,
.rxBdStartAddrAlign = rx_buffer_desc,
.txBdStartAddrAlign = tx_buffer_desc,
.rxBufferAlign = rx_buffer[0],
@ -290,7 +290,7 @@ static int eth_0_init(struct device *dev)
};
k_sem_init(&context->tx_buf_sem,
CONFIG_ETH_KSDK_TX_BUFFERS, CONFIG_ETH_KSDK_TX_BUFFERS);
CONFIG_ETH_MCUX_TX_BUFFERS, CONFIG_ETH_MCUX_TX_BUFFERS);
sys_clock = CLOCK_GetFreq(kCLOCK_CoreSysClk);
@ -320,7 +320,7 @@ static int eth_0_init(struct device *dev)
SYS_LOG_INF("Link down.");
}
#if defined(CONFIG_ETH_KSDK_0_RANDOM_MAC)
#if defined(CONFIG_ETH_MCUX_0_RANDOM_MAC)
generate_mac(context->mac_addr);
#endif
@ -357,7 +357,7 @@ static struct net_if_api api_funcs_0 = {
.send = eth_tx,
};
static void eth_ksdk_rx_isr(void *p)
static void eth_mcux_rx_isr(void *p)
{
struct device *dev = p;
struct eth_context *context = dev->driver_data;
@ -365,7 +365,7 @@ static void eth_ksdk_rx_isr(void *p)
ENET_ReceiveIRQHandler(ENET, &context->enet_handle);
}
static void eth_ksdk_tx_isr(void *p)
static void eth_mcux_tx_isr(void *p)
{
struct device *dev = p;
struct eth_context *context = dev->driver_data;
@ -373,7 +373,7 @@ static void eth_ksdk_tx_isr(void *p)
ENET_TransmitIRQHandler(ENET, &context->enet_handle);
}
static void eth_ksdk_error_isr(void *p)
static void eth_mcux_error_isr(void *p)
{
struct device *dev = p;
struct eth_context *context = dev->driver_data;
@ -387,30 +387,30 @@ static struct eth_context eth_0_context = {
0x00,
0x04,
0x9f,
#if !defined(CONFIG_ETH_KSDK_0_RANDOM_MAC)
CONFIG_ETH_KSDK_0_MAC3,
CONFIG_ETH_KSDK_0_MAC4,
CONFIG_ETH_KSDK_0_MAC5
#if !defined(CONFIG_ETH_MCUX_0_RANDOM_MAC)
CONFIG_ETH_MCUX_0_MAC3,
CONFIG_ETH_MCUX_0_MAC4,
CONFIG_ETH_MCUX_0_MAC5
#endif
}
};
NET_DEVICE_INIT(eth_ksdk_0, CONFIG_ETH_KSDK_0_NAME,
NET_DEVICE_INIT(eth_mcux_0, CONFIG_ETH_MCUX_0_NAME,
eth_0_init, &eth_0_context,
NULL, CONFIG_ETH_INIT_PRIORITY, &api_funcs_0,
ETHERNET_L2, NET_L2_GET_CTX_TYPE(ETHERNET_L2), 1500);
static void eth_0_config_func(void)
{
IRQ_CONNECT(IRQ_ETH_RX, CONFIG_ETH_KSDK_0_IRQ_PRI,
eth_ksdk_rx_isr, DEVICE_GET(eth_ksdk_0), 0);
IRQ_CONNECT(IRQ_ETH_RX, CONFIG_ETH_MCUX_0_IRQ_PRI,
eth_mcux_rx_isr, DEVICE_GET(eth_mcux_0), 0);
irq_enable(IRQ_ETH_RX);
IRQ_CONNECT(IRQ_ETH_TX, CONFIG_ETH_KSDK_0_IRQ_PRI,
eth_ksdk_tx_isr, DEVICE_GET(eth_ksdk_0), 0);
IRQ_CONNECT(IRQ_ETH_TX, CONFIG_ETH_MCUX_0_IRQ_PRI,
eth_mcux_tx_isr, DEVICE_GET(eth_mcux_0), 0);
irq_enable(IRQ_ETH_TX);
IRQ_CONNECT(IRQ_ETH_ERR_MISC, CONFIG_ETH_KSDK_0_IRQ_PRI,
eth_ksdk_error_isr, DEVICE_GET(eth_ksdk_0), 0);
IRQ_CONNECT(IRQ_ETH_ERR_MISC, CONFIG_ETH_MCUX_0_IRQ_PRI,
eth_mcux_error_isr, DEVICE_GET(eth_mcux_0), 0);
irq_enable(IRQ_ETH_ERR_MISC);
}

16
drivers/flash/Kconfig
View file

@ -132,21 +132,21 @@ config SOC_FLASH_NRF5_DEV_NAME
help
Specify the device name for the flash driver.
config SOC_FLASH_KSDK
bool "KSDK flash shim driver"
depends on FLASH && HAS_KSDK
config SOC_FLASH_MCUX
bool "MCUX flash shim driver"
depends on FLASH && HAS_MCUX
default n
help
Enables the KSDK flash shim driver.
Enables the MCUX flash shim driver.
WARNING: This driver will disable the system interrupts for
the duration of the flash erase/write operations. This will
have an impact on the overall system performance - whether
this is acceptable or not will depend on the use case.
config SOC_FLASH_KSDK_DEV_NAME
string "KSDK flash device name"
depends on SOC_FLASH_KSDK
default "KSDK_FLASH"
config SOC_FLASH_MCUX_DEV_NAME
string "MCUX flash device name"
depends on SOC_FLASH_MCUX
default "MCUX_FLASH"
help
Specify the device name for the flash driver.

2
drivers/flash/Makefile
View file

@ -1,4 +1,4 @@
obj-$(CONFIG_SPI_FLASH_W25QXXDV) += spi_flash_w25qxxdv.o
obj-$(CONFIG_SOC_FLASH_QMSI) += soc_flash_qmsi.o
obj-$(CONFIG_SOC_FLASH_NRF5) += soc_flash_nrf5.o
obj-$(CONFIG_SOC_FLASH_KSDK) += soc_flash_ksdk.o
obj-$(CONFIG_SOC_FLASH_MCUX) += soc_flash_mcux.o

30
drivers/flash/soc_flash_ksdk.c → drivers/flash/soc_flash_mcux.c
View file

@ -32,14 +32,14 @@ struct flash_priv {
/*
* Interrupt vectors could be executed from flash hence the need for locking.
* The underlying KDSK driver takes care of copying the functions to SRAM.
* The underlying MCUX driver takes care of copying the functions to SRAM.
*
* For more information, see the application note below on Read-While-Write
* http://cache.freescale.com/files/32bit/doc/app_note/AN4695.pdf
*
*/
static int flash_ksdk_erase(struct device *dev, off_t offset, size_t len)
static int flash_mcux_erase(struct device *dev, off_t offset, size_t len)
{
struct flash_priv *priv = dev->driver_data;
uint32_t addr;
@ -55,14 +55,14 @@ static int flash_ksdk_erase(struct device *dev, off_t offset, size_t len)
return (rc == kStatus_Success) ? 0 : -EINVAL;
}
static int flash_ksdk_read(struct device *dev, off_t offset,
static int flash_mcux_read(struct device *dev, off_t offset,
void *data, size_t len)
{
struct flash_priv *priv = dev->driver_data;
uint32_t addr;
/*
* The KSDK supports different flash chips whose valid ranges are
* The MCUX supports different flash chips whose valid ranges are
* hidden below the API: until the API export these ranges, we can not
* do any generic validation
*/
@ -73,7 +73,7 @@ static int flash_ksdk_read(struct device *dev, off_t offset,
return 0;
}
static int flash_ksdk_write(struct device *dev, off_t offset,
static int flash_mcux_write(struct device *dev, off_t offset,
const void *data, size_t len)
{
struct flash_priv *priv = dev->driver_data;
@ -90,21 +90,21 @@ static int flash_ksdk_write(struct device *dev, off_t offset,
return (rc == kStatus_Success) ? 0 : -EINVAL;
}
static int flash_ksdk_write_protection(struct device *dev, bool enable)
static int flash_mcux_write_protection(struct device *dev, bool enable)
{
return -EIO;
}
static struct flash_priv flash_data;
static const struct flash_driver_api flash_ksdk_api = {
.write_protection = flash_ksdk_write_protection,
.erase = flash_ksdk_erase,
.write = flash_ksdk_write,
.read = flash_ksdk_read,
static const struct flash_driver_api flash_mcux_api = {
.write_protection = flash_mcux_write_protection,
.erase = flash_mcux_erase,
.write = flash_mcux_write,
.read = flash_mcux_read,
};
static int flash_ksdk_init(struct device *dev)
static int flash_mcux_init(struct device *dev)
{
struct flash_priv *priv = dev->driver_data;
status_t rc;
@ -114,7 +114,7 @@ static int flash_ksdk_init(struct device *dev)
return (rc == kStatus_Success) ? 0 : -EIO;
}
DEVICE_AND_API_INIT(flash_ksdk, CONFIG_SOC_FLASH_KSDK_DEV_NAME,
flash_ksdk_init, &flash_data, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_ksdk_api);
DEVICE_AND_API_INIT(flash_mcux, CONFIG_SOC_FLASH_MCUX_DEV_NAME,
flash_mcux_init, &flash_data, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_mcux_api);

2
drivers/gpio/Kconfig
View file

@ -53,7 +53,7 @@ source "drivers/gpio/Kconfig.qmsi"
source "drivers/gpio/Kconfig.sch"
source "drivers/gpio/Kconfig.k64"
source "drivers/gpio/Kconfig.mcux"
source "drivers/gpio/Kconfig.atmel_sam3"

133
drivers/gpio/Kconfig.k64
View file

@ -1,133 +0,0 @@
# Kconfig.k64 - K64 GPIO configuration options
#
#
# Copyright (c) 2016 Intel Corporation
# Copyright (c) 2016 Wind River Systems, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
menuconfig GPIO_K64
bool "Freescale K64-based GPIO driver"
depends on GPIO && SOC_MK64F12
default n
help
Enable driver for Freescale K64-based GPIOs.
if GPIO_K64
config PORT_K64_INT_STATUS_OFFSET
hex "Freescale K64-based Port Control interrupt status register offset"
default 0xA0
config GPIO_K64_A
bool "Freescale K64-based GPIO Port A"
default n
help
Enable config options for Freescale K64-based GPIO port A.
config GPIO_K64_A_DEV_NAME
string "Freescale K64-based GPIO Port A Device Name"
depends on GPIO_K64_A
default "GPIO_0"
help
Specify the device name.
config GPIO_K64_PORTA_PRI
int "Freescale K64-based Port A interrupt priority"
depends on GPIO_K64_A
default 2
help
K64 Port A IRQ priority
config GPIO_K64_B
bool "Freescale K64-based GPIO Port B"
default n
help
Enable config options for Freescale K64-based GPIO port B.
config GPIO_K64_B_DEV_NAME
string "Freescale K64-based GPIO Port B Device Name"
depends on GPIO_K64_B
default "GPIO_1"
help
Specify the device name.
config GPIO_K64_PORTB_PRI
int "Freescale K64-based Port B interrupt priority"
depends on GPIO_K64_B
default 2
help
K64 Port B IRQ priority
config GPIO_K64_C
bool "Freescale K64-based GPIO Port B"
default n
help
Enable config options for Freescale K64-based GPIO port C.
config GPIO_K64_C_DEV_NAME
string "Freescale K64-based GPIO Port C Device Name"
depends on GPIO_K64_C
default "GPIO_2"
help
Specify the device name.
config GPIO_K64_PORTC_PRI
int "Freescale K64-based Port C interrupt priority"
depends on GPIO_K64_C
default 2
help
K64 Port C IRQ priority
config GPIO_K64_D
bool "Freescale K64-based GPIO Port D"
default n
help
Enable config options for Freescale K64-based GPIO port D.
config GPIO_K64_D_DEV_NAME
string "Freescale K64-based GPIO Port D Device Name"
depends on GPIO_K64_D
default "GPIO_3"
help
Specify the device name.
config GPIO_K64_PORTD_PRI
int "Freescale K64-based Port D interrupt priority"
depends on GPIO_K64_D
default 2
help
K64 Port D IRQ priority
config GPIO_K64_E
bool "Freescale K64-based GPIO Port E"
default n
help
Enable config options for Freescale K64-based GPIO port E.
config GPIO_K64_E_DEV_NAME
string "Freescale K64-based GPIO Port E Device Name"
depends on GPIO_K64_E
default "GPIO_4"
help
Specify the device name.
config GPIO_K64_PORTE_PRI
int "Freescale K64-based Port E interrupt priority"
depends on GPIO_K64_E
default 2
help
K64 Port E IRQ priority
endif # GPIO_K64

113
drivers/gpio/Kconfig.mcux Normal file
View file

@ -0,0 +1,113 @@
# Kconfig.mcux - MCUX GPIO configuration options
#
# Copyright (c) 2016 Freescale Semiconductor, Inc.
# Copyright (c) 2017, NXP Semiconductors, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
menuconfig GPIO_MCUX
bool "MCUX GPIO driver"
depends on GPIO && HAS_MCUX
default n
help
Enable the MCUX pinmux driver.
if GPIO_MCUX
config GPIO_MCUX_PORTA
bool "Port A"
depends on PINMUX_MCUX_PORTA
default n
help
Enable Port A.
config GPIO_MCUX_PORTA_NAME
string "Port A driver name"
depends on GPIO_MCUX_PORTA
default "gpio_porta"
config GPIO_MCUX_PORTA_PRI
int "Port A interrupt priority"
depends on GPIO_MCUX_PORTA
default 2
config GPIO_MCUX_PORTB
bool "Port B"
depends on PINMUX_MCUX_PORTB
default n
help
Enable Port B.
config GPIO_MCUX_PORTB_NAME
string "Port B driver name"
depends on GPIO_MCUX_PORTB
default "gpio_portb"
config GPIO_MCUX_PORTB_PRI
int "Port B interrupt priority"
depends on GPIO_MCUX_PORTB
default 2
config GPIO_MCUX_PORTC
bool "Port C"
depends on PINMUX_MCUX_PORTC
default n
help
Enable Port C.
config GPIO_MCUX_PORTC_NAME
string "Port C driver name"
depends on GPIO_MCUX_PORTC
default "gpio_portc"
config GPIO_MCUX_PORTC_PRI
int "Port C interrupt priority"
depends on GPIO_MCUX_PORTC
default 2
config GPIO_MCUX_PORTD
bool "Port D"
depends on PINMUX_MCUX_PORTD
default n
help
Enable Port D.
config GPIO_MCUX_PORTD_NAME
string "Port D driver name"
depends on GPIO_MCUX_PORTD
default "gpio_portd"
config GPIO_MCUX_PORTD_PRI
int "Port D interrupt priority"
depends on GPIO_MCUX_PORTD
default 2
config GPIO_MCUX_PORTE
bool "Port E"
depends on PINMUX_MCUX_PORTE
default n
help
Enable Port E.
config GPIO_MCUX_PORTE_NAME
string "Port E driver name"
depends on GPIO_MCUX_PORTE
default "gpio_porte"
config GPIO_MCUX_PORTE_PRI
int "Port E interrupt priority"
depends on GPIO_MCUX_PORTE
default 2
endif # GPIO_MCUX

2
drivers/gpio/Makefile
View file

@ -6,7 +6,7 @@ obj-$(CONFIG_GPIO_SCH) += gpio_sch.o
obj-$(CONFIG_GPIO_QMSI) += gpio_qmsi.o
obj-$(CONFIG_GPIO_QMSI_SS) += gpio_qmsi_ss.o
obj-$(CONFIG_GPIO_ATMEL_SAM3) += gpio_atmel_sam3.o
obj-$(CONFIG_GPIO_K64) += gpio_k64.o
obj-$(CONFIG_GPIO_MCUX) += gpio_mcux.o
obj-$(CONFIG_GPIO_STM32) += gpio_stm32.o
obj-$(CONFIG_GPIO_NRF5) += gpio_nrf5.o
obj-$(CONFIG_GPIO_CMSDK_AHB) += gpio_cmsdk_ahb.o

415
drivers/gpio/gpio_k64.c
View file

@ -1,415 +0,0 @@
/*
* Copyright (c) 2016, Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file Driver for the Freescale K64 GPIO module.
*/
#include <errno.h>
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <gpio.h>
#include <soc.h>
#include <sys_io.h>
#include <pinmux/k64/pinmux.h>
#include "gpio_k64.h"
#include "gpio_utils.h"
static int gpio_k64_config(struct device *dev,
int access_op, uint32_t pin, int flags)
{
const struct gpio_k64_config * const cfg = dev->config->config_info;
uint32_t value;
uint32_t setting;
uint8_t i;
/* check for an invalid pin configuration */
if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
return -ENOTSUP;
}
/*
* Setup direction register:
* 0 - pin is input, 1 - pin is output
*/
if (access_op == GPIO_ACCESS_BY_PIN) {
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
sys_clear_bit((cfg->gpio_base_addr +
GPIO_K64_DIR_OFFSET), pin);
} else { /* GPIO_DIR_OUT */
sys_set_bit((cfg->gpio_base_addr +
GPIO_K64_DIR_OFFSET), pin);
}
} else { /* GPIO_ACCESS_BY_PORT */
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
value = 0x0;
} else { /* GPIO_DIR_OUT */
value = 0xFFFFFFFF;
}
sys_write32(value, (cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET));
}
/*
* Set up pullup/pulldown configuration, in Port Control module:
*/
if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_UP);
} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_DN);
} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_NORMAL) {
setting = K64_PINMUX_PULL_DISABLE;
} else {
return -ENOTSUP;
}
/*
* Set up interrupt configuration, in Port Control module:
*/
if (flags & GPIO_INT) {
/* edge or level */
if (flags & GPIO_INT_EDGE) {
if (flags & GPIO_INT_ACTIVE_HIGH) {
setting |= K64_PINMUX_INT_RISING;
} else if (flags & GPIO_INT_DOUBLE_EDGE) {
setting |= K64_PINMUX_INT_BOTH_EDGE;
} else {
setting |= K64_PINMUX_INT_FALLING;
}
} else { /* GPIO_INT_LEVEL */
if (flags & GPIO_INT_ACTIVE_HIGH) {
setting |= K64_PINMUX_INT_HIGH;
} else {
setting |= K64_PINMUX_INT_LOW;
}
}
}
/* write pull-up/-down and, if set, interrupt configuration settings */
if (access_op == GPIO_ACCESS_BY_PIN) {
value = sys_read32((cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(pin)));
/* clear, then set configuration values */
value &= ~(K64_PINMUX_PULL_EN_MASK | K64_PINMUX_PULL_SEL_MASK);
if (flags & GPIO_INT) {
value &= ~K64_PINMUX_INT_MASK;
}
/* Pins must configured as gpio */
value |= (setting | K64_PINMUX_FUNC_GPIO);
sys_write32(value, (cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(pin)));
} else { /* GPIO_ACCESS_BY_PORT */
for (i = 0; i < K64_PINMUX_NUM_PINS; i++) {
/* clear, then set configuration values */
value = sys_read32((cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(i)));
value &= ~(K64_PINMUX_PULL_EN_MASK |
K64_PINMUX_PULL_SEL_MASK);
if (flags & GPIO_INT) {
value &= ~K64_PINMUX_INT_MASK;
}
/* Pins must configured as gpio */
value |= (setting | K64_PINMUX_FUNC_GPIO);
sys_write32(value, (cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(i)));
}
}
return 0;
}
static int gpio_k64_write(struct device *dev,
int access_op, uint32_t pin, uint32_t value)
{
const struct gpio_k64_config * const cfg = dev->config->config_info;
if (access_op == GPIO_ACCESS_BY_PIN) {
if (value) {
sys_set_bit((cfg->gpio_base_addr +
GPIO_K64_DATA_OUT_OFFSET), pin);
} else {
sys_clear_bit((cfg->gpio_base_addr +
GPIO_K64_DATA_OUT_OFFSET), pin);
}
} else { /* GPIO_ACCESS_BY_PORT */
sys_write32(value, (cfg->gpio_base_addr +
GPIO_K64_DATA_OUT_OFFSET));
}
return 0;
}
static int gpio_k64_read(struct device *dev,
int access_op, uint32_t pin, uint32_t *value)
{
const struct gpio_k64_config * const cfg = dev->config->config_info;
*value = sys_read32((cfg->gpio_base_addr + GPIO_K64_DATA_IN_OFFSET));
if (access_op == GPIO_ACCESS_BY_PIN) {
*value = (*value & BIT(pin)) >> pin;
}
/* nothing more to do for GPIO_ACCESS_BY_PORT */
return 0;
}
static int gpio_k64_manage_callback(struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_k64_data *data = dev->driver_data;
_gpio_manage_callback(&data->callbacks, callback, set);
return 0;
}
static int gpio_k64_enable_callback(struct device *dev,
int access_op, uint32_t pin)
{
struct gpio_k64_data *data = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables |= BIT(pin);
} else {
data->pin_callback_enables = 0xFFFFFFFF;
}
return 0;
}
static int gpio_k64_disable_callback(struct device *dev,
int access_op, uint32_t pin)
{
struct gpio_k64_data *data = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables &= ~BIT(pin);
} else {
data->pin_callback_enables = 0;
}
return 0;
}
/**
* @brief Handler for port interrupts
* @param dev Pointer to device structure for driver instance
*
* @return N/A
*/
static void gpio_k64_port_isr(void *dev)
{
struct device *port = (struct device *)dev;
struct gpio_k64_data *data = port->driver_data;
const struct gpio_k64_config *config = port->config->config_info;
mem_addr_t int_status_reg_addr;
uint32_t enabled_int, int_status;
int_status_reg_addr = config->port_base_addr +
CONFIG_PORT_K64_INT_STATUS_OFFSET;
int_status = sys_read32(int_status_reg_addr);
enabled_int = int_status & data->pin_callback_enables;
_gpio_fire_callbacks(&data->callbacks, port, enabled_int);
/* clear the port interrupts */
sys_write32(0xFFFFFFFF, int_status_reg_addr);
}
static const struct gpio_driver_api gpio_k64_drv_api_funcs = {
.config = gpio_k64_config,
.write = gpio_k64_write,
.read = gpio_k64_read,
.manage_callback = gpio_k64_manage_callback,
.enable_callback = gpio_k64_enable_callback,
.disable_callback = gpio_k64_disable_callback,
};
/* Initialization for Port A */
#ifdef CONFIG_GPIO_K64_A
static int gpio_k64_A_init(struct device *dev);
static const struct gpio_k64_config gpio_k64_A_cfg = {
.gpio_base_addr = GPIO_K64_A_BASE_ADDR,
.port_base_addr = PORT_K64_A_BASE_ADDR,
};
static struct gpio_k64_data gpio_data_A;
DEVICE_AND_API_INIT(gpio_k64_A, CONFIG_GPIO_K64_A_DEV_NAME, gpio_k64_A_init,
&gpio_data_A, &gpio_k64_A_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_k64_drv_api_funcs);
static int gpio_k64_A_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(GPIO_K64_A_IRQ, CONFIG_GPIO_K64_PORTA_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_A), 0);
irq_enable(GPIO_K64_A_IRQ);
return 0;
}
#endif /* CONFIG_GPIO_K64_A */
/* Initialization for Port B */
#ifdef CONFIG_GPIO_K64_B
static int gpio_k64_B_init(struct device *dev);
static const struct gpio_k64_config gpio_k64_B_cfg = {
.gpio_base_addr = GPIO_K64_B_BASE_ADDR,
.port_base_addr = PORT_K64_B_BASE_ADDR,
};
static struct gpio_k64_data gpio_data_B;
DEVICE_AND_API_INIT(gpio_k64_B, CONFIG_GPIO_K64_B_DEV_NAME, gpio_k64_B_init,
&gpio_data_B, &gpio_k64_B_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_k64_drv_api_funcs);
static int gpio_k64_B_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(GPIO_K64_B_IRQ, CONFIG_GPIO_K64_PORTB_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_B), 0);
irq_enable(GPIO_K64_B_IRQ);
return 0;
}
#endif /* CONFIG_GPIO_K64_B */
/* Initialization for Port C */
#ifdef CONFIG_GPIO_K64_C
static int gpio_k64_C_init(struct device *dev);
static const struct gpio_k64_config gpio_k64_C_cfg = {
.gpio_base_addr = GPIO_K64_C_BASE_ADDR,
.port_base_addr = PORT_K64_C_BASE_ADDR,
};
static struct gpio_k64_data gpio_data_C;
DEVICE_AND_API_INIT(gpio_k64_C, CONFIG_GPIO_K64_C_DEV_NAME, gpio_k64_C_init,
&gpio_data_C, &gpio_k64_C_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_k64_drv_api_funcs);
static int gpio_k64_C_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(GPIO_K64_C_IRQ, CONFIG_GPIO_K64_PORTC_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_C), 0);
irq_enable(GPIO_K64_C_IRQ);
return 0;
}
#endif /* CONFIG_GPIO_K64_C */
/* Initialization for Port D */
#ifdef CONFIG_GPIO_K64_D
static int gpio_k64_D_init(struct device *dev);
static const struct gpio_k64_config gpio_k64_D_cfg = {
.gpio_base_addr = GPIO_K64_D_BASE_ADDR,
.port_base_addr = PORT_K64_D_BASE_ADDR,
};
static struct gpio_k64_data gpio_data_D;
DEVICE_AND_API_INIT(gpio_k64_D, CONFIG_GPIO_K64_D_DEV_NAME, gpio_k64_D_init,
&gpio_data_D, &gpio_k64_D_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_k64_drv_api_funcs);
static int gpio_k64_D_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(GPIO_K64_D_IRQ, CONFIG_GPIO_K64_PORTD_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_D), 0);
irq_enable(GPIO_K64_D_IRQ);
return 0;
}
#endif /* CONFIG_GPIO_K64_D */
/* Initialization for Port E */
#ifdef CONFIG_GPIO_K64_E
static int gpio_k64_E_init(struct device *dev);
static const struct gpio_k64_config gpio_k64_E_cfg = {
.gpio_base_addr = GPIO_K64_E_BASE_ADDR,
.port_base_addr = PORT_K64_E_BASE_ADDR,
};
static struct gpio_k64_data gpio_data_E;
DEVICE_AND_API_INIT(gpio_k64_E, CONFIG_GPIO_K64_E_DEV_NAME, gpio_k64_E_init,
&gpio_data_E, &gpio_k64_E_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_k64_drv_api_funcs);
static int gpio_k64_E_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(GPIO_K64_E_IRQ, CONFIG_GPIO_K64_PORTE_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_E), 0);
irq_enable(GPIO_K64_E_IRQ);
return 0;
}
#endif /* CONFIG_GPIO_K64_E */

51
drivers/gpio/gpio_k64.h
View file

@ -1,51 +0,0 @@
/*
* Copyright (c) 2016, Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file Header file for the Freescale K64 GPIO module.
*/
#ifndef _GPIO_K64_H_
#define _GPIO_K64_H_
#include <kernel.h>
#include <gpio.h>
/* GPIO Port Register offsets */
#define GPIO_K64_DATA_OUT_OFFSET 0x00 /* Port Data Output */
#define GPIO_K64_SET_OUT_OFFSET 0x04 /* Port Set Output */
#define GPIO_K64_CLR_OUT_OFFSET 0x08 /* Port Clear Output */
#define GPIO_K64_TOGGLE_OUT_OFFSET 0x0C /* Port Toggle Output */
#define GPIO_K64_DATA_IN_OFFSET 0x10 /* Port Data Input */
#define GPIO_K64_DIR_OFFSET 0x14 /* Port Data Direction */
/** Configuration data */
struct gpio_k64_config {
/* GPIO module base address */
uint32_t gpio_base_addr;
/* Port Control module base address */
uint32_t port_base_addr;
};
struct gpio_k64_data {
/* port ISR callback routine address */
sys_slist_t callbacks;
/* pin callback routine enable flags, by pin number */
uint32_t pin_callback_enables;
};
#endif /* _GPIO_K64_H_ */

373
drivers/gpio/gpio_mcux.c Normal file
View file

@ -0,0 +1,373 @@
/*
* Copyright (c) 2016 Freescale Semiconductor, Inc.
* Copyright (c) 2017, NXP Semiconductors, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <errno.h>
#include <device.h>
#include <gpio.h>
#include <soc.h>
#include <fsl_common.h>
#include <fsl_port.h>
#include "gpio_utils.h"
struct gpio_mcux_config {
GPIO_Type *gpio_base;
PORT_Type *port_base;
};
struct gpio_mcux_data {
/* port ISR callback routine address */
sys_slist_t callbacks;
/* pin callback routine enable flags, by pin number */
uint32_t pin_callback_enables;
};
static int gpio_mcux_configure(struct device *dev,
int access_op, uint32_t pin, int flags)
{
const struct gpio_mcux_config *config = dev->config->config_info;
GPIO_Type *gpio_base = config->gpio_base;
PORT_Type *port_base = config->port_base;
port_interrupt_t port_interrupt = 0;
uint32_t mask = 0;
uint32_t pcr = 0;
uint8_t i;
/* Check for an invalid pin configuration */
if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
return -ENOTSUP;
}
/* The flags contain options that require touching registers in the
* GPIO module and the corresponding PORT module.
*
* Start with the GPIO module and set up the pin direction register.
* 0 - pin is input, 1 - pin is output
*/
if (access_op == GPIO_ACCESS_BY_PIN) {
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
gpio_base->PDDR &= ~BIT(pin);
} else { /* GPIO_DIR_OUT */
gpio_base->PDDR |= BIT(pin);
}
} else { /* GPIO_ACCESS_BY_PORT */
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
gpio_base->PDDR = 0x0;
} else { /* GPIO_DIR_OUT */
gpio_base->PDDR = 0xFFFFFFFF;
}
}
/* Now do the PORT module. Figure out the pullup/pulldown
* configuration, but don't write it to the PCR register yet.
*/
mask |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
/* Enable the pull and select the pullup resistor. */
pcr |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
/* Enable the pull and select the pulldown resistor (deselect
* the pullup resistor.
*/
pcr |= PORT_PCR_PE_MASK;
}
/* Still in the PORT module. Figure out the interrupt configuration,
* but don't write it to the PCR register yet.
*/
mask |= PORT_PCR_IRQC_MASK;
if (flags & GPIO_INT) {
if (flags & GPIO_INT_EDGE) {
if (flags & GPIO_INT_ACTIVE_HIGH) {
port_interrupt = kPORT_InterruptRisingEdge;
} else if (flags & GPIO_INT_DOUBLE_EDGE) {
port_interrupt = kPORT_InterruptEitherEdge;
} else {
port_interrupt = kPORT_InterruptFallingEdge;
}
} else { /* GPIO_INT_LEVEL */
if (flags & GPIO_INT_ACTIVE_HIGH) {
port_interrupt = kPORT_InterruptLogicOne;
} else {
port_interrupt = kPORT_InterruptLogicZero;
}
}
pcr |= PORT_PCR_IRQC(port_interrupt);
}
/* Now we can write the PORT PCR register(s). If accessing by pin, we
* only need to write one PCR register. Otherwise, write all the PCR
* registers in the PORT module (one for each pin).
*/
if (access_op == GPIO_ACCESS_BY_PIN) {
port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
} else { /* GPIO_ACCESS_BY_PORT */
for (i = 0; i < ARRAY_SIZE(port_base->PCR); i++) {
port_base->PCR[i] = (port_base->PCR[pin] & ~mask) | pcr;
}
}
return 0;
}
static int gpio_mcux_write(struct device *dev,
int access_op, uint32_t pin, uint32_t value)
{
const struct gpio_mcux_config *config = dev->config->config_info;
GPIO_Type *gpio_base = config->gpio_base;
if (access_op == GPIO_ACCESS_BY_PIN) {
if (value) {
/* Set the data output for the corresponding pin.
* Writing zeros to the other bits leaves the data
* output unchanged for the other pins.
*/
gpio_base->PSOR = BIT(pin);
} else {
/* Clear the data output for the corresponding pin.
* Writing zeros to the other bits leaves the data
* output unchanged for the other pins.
*/
gpio_base->PCOR = BIT(pin);
}
} else { /* GPIO_ACCESS_BY_PORT */
/* Write the data output for all the pins */
gpio_base->PDOR = value;
}
return 0;
}
static int gpio_mcux_read(struct device *dev,
int access_op, uint32_t pin, uint32_t *value)
{
const struct gpio_mcux_config *config = dev->config->config_info;
GPIO_Type *gpio_base = config->gpio_base;
*value = gpio_base->PDIR;
if (access_op == GPIO_ACCESS_BY_PIN) {
*value = (*value & BIT(pin)) >> pin;
}
/* nothing more to do for GPIO_ACCESS_BY_PORT */
return 0;
}
static int gpio_mcux_manage_callback(struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_mcux_data *data = dev->driver_data;
_gpio_manage_callback(&data->callbacks, callback, set);
return 0;
}
static int gpio_mcux_enable_callback(struct device *dev,
int access_op, uint32_t pin)
{
struct gpio_mcux_data *data = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables |= BIT(pin);
} else {
data->pin_callback_enables = 0xFFFFFFFF;
}
return 0;
}
static int gpio_mcux_disable_callback(struct device *dev,
int access_op, uint32_t pin)
{
struct gpio_mcux_data *data = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables &= ~BIT(pin);
} else {
data->pin_callback_enables = 0;
}
return 0;
}
static void gpio_mcux_port_isr(void *arg)
{
struct device *dev = (struct device *)arg;
const struct gpio_mcux_config *config = dev->config->config_info;
struct gpio_mcux_data *data = dev->driver_data;
uint32_t enabled_int, int_status;
int_status = config->port_base->ISFR;
enabled_int = int_status & data->pin_callback_enables;
_gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
/* Clear the port interrupts */
config->port_base->ISFR = 0xFFFFFFFF;
}
static const struct gpio_driver_api gpio_mcux_driver_api = {
.config = gpio_mcux_configure,
.write = gpio_mcux_write,
.read = gpio_mcux_read,
.manage_callback = gpio_mcux_manage_callback,
.enable_callback = gpio_mcux_enable_callback,
.disable_callback = gpio_mcux_disable_callback,
};
#ifdef CONFIG_GPIO_MCUX_PORTA
static int gpio_mcux_porta_init(struct device *dev);
static const struct gpio_mcux_config gpio_mcux_porta_config = {
.gpio_base = GPIOA,
.port_base = PORTA,
};
static struct gpio_mcux_data gpio_mcux_porta_data;
DEVICE_AND_API_INIT(gpio_mcux_porta, CONFIG_GPIO_MCUX_PORTA_NAME,
gpio_mcux_porta_init,
&gpio_mcux_porta_data, &gpio_mcux_porta_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_mcux_driver_api);
static int gpio_mcux_porta_init(struct device *dev)
{
IRQ_CONNECT(IRQ_GPIO_PORTA, CONFIG_GPIO_MCUX_PORTA_PRI,
gpio_mcux_port_isr, DEVICE_GET(gpio_mcux_porta), 0);
irq_enable(IRQ_GPIO_PORTA);
return 0;
}
#endif /* CONFIG_GPIO_MCUX_PORTA */
#ifdef CONFIG_GPIO_MCUX_PORTB
static int gpio_mcux_portb_init(struct device *dev);
static const struct gpio_mcux_config gpio_mcux_portb_config = {
.gpio_base = GPIOB,
.port_base = PORTB,
};
static struct gpio_mcux_data gpio_mcux_portb_data;
DEVICE_AND_API_INIT(gpio_mcux_portb, CONFIG_GPIO_MCUX_PORTB_NAME,
gpio_mcux_portb_init,
&gpio_mcux_portb_data, &gpio_mcux_portb_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_mcux_driver_api);
static int gpio_mcux_portb_init(struct device *dev)
{
IRQ_CONNECT(IRQ_GPIO_PORTB, CONFIG_GPIO_MCUX_PORTB_PRI,
gpio_mcux_port_isr, DEVICE_GET(gpio_mcux_portb), 0);
irq_enable(IRQ_GPIO_PORTB);
return 0;
}
#endif /* CONFIG_GPIO_MCUX_PORTB */
#ifdef CONFIG_GPIO_MCUX_PORTC
static int gpio_mcux_portc_init(struct device *dev);
static const struct gpio_mcux_config gpio_mcux_portc_config = {
.gpio_base = GPIOC,
.port_base = PORTC,
};
static struct gpio_mcux_data gpio_mcux_portc_data;
DEVICE_AND_API_INIT(gpio_mcux_portc, CONFIG_GPIO_MCUX_PORTC_NAME,
gpio_mcux_portc_init,
&gpio_mcux_portc_data, &gpio_mcux_portc_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_mcux_driver_api);
static int gpio_mcux_portc_init(struct device *dev)
{
IRQ_CONNECT(IRQ_GPIO_PORTC, CONFIG_GPIO_MCUX_PORTC_PRI,
gpio_mcux_port_isr, DEVICE_GET(gpio_mcux_portc), 0);
irq_enable(IRQ_GPIO_PORTC);
return 0;
}
#endif /* CONFIG_GPIO_MCUX_PORTC */
#ifdef CONFIG_GPIO_MCUX_PORTD
static int gpio_mcux_portd_init(struct device *dev);
static const struct gpio_mcux_config gpio_mcux_portd_config = {
.gpio_base = GPIOD,
.port_base = PORTD,
};
static struct gpio_mcux_data gpio_mcux_portd_data;
DEVICE_AND_API_INIT(gpio_mcux_portd, CONFIG_GPIO_MCUX_PORTD_NAME,
gpio_mcux_portd_init,
&gpio_mcux_portd_data, &gpio_mcux_portd_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_mcux_driver_api);
static int gpio_mcux_portd_init(struct device *dev)
{
IRQ_CONNECT(IRQ_GPIO_PORTD, CONFIG_GPIO_MCUX_PORTD_PRI,
gpio_mcux_port_isr, DEVICE_GET(gpio_mcux_portd), 0);
irq_enable(IRQ_GPIO_PORTD);
return 0;
}
#endif /* CONFIG_GPIO_MCUX_PORTD */
#ifdef CONFIG_GPIO_MCUX_PORTE
static int gpio_mcux_porte_init(struct device *dev);
static const struct gpio_mcux_config gpio_mcux_porte_config = {
.gpio_base = GPIOE,
.port_base = PORTE,
};
static struct gpio_mcux_data gpio_mcux_porte_data;
DEVICE_AND_API_INIT(gpio_mcux_porte, CONFIG_GPIO_MCUX_PORTE_NAME,
gpio_mcux_porte_init,
&gpio_mcux_porte_data, &gpio_mcux_porte_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_mcux_driver_api);
static int gpio_mcux_porte_init(struct device *dev)
{
IRQ_CONNECT(IRQ_GPIO_PORTE, CONFIG_GPIO_MCUX_PORTE_PRI,
gpio_mcux_port_isr, DEVICE_GET(gpio_mcux_porte), 0);
irq_enable(IRQ_GPIO_PORTE);
return 0;
}
#endif /* CONFIG_GPIO_MCUX_PORTE */

8
drivers/i2c/Kconfig
View file

@ -65,12 +65,12 @@ config I2C_ATMEL_SAM3
Says y to enable additional options to enable support
for individual controllers.
config I2C_KSDK
bool "KSDK I2C driver"
depends on I2C && HAS_KSDK
config I2C_MCUX
bool "MCUX I2C driver"
depends on I2C && HAS_MCUX
default n
help
Enable the ksdk I2C driver.
Enable the mcux I2C driver.
config I2C_STM32LX
bool "STM32Lx MCU I2C Driver"

2
drivers/i2c/Makefile
View file

@ -2,5 +2,5 @@ obj-$(CONFIG_I2C_DW) += i2c_dw.o
obj-$(CONFIG_I2C_QMSI) += i2c_qmsi.o
obj-$(CONFIG_I2C_QMSI_SS) += i2c_qmsi_ss.o
obj-$(CONFIG_I2C_ATMEL_SAM3) += i2c_atmel_sam3.o
obj-$(CONFIG_I2C_KSDK) += i2c_ksdk.o
obj-$(CONFIG_I2C_MCUX) += i2c_mcux.o
obj-$(CONFIG_I2C_STM32LX) += i2c_stm32lx.o

80
drivers/i2c/i2c_ksdk.c → drivers/i2c/i2c_mcux.c
View file

@ -22,29 +22,29 @@
#include <misc/util.h>
#define DEV_CFG(dev) \
((const struct i2c_ksdk_config * const)(dev)->config->config_info)
((const struct i2c_mcux_config * const)(dev)->config->config_info)
#define DEV_DATA(dev) \
((struct i2c_ksdk_data * const)(dev)->driver_data)
((struct i2c_mcux_data * const)(dev)->driver_data)
#define DEV_BASE(dev) \
((I2C_Type *)(DEV_CFG(dev))->base)
struct i2c_ksdk_config {
struct i2c_mcux_config {
I2C_Type *base;
clock_name_t clock_source;
void (*irq_config_func)(struct device *dev);
union dev_config default_cfg;
};
struct i2c_ksdk_data {
struct i2c_mcux_data {
i2c_master_handle_t handle;
struct k_sem device_sync_sem;
status_t callback_status;
};
static int i2c_ksdk_configure(struct device *dev, uint32_t dev_config_raw)
static int i2c_mcux_configure(struct device *dev, uint32_t dev_config_raw)
{
I2C_Type *base = DEV_BASE(dev);
const struct i2c_ksdk_config *config = DEV_CFG(dev);
const struct i2c_mcux_config *config = DEV_CFG(dev);
union dev_config dev_config = (union dev_config)dev_config_raw;
uint32_t clock_freq;
uint32_t baudrate;
@ -78,11 +78,11 @@ static int i2c_ksdk_configure(struct device *dev, uint32_t dev_config_raw)
return 0;
}
static void i2c_ksdk_master_transfer_callback(I2C_Type *base,
static void i2c_mcux_master_transfer_callback(I2C_Type *base,
i2c_master_handle_t *handle, status_t status, void *userData)
{
struct device *dev = userData;
struct i2c_ksdk_data *data = DEV_DATA(dev);
struct i2c_mcux_data *data = DEV_DATA(dev);
ARG_UNUSED(handle);
ARG_UNUSED(base);
@ -91,7 +91,7 @@ static void i2c_ksdk_master_transfer_callback(I2C_Type *base,
k_sem_give(&data->device_sync_sem);
}
static uint32_t i2c_ksdk_convert_flags(int msg_flags)
static uint32_t i2c_mcux_convert_flags(int msg_flags)
{
uint32_t flags = 0;
@ -106,11 +106,11 @@ static uint32_t i2c_ksdk_convert_flags(int msg_flags)
return flags;
}
static int i2c_ksdk_transfer(struct device *dev, struct i2c_msg *msgs,
static int i2c_mcux_transfer(struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_ksdk_data *data = DEV_DATA(dev);
struct i2c_mcux_data *data = DEV_DATA(dev);
i2c_master_transfer_t transfer;
status_t status;
@ -118,7 +118,7 @@ static int i2c_ksdk_transfer(struct device *dev, struct i2c_msg *msgs,
for (int i = 0; i < num_msgs; i++) {
/* Initialize the transfer descriptor */
transfer.flags = i2c_ksdk_convert_flags(msgs->flags);
transfer.flags = i2c_mcux_convert_flags(msgs->flags);
transfer.slaveAddress = addr;
transfer.direction = (msgs->flags & I2C_MSG_READ)
? kI2C_Read : kI2C_Write;
@ -155,20 +155,20 @@ static int i2c_ksdk_transfer(struct device *dev, struct i2c_msg *msgs,
return 0;
}
static void i2c_ksdk_isr(void *arg)
static void i2c_mcux_isr(void *arg)
{
struct device *dev = (struct device *)arg;
I2C_Type *base = DEV_BASE(dev);
struct i2c_ksdk_data *data = DEV_DATA(dev);
struct i2c_mcux_data *data = DEV_DATA(dev);
I2C_MasterTransferHandleIRQ(base, &data->handle);
}
static int i2c_ksdk_init(struct device *dev)
static int i2c_mcux_init(struct device *dev)
{
I2C_Type *base = DEV_BASE(dev);
const struct i2c_ksdk_config *config = DEV_CFG(dev);
struct i2c_ksdk_data *data = DEV_DATA(dev);
const struct i2c_mcux_config *config = DEV_CFG(dev);
struct i2c_mcux_data *data = DEV_DATA(dev);
uint32_t clock_freq;
i2c_master_config_t master_config;
int error;
@ -179,9 +179,9 @@ static int i2c_ksdk_init(struct device *dev)
I2C_MasterGetDefaultConfig(&master_config);
I2C_MasterInit(base, &master_config, clock_freq);
I2C_MasterTransferCreateHandle(base, &data->handle,
i2c_ksdk_master_transfer_callback, dev);
i2c_mcux_master_transfer_callback, dev);
error = i2c_ksdk_configure(dev, config->default_cfg.raw);
error = i2c_mcux_configure(dev, config->default_cfg.raw);
if (error) {
return error;
}
@ -191,60 +191,60 @@ static int i2c_ksdk_init(struct device *dev)
return 0;
}
static const struct i2c_driver_api i2c_ksdk_driver_api = {
.configure = i2c_ksdk_configure,
.transfer = i2c_ksdk_transfer,
static const struct i2c_driver_api i2c_mcux_driver_api = {
.configure = i2c_mcux_configure,
.transfer = i2c_mcux_transfer,
};
#ifdef CONFIG_I2C_0
static void i2c_ksdk_config_func_0(struct device *dev);
static void i2c_mcux_config_func_0(struct device *dev);
static const struct i2c_ksdk_config i2c_ksdk_config_0 = {
static const struct i2c_mcux_config i2c_mcux_config_0 = {
.base = I2C0,
.clock_source = I2C0_CLK_SRC,
.irq_config_func = i2c_ksdk_config_func_0,
.irq_config_func = i2c_mcux_config_func_0,
.default_cfg.raw = CONFIG_I2C_0_DEFAULT_CFG,
};
static struct i2c_ksdk_data i2c_ksdk_data_0;
static struct i2c_mcux_data i2c_mcux_data_0;
DEVICE_AND_API_INIT(i2c_ksdk_0, CONFIG_I2C_0_NAME, &i2c_ksdk_init,
&i2c_ksdk_data_0, &i2c_ksdk_config_0,
DEVICE_AND_API_INIT(i2c_mcux_0, CONFIG_I2C_0_NAME, &i2c_mcux_init,
&i2c_mcux_data_0, &i2c_mcux_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&i2c_ksdk_driver_api);
&i2c_mcux_driver_api);
static void i2c_ksdk_config_func_0(struct device *dev)
static void i2c_mcux_config_func_0(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(IRQ_I2C0, CONFIG_I2C_0_IRQ_PRI,
i2c_ksdk_isr, DEVICE_GET(i2c_ksdk_0), 0);
i2c_mcux_isr, DEVICE_GET(i2c_mcux_0), 0);
irq_enable(I2C0_IRQn);
}
#endif /* CONFIG_I2C_0 */
#ifdef CONFIG_I2C_1
static void i2c_ksdk_config_func_1(struct device *dev);
static void i2c_mcux_config_func_1(struct device *dev);
static const struct i2c_ksdk_config i2c_ksdk_config_1 = {
static const struct i2c_mcux_config i2c_mcux_config_1 = {
.base = I2C1,
.clock_source = I2C1_CLK_SRC,
.irq_config_func = i2c_ksdk_config_func_1,
.irq_config_func = i2c_mcux_config_func_1,
.default_cfg.raw = CONFIG_I2C_1_DEFAULT_CFG,
};
static struct i2c_ksdk_data i2c_ksdk_data_1;
static struct i2c_mcux_data i2c_mcux_data_1;
DEVICE_AND_API_INIT(i2c_ksdk_1, CONFIG_I2C_1_NAME, &i2c_ksdk_init,
&i2c_ksdk_data_1, &i2c_ksdk_config_1,
DEVICE_AND_API_INIT(i2c_mcux_1, CONFIG_I2C_1_NAME, &i2c_mcux_init,
&i2c_mcux_data_1, &i2c_mcux_config_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&i2c_ksdk_driver_api);
&i2c_mcux_driver_api);
static void i2c_ksdk_config_func_1(struct device *dev)
static void i2c_mcux_config_func_1(struct device *dev)
{
IRQ_CONNECT(IRQ_I2C1, CONFIG_I2C_1_IRQ_PRI,
i2c_ksdk_isr, DEVICE_GET(i2c_ksdk_1), 0);
i2c_mcux_isr, DEVICE_GET(i2c_mcux_1), 0);
irq_enable(I2C1_IRQn);
}

9
drivers/pinmux/Kconfig
View file

@ -49,14 +49,7 @@ config PINMUX_INIT_PRIORITY
rule for particular boards. Don't change this value unless you
know what you are doing.
config PINMUX_K64
bool "Freescale K64-based Pin multiplexer driver"
depends on SOC_MK64F12
default n
help
Enable driver for Freescale K64-based Pin multiplexer.
source "drivers/pinmux/Kconfig.ksdk"
source "drivers/pinmux/Kconfig.mcux"
source "drivers/pinmux/Kconfig.stm32"

49
drivers/pinmux/Kconfig.ksdk → drivers/pinmux/Kconfig.mcux
View file

@ -1,4 +1,4 @@
# Kconfig - Kinetis SDK pinmux
# Kconfig - MCUXpresso SDK pinmux
#
# Copyright (c) 2016, Freescale Semiconductor, Inc.
#
@ -15,43 +15,68 @@
# limitations under the License.
#
menuconfig PINMUX_KSDK
bool "KSDK pinmux driver"
depends on HAS_KSDK
menuconfig PINMUX_MCUX
bool "MCUX pinmux driver"
depends on HAS_MCUX
default n
help
Enable the KSDK pinmux driver.
Enable the MCUX pinmux driver.
if PINMUX_KSDK
if PINMUX_MCUX
config PINMUX_KSDK_PORTA
config PINMUX_MCUX_PORTA
bool "Port A"
default n
help
Enable Port A.
config PINMUX_KSDK_PORTB
config PINMUX_MCUX_PORTA_NAME
string "Pinmux Port A driver name"
depends on PINMUX_MCUX_PORTA
default "porta"
config PINMUX_MCUX_PORTB
bool "Port B"
default n
help
Enable Port B.
config PINMUX_KSDK_PORTC
config PINMUX_MCUX_PORTB_NAME
string "Pinmux Port B driver name"
depends on PINMUX_MCUX_PORTB
default "portb"
config PINMUX_MCUX_PORTC
bool "Port C"
default n
help
Enable Port C.
config PINMUX_KSDK_PORTD
config PINMUX_MCUX_PORTC_NAME
string "Pinmux Port C driver name"
depends on PINMUX_MCUX_PORTC
default "portc"
config PINMUX_MCUX_PORTD
bool "Port D"
default n
help
Enable Port D.
config PINMUX_KSDK_PORTE
config PINMUX_MCUX_PORTD_NAME
string "Pinmux Port D driver name"
depends on PINMUX_MCUX_PORTD
default "portd"
config PINMUX_MCUX_PORTE
bool "Port E"
default n
help
Enable Port E.
endif # PINMUX_KSDK
config PINMUX_MCUX_PORTE_NAME
string "Pinmux Port E driver name"
depends on PINMUX_MCUX_PORTE
default "porte"
endif # PINMUX_MCUX

7
drivers/pinmux/Makefile
View file

@ -1,12 +1,7 @@
ccflags-y +=-I$(srctree)/drivers
# Board initialization
ifdef CONFIG_PINMUX_K64
obj-y += k64/pinmux.o
obj-$(CONFIG_BOARD_FRDM_K64F) += k64/pinmux_board_frdm_k64f.o
obj-$(CONFIG_BOARD_HEXIWEAR_K64) += k64/pinmux_board_hexiwear.o
endif
obj-$(CONFIG_PINMUX_KSDK) += pinmux_ksdk.o
obj-$(CONFIG_PINMUX_MCUX) += pinmux_mcux.o
obj-$(CONFIG_PINMUX_STM32) += stm32/pinmux_stm32.o
obj-$(CONFIG_PINMUX_BEETLE) += beetle/pinmux_board_v2m_beetle.o
obj-$(CONFIG_BOARD_NUCLEO_F103RB) += stm32/pinmux_board_nucleo_f103rb.o

2
drivers/pinmux/dev/Kconfig
View file

@ -75,5 +75,3 @@ config PINMUX_DEV_ARM_V2M_BEETLE
Enables the pinmux dev driver for boards based on the
ARM Beetle SoC MCUs.
default n
source "drivers/pinmux/dev/Kconfig.ksdk"

52
drivers/pinmux/dev/Kconfig.ksdk
View file

@ -1,52 +0,0 @@
# Kconfig - Kinetis SDK pinmux dev
#
# Copyright (c) 2016, Freescale Semiconductor, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
menuconfig PINMUX_DEV_KSDK
bool "KSDK pinmux dev driver"
depends on PINMUX_DEV && PINMUX_KSDK
default n
help
Enable the KSDK pinmux dev driver.
if PINMUX_DEV_KSDK
config PINMUX_DEV_KSDK_PORTA_NAME
string "Pinmux Dev Port A driver name"
depends on PINMUX_KSDK_PORTA
default "pinmux_dev_porta"
config PINMUX_DEV_KSDK_PORTB_NAME
string "Pinmux Dev Port B driver name"
depends on PINMUX_KSDK_PORTB
default "pinmux_dev_portb"
config PINMUX_DEV_KSDK_PORTC_NAME
string "Pinmux Dev Port C driver name"
depends on PINMUX_KSDK_PORTC
default "pinmux_dev_portc"
config PINMUX_DEV_KSDK_PORTD_NAME
string "Pinmux Dev Port D driver name"
depends on PINMUX_KSDK_PORTD
default "pinmux_dev_portd"
config PINMUX_DEV_KSDK_PORTE_NAME
string "Pinmux Dev Port E driver name"
depends on PINMUX_KSDK_PORTE
default "pinmux_dev_porte"
endif # PINMUX_DEV_KSDK

1
drivers/pinmux/dev/Makefile
View file

@ -4,7 +4,6 @@ ccflags-$(CONFIG_PINMUX_DEV_QMSI) += -I$(CONFIG_QMSI_INSTALL_PATH)/include
obj-$(CONFIG_PINMUX_DEV_ATMEL_SAM3X) += pinmux_dev_atmel_sam3x.o
obj-$(CONFIG_PINMUX_DEV_K64) += pinmux_dev_k64.o
obj-$(CONFIG_PINMUX_DEV_KSDK) += pinmux_dev_ksdk.o
obj-$(CONFIG_PINMUX_DEV_QMSI) += pinmux_dev_qmsi.o
obj-$(CONFIG_PINMUX_DEV_STM32) += pinmux_dev_stm32.o
obj-$(CONFIG_PINMUX_DEV_ARM_V2M_BEETLE) += pinmux_dev_arm_beetle.o

122
drivers/pinmux/dev/pinmux_dev_ksdk.c
View file

@ -1,122 +0,0 @@
/*
* Copyright (c) 2016 Freescale Semiconductor, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <errno.h>
#include <device.h>
#include <pinmux.h>
#include <pinmux/pinmux_ksdk.h>
struct pinmux_dev_ksdk_config {
PORT_Type *base;
};
static int pinmux_dev_ksdk_set(struct device *dev, uint32_t pin, uint32_t func)
{
const struct pinmux_dev_ksdk_config *config = dev->config->config_info;
return pinmux_ksdk_set(config->base, pin, func);
}
static int pinmux_dev_ksdk_get(struct device *dev, uint32_t pin, uint32_t *func)
{
const struct pinmux_dev_ksdk_config *config = dev->config->config_info;
return pinmux_ksdk_get(config->base, pin, func);
}
static int pinmux_dev_ksdk_pullup(struct device *dev, uint32_t pin,
uint8_t func)
{
return -ENOTSUP;
}
static int pinmux_dev_ksdk_input(struct device *dev, uint32_t pin,
uint8_t func)
{
return -ENOTSUP;
}
static const struct pinmux_driver_api pinmux_dev_ksdk_driver_api = {
.set = pinmux_dev_ksdk_set,
.get = pinmux_dev_ksdk_get,
.pullup = pinmux_dev_ksdk_pullup,
.input = pinmux_dev_ksdk_input,
};
static int pinmux_dev_ksdk_init(struct device *dev)
{
return 0;
}
#ifdef CONFIG_PINMUX_KSDK_PORTA
static const struct pinmux_dev_ksdk_config pinmux_dev_ksdk_porta_config = {
.base = PORTA,
};
DEVICE_AND_API_INIT(pinmux_dev_porta, CONFIG_PINMUX_DEV_KSDK_PORTA_NAME,
&pinmux_dev_ksdk_init,
NULL, &pinmux_dev_ksdk_porta_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_dev_ksdk_driver_api);
#endif
#ifdef CONFIG_PINMUX_KSDK_PORTB
static const struct pinmux_dev_ksdk_config pinmux_dev_ksdk_portb_config = {
.base = PORTB,
};
DEVICE_AND_API_INIT(pinmux_dev_portb, CONFIG_PINMUX_DEV_KSDK_PORTB_NAME,
&pinmux_dev_ksdk_init,
NULL, &pinmux_dev_ksdk_portb_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_dev_ksdk_driver_api);
#endif
#ifdef CONFIG_PINMUX_KSDK_PORTC
static const struct pinmux_dev_ksdk_config pinmux_dev_ksdk_portc_config = {
.base = PORTC,
};
DEVICE_AND_API_INIT(pinmux_dev_portc, CONFIG_PINMUX_DEV_KSDK_PORTC_NAME,
&pinmux_dev_ksdk_init,
NULL, &pinmux_dev_ksdk_portc_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_dev_ksdk_driver_api);
#endif
#ifdef CONFIG_PINMUX_KSDK_PORTD
static const struct pinmux_dev_ksdk_config pinmux_dev_ksdk_portd_config = {
.base = PORTD,
};
DEVICE_AND_API_INIT(pinmux_dev_portd, CONFIG_PINMUX_DEV_KSDK_PORTD_NAME,
&pinmux_dev_ksdk_init,
NULL, &pinmux_dev_ksdk_portd_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_dev_ksdk_driver_api);
#endif
#ifdef CONFIG_PINMUX_KSDK_PORTE
static const struct pinmux_dev_ksdk_config pinmux_dev_ksdk_porte_config = {
.base = PORTE,
};
DEVICE_AND_API_INIT(pinmux_dev_porte, CONFIG_PINMUX_DEV_KSDK_PORTE_NAME,
&pinmux_dev_ksdk_init,
NULL, &pinmux_dev_ksdk_porte_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_dev_ksdk_driver_api);
#endif

163
drivers/pinmux/k64/pinmux.c
View file

@ -1,163 +0,0 @@
/* pinmux.c - pin out mapping for the Freescale K64 SoC */
/*
* Copyright (c) 2016, Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <errno.h>
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <sys_io.h>
#include <pinmux.h>
#include <pinmux/pinmux.h>
#include <pinmux/k64/pinmux.h>
/* port pin number conversion from pin ID */
#define PIN_FROM_ID(pin_id) (pin_id % K64_PINMUX_NUM_PINS)
#ifdef CONFIG_GPIO_K64_A
static inline int config_port_a(mem_addr_t *addr)
{
*addr = PORT_K64_A_BASE_ADDR;
return 0;
}
#else
#define config_port_a(addr) -EACCES
#endif
#ifdef CONFIG_GPIO_K64_B
static inline int config_port_b(mem_addr_t *addr)
{
*addr = PORT_K64_B_BASE_ADDR;
return 0;
}
#else
#define config_port_b(addr) -EACCES
#endif
#ifdef CONFIG_GPIO_K64_C
static inline int config_port_c(mem_addr_t *addr)
{
*addr = PORT_K64_C_BASE_ADDR;
return 0;
}
#else
#define config_port_c(addr) -EACCES
#endif
#ifdef CONFIG_GPIO_K64_D
static inline int config_port_d(mem_addr_t *addr)
{
*addr = PORT_K64_D_BASE_ADDR;
return 0;
}
#else
#define config_port_d(addr) -EACCES
#endif
#ifdef CONFIG_GPIO_K64_E
static inline int config_port_e(mem_addr_t *addr)
{
*addr = PORT_K64_E_BASE_ADDR;
return 0;
}
#else
#define config_port_e(addr) -EACCES
#endif
static int _fsl_k64_get_port_addr(uint8_t pin_id, mem_addr_t *port_addr_ptr)
{
/* determine the port base address associated with the
* pin identifier
*/
if (pin_id < K64_PIN_PTB0) { /* Port A pin */
return config_port_a(port_addr_ptr);
} else if (pin_id < K64_PIN_PTC0) { /* Port B pin */
return config_port_b(port_addr_ptr);
} else if (pin_id < K64_PIN_PTD0) { /* Port C pin */
return config_port_c(port_addr_ptr);
} else if (pin_id < K64_PIN_PTE0) { /* Port D pin */
return config_port_d(port_addr_ptr);
} else { /* Port E pin */
return config_port_e(port_addr_ptr);
}
}
int _fsl_k64_set_pin(uint32_t pin_id, uint32_t func)
{
mem_addr_t port_base_addr;
uint8_t port_pin;
uint32_t status;
if (pin_id >= PINMUX_NUM_PINS) {
return -ENOTSUP;
}
/* determine the pin's port register base address */
status = _fsl_k64_get_port_addr(pin_id, &port_base_addr);
if (status != 0) {
return status;
}
/* extract the pin number within its port */
port_pin = PIN_FROM_ID(pin_id);
/* set pin function and control settings */
sys_write32(func, port_base_addr + K64_PINMUX_CTRL_OFFSET(port_pin));
return 0;
}
int _fsl_k64_get_pin(uint32_t pin_id, uint32_t *func)
{
mem_addr_t port_base_addr;
uint8_t port_pin;
uint32_t status;
if (pin_id >= PINMUX_NUM_PINS) {
return -ENOTSUP;
}
/* determine the pin's port register base address */
status = _fsl_k64_get_port_addr(pin_id, &port_base_addr);
if (status != 0) {
return status;
}
/* extract the pin number within its port */
port_pin = PIN_FROM_ID(pin_id);
/* get pin function and control settings */
*func = sys_read32(port_base_addr + K64_PINMUX_CTRL_OFFSET(port_pin));
return 0;
}

290
drivers/pinmux/k64/pinmux.h
View file

@ -1,290 +0,0 @@
/* pinmux.h - Freescale K64 pinmux header */
/*
* Copyright (c) 2016, Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file Header file for Freescale K64 pin multiplexing.
*/
#ifndef __INCLUDE_PINMUX_K64_H
#define __INCLUDE_PINMUX_K64_H
#define K64_PINMUX_NUM_PINS 32 /* # of I/O pins per port */
/* Port Control Register offsets */
#define K64_PINMUX_CTRL_OFFSET(pin) (pin * 4)
/*
* The following pin settings match the K64 PORT module's
* Pin Control Register bit fields.
*/
/*
* Pin interrupt configuration:
* At reset, interrupts are disabled for all pins.
*/
#define K64_PINMUX_INT_MASK (0xF << 16) /* interrupt config. */
#define K64_PINMUX_INT_DISABLE (0x0 << 16) /* disable interrupt */
#define K64_PINMUX_INT_LOW (0x8 << 16) /* active-low interrupt */
#define K64_PINMUX_INT_RISING (0x9 << 16) /* rising-edge interrupt */
#define K64_PINMUX_INT_FALLING (0xA << 16) /* falling-edge interrupt */
#define K64_PINMUX_INT_BOTH_EDGE (0xB << 16) /* either edge interrupt */
#define K64_PINMUX_INT_HIGH (0xC << 16) /* active-high interrupt */
/*
* Pin function identification:
* At reset, the setting for PTA0/1/2/3/4 is function 7;
* the remaining pins are set to function 0.
*/
#define K64_PINMUX_ALT_MASK (0x7 << 8)
#define K64_PINMUX_ALT_0 (0x0 << 8)
#define K64_PINMUX_ALT_1 (0x1 << 8)
#define K64_PINMUX_ALT_2 (0x2 << 8)
#define K64_PINMUX_ALT_3 (0x3 << 8)
#define K64_PINMUX_ALT_4 (0x4 << 8)
#define K64_PINMUX_ALT_5 (0x5 << 8)
#define K64_PINMUX_ALT_6 (0x6 << 8)
#define K64_PINMUX_ALT_7 K64_PINMUX_ALT_MASK
#define K64_PINMUX_FUNC_GPIO K64_PINMUX_ALT_1
#define K64_PINMUX_FUNC_DISABLED K64_PINMUX_ALT_0
#define K64_PINMUX_FUNC_ANALOG K64_PINMUX_ALT_0
#define K64_PINMUX_FUNC_ETHERNET K64_PINMUX_ALT_4
#define K64_PINMUX_FUNC_SPI K64_PINMUX_ALT_2
/*
* Pin drive strength configuration, for output:
* At reset, the setting for PTA0/1/2/3/4/5 is high drive strength;
* the remaining pins are set to low drive strength.
*/
#define K64_PINMUX_DRV_STRN_MASK (0x1 << 6) /* drive strength select */
#define K64_PINMUX_DRV_STRN_LOW (0x0 << 6) /* low drive strength */
#define K64_PINMUX_DRV_STRN_HIGH (0x1 << 6) /* high drive strength */
/*
* Pin open drain configuration, for output:
* At reset, open drain is disabled for all pins.
*/
#define K64_PINMUX_OPEN_DRN_MASK (0x1 << 5) /* open drain enable */
#define K64_PINMUX_OPEN_DRN_DISABLE (0x0 << 5) /* disable open drain */
#define K64_PINMUX_OPEN_DRN_ENABLE (0x1 << 5) /* enable open drain */
/*
* Pin slew rate configuration, for output:
* At reset, fast slew rate is set for all pins.
*/
#define K64_PINMUX_SLEW_RATE_MASK (0x1 << 2) /* slew rate select */
#define K64_PINMUX_SLEW_RATE_FAST (0x0 << 2) /* fast slew rate */
#define K64_PINMUX_SLEW_RATE_SLOW (0x1 << 2) /* slow slew rate */
/*
* Pin pull-up/pull-down configuration, for input:
* At reset, the setting for PTA1/2/3/4/5 is pull-up; PTA0 is pull-down;
* pull-up/pull-down is disabled for the remaining pins.
*/
#define K64_PINMUX_PULL_EN_MASK (0x1 << 1) /* pullup/pulldown enable */
#define K64_PINMUX_PULL_DISABLE (0x0 << 1) /* disable pullup/pulldown */
#define K64_PINMUX_PULL_ENABLE (0x1 << 1) /* enable pullup/pulldown */
#define K64_PINMUX_PULL_SEL_MASK (0x1 << 0) /* pullup/pulldown select */
#define K64_PINMUX_PULL_DN (0x0 << 0) /* select pulldown */
#define K64_PINMUX_PULL_UP (0x1 << 0) /* select pullup */
/*
* Pin identification, by port and pin
*/
#define K64_PIN_PTA0 0
#define K64_PIN_PTA1 1
#define K64_PIN_PTA2 2
#define K64_PIN_PTA3 3
#define K64_PIN_PTA4 4
#define K64_PIN_PTA5 5
#define K64_PIN_PTA6 6
#define K64_PIN_PTA7 7
#define K64_PIN_PTA8 8
#define K64_PIN_PTA9 9
#define K64_PIN_PTA10 10
#define K64_PIN_PTA11 11
#define K64_PIN_PTA12 12
#define K64_PIN_PTA13 13
#define K64_PIN_PTA14 14
#define K64_PIN_PTA15 15
#define K64_PIN_PTA16 16
#define K64_PIN_PTA17 17
#define K64_PIN_PTA18 18
#define K64_PIN_PTA19 19
#define K64_PIN_PTA20 20
#define K64_PIN_PTA21 21
#define K64_PIN_PTA22 22
#define K64_PIN_PTA23 23
#define K64_PIN_PTA24 24
#define K64_PIN_PTA25 25
#define K64_PIN_PTA26 26
#define K64_PIN_PTA27 27
#define K64_PIN_PTA28 28
#define K64_PIN_PTA29 29
#define K64_PIN_PTA30 30
#define K64_PIN_PTA31 31
#define K64_PIN_PTB0 32
#define K64_PIN_PTB1 33
#define K64_PIN_PTB2 34
#define K64_PIN_PTB3 35
#define K64_PIN_PTB4 36
#define K64_PIN_PTB5 37
#define K64_PIN_PTB6 38
#define K64_PIN_PTB7 39
#define K64_PIN_PTB8 40
#define K64_PIN_PTB9 41
#define K64_PIN_PTB10 42
#define K64_PIN_PTB11 43
#define K64_PIN_PTB12 44
#define K64_PIN_PTB13 45
#define K64_PIN_PTB14 46
#define K64_PIN_PTB15 47
#define K64_PIN_PTB16 48
#define K64_PIN_PTB17 49
#define K64_PIN_PTB18 50
#define K64_PIN_PTB19 51
#define K64_PIN_PTB20 52
#define K64_PIN_PTB21 53
#define K64_PIN_PTB22 54
#define K64_PIN_PTB23 55
#define K64_PIN_PTB24 56
#define K64_PIN_PTB25 57
#define K64_PIN_PTB26 58
#define K64_PIN_PTB27 59
#define K64_PIN_PTB28 60
#define K64_PIN_PTB29 61
#define K64_PIN_PTB30 62
#define K64_PIN_PTB31 63
#define K64_PIN_PTC0 64
#define K64_PIN_PTC1 65
#define K64_PIN_PTC2 66
#define K64_PIN_PTC3 67
#define K64_PIN_PTC4 68
#define K64_PIN_PTC5 69
#define K64_PIN_PTC6 70
#define K64_PIN_PTC7 71
#define K64_PIN_PTC8 72
#define K64_PIN_PTC9 73
#define K64_PIN_PTC10 74
#define K64_PIN_PTC11 75
#define K64_PIN_PTC12 76
#define K64_PIN_PTC13 77
#define K64_PIN_PTC14 78
#define K64_PIN_PTC15 79
#define K64_PIN_PTC16 80
#define K64_PIN_PTC17 81
#define K64_PIN_PTC18 82
#define K64_PIN_PTC19 83
#define K64_PIN_PTC20 84
#define K64_PIN_PTC21 85
#define K64_PIN_PTC22 86
#define K64_PIN_PTC23 87
#define K64_PIN_PTC24 88
#define K64_PIN_PTC25 89
#define K64_PIN_PTC26 90
#define K64_PIN_PTC27 91
#define K64_PIN_PTC28 92
#define K64_PIN_PTC29 93
#define K64_PIN_PTC30 94
#define K64_PIN_PTC31 95
#define K64_PIN_PTD0 96
#define K64_PIN_PTD1 97
#define K64_PIN_PTD2 98
#define K64_PIN_PTD3 99
#define K64_PIN_PTD4 100
#define K64_PIN_PTD5 101
#define K64_PIN_PTD6 102
#define K64_PIN_PTD7 103
#define K64_PIN_PTD8 104
#define K64_PIN_PTD9 105
#define K64_PIN_PTD10 106
#define K64_PIN_PTD11 107
#define K64_PIN_PTD12 108
#define K64_PIN_PTD13 109
#define K64_PIN_PTD14 110
#define K64_PIN_PTD15 111
#define K64_PIN_PTD16 112
#define K64_PIN_PTD17 113
#define K64_PIN_PTD18 114
#define K64_PIN_PTD19 115
#define K64_PIN_PTD20 116
#define K64_PIN_PTD21 117
#define K64_PIN_PTD22 118
#define K64_PIN_PTD23 119
#define K64_PIN_PTD24 120
#define K64_PIN_PTD25 121
#define K64_PIN_PTD26 122
#define K64_PIN_PTD27 123
#define K64_PIN_PTD28 124
#define K64_PIN_PTD29 125
#define K64_PIN_PTD30 126
#define K64_PIN_PTD31 127
#define K64_PIN_PTE0 128
#define K64_PIN_PTE1 129
#define K64_PIN_PTE2 130
#define K64_PIN_PTE3 131
#define K64_PIN_PTE4 132
#define K64_PIN_PTE5 133
#define K64_PIN_PTE6 134
#define K64_PIN_PTE7 135
#define K64_PIN_PTE8 136
#define K64_PIN_PTE9 137
#define K64_PIN_PTE10 138
#define K64_PIN_PTE11 139
#define K64_PIN_PTE12 140
#define K64_PIN_PTE13 141
#define K64_PIN_PTE14 142
#define K64_PIN_PTE15 143
#define K64_PIN_PTE16 144
#define K64_PIN_PTE17 145
#define K64_PIN_PTE18 146
#define K64_PIN_PTE19 147
#define K64_PIN_PTE20 148
#define K64_PIN_PTE21 149
#define K64_PIN_PTE22 150
#define K64_PIN_PTE23 151
#define K64_PIN_PTE24 152
#define K64_PIN_PTE25 153
#define K64_PIN_PTE26 154
#define K64_PIN_PTE27 155
#define K64_PIN_PTE28 156
#define K64_PIN_PTE29 157
#define K64_PIN_PTE30 158
#define K64_PIN_PTE31 159
int __deprecated _fsl_k64_set_pin(uint32_t pin_id, uint32_t func);
int __deprecated _fsl_k64_get_pin(uint32_t pin_id, uint32_t *func);
#endif /* __INCLUDE_PINMUX_K64_H */

126
drivers/pinmux/k64/pinmux_board_frdm_k64f.c
View file

@ -1,126 +0,0 @@
/* pinmux_board_frdm_k64f.c - pin out mapping for the Freescale FRDM-K64F board */
/*
* Copyright (c) 2016 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <sys_io.h>
#include <pinmux.h>
#include <pinmux/pinmux.h>
#include <pinmux/k64/pinmux.h>
/*
* I/O pin configuration
*/
/*
* Alter this table to change the default Arduino pin settings on the Freescale
* FRDM-K64F boards. Specifically, change the PINMUX_* values to represent
* the functionality desired.
*
* The FRDM-K64F board routes the PTA0/1/2 pins for JTAG/SWD signals that
* are used for the OpenSDAv2 debug interface. These pins are also routed to
* the Arduino header pins as D8, D3 and D5, respectively.
* Since the K64 MCU configures these pins for JTAG/SWD signaling at reset,
* they should only be re-configured if the debug interface is not used.
*
*/
static const struct pin_config mux_config[] = {
/* pin, selected mode */
{ K64_PIN_PTC16, K64_PINMUX_ALT_3 }, /* UART3 RX */
{ K64_PIN_PTC17, K64_PINMUX_ALT_3 }, /* UART3 TX */
{ K64_PIN_PTB9, K64_PINMUX_FUNC_GPIO },
#ifndef CONFIG_PRESERVE_JTAG_IO_PINS
{ K64_PIN_PTA1, K64_PINMUX_FUNC_GPIO },
#endif
{ K64_PIN_PTB23, K64_PINMUX_FUNC_GPIO },
#ifndef CONFIG_PRESERVE_JTAG_IO_PINS
{ K64_PIN_PTA2, K64_PINMUX_FUNC_GPIO },
#endif
{ K64_PIN_PTC2, K64_PINMUX_FUNC_GPIO },
{ K64_PIN_PTC3, K64_PINMUX_FUNC_GPIO },
#ifndef CONFIG_PRESERVE_JTAG_IO_PINS
{ K64_PIN_PTA0, K64_PINMUX_FUNC_GPIO },
#endif
{ K64_PIN_PTC4, K64_PINMUX_FUNC_GPIO },
{ K64_PIN_PTC6, K64_PINMUX_FUNC_GPIO }, /* SW2 / FXOS8700 INT1 */
{ K64_PIN_PTA4, K64_PINMUX_FUNC_GPIO }, /* SW3 */
{ K64_PIN_PTB22, K64_PINMUX_FUNC_GPIO }, /* Red LED */
{ K64_PIN_PTE26, K64_PINMUX_FUNC_GPIO }, /* Green LED */
{ K64_PIN_PTB21, K64_PINMUX_FUNC_GPIO }, /* Blue LED */
/* SPI 0 */
#ifdef CONFIG_SPI_0
{ K64_PIN_PTD0, K64_PINMUX_FUNC_SPI },
{ K64_PIN_PTD2, K64_PINMUX_FUNC_SPI },
{ K64_PIN_PTD3, K64_PINMUX_FUNC_SPI },
{ K64_PIN_PTD1, K64_PINMUX_FUNC_SPI },
#else
{ K64_PIN_PTD0, K64_PINMUX_FUNC_GPIO },
{ K64_PIN_PTD2, K64_PINMUX_FUNC_GPIO },
{ K64_PIN_PTD3, K64_PINMUX_FUNC_GPIO },
{ K64_PIN_PTD1, K64_PINMUX_FUNC_GPIO },
#endif
/* I2C0_SDA */
{ K64_PIN_PTE25, (K64_PINMUX_ALT_5 | K64_PINMUX_OPEN_DRN_ENABLE) },
/* I2C0_SCL */
{ K64_PIN_PTE24, (K64_PINMUX_ALT_5 | K64_PINMUX_OPEN_DRN_ENABLE) },
{ K64_PIN_PTB2, K64_PINMUX_FUNC_ANALOG }, /* ADC0_SE12/Analog In 0 */
{ K64_PIN_PTB3, K64_PINMUX_FUNC_ANALOG }, /* ADC0_SE13/Analog In 1 */
{ K64_PIN_PTB10, K64_PINMUX_FUNC_ANALOG }, /* ADC1_SE14/Analog In 2 */
{ K64_PIN_PTB11, K64_PINMUX_FUNC_ANALOG }, /* ADC1_SE15/Analog In 3 */
{ K64_PIN_PTC11, K64_PINMUX_FUNC_ANALOG }, /* ADC1_SE7b/Analog In 4 */
{ K64_PIN_PTC10, K64_PINMUX_FUNC_ANALOG }, /* ADC1_SE6b/Analog In 5 */
#if CONFIG_ETH_KSDK_0
{ K64_PIN_PTA5, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTA12, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTA13, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTA14, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTA15, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTA16, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTA17, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTA28, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTB0, (K64_PINMUX_FUNC_ETHERNET |
K64_PINMUX_OPEN_DRN_ENABLE |
K64_PINMUX_PULL_ENABLE |
K64_PINMUX_PULL_UP)},
{ K64_PIN_PTB1, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTC16, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTC17, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTC18, K64_PINMUX_FUNC_ETHERNET},
{ K64_PIN_PTC19, K64_PINMUX_FUNC_ETHERNET},
#endif
};
static int fsl_frdm_k64f_pin_init(struct device *arg)
{
ARG_UNUSED(arg);
/* configure the pins from the default mapping above */
for (int i = 0; i < ARRAY_SIZE(mux_config); i++) {
_fsl_k64_set_pin(mux_config[i].pin_num, mux_config[i].mode);
}
return 0;
}
SYS_INIT(fsl_frdm_k64f_pin_init, POST_KERNEL, CONFIG_PINMUX_INIT_PRIORITY);

69
drivers/pinmux/k64/pinmux_board_hexiwear.c
View file

@ -1,69 +0,0 @@
/* pinmux_board_hexiwear.c - pin out mapping for the NXP Hexiwear board */
/*
* Copyright (c) 2016 Intel Corporation
* Copyright (c) 2016, Freescale Semiconductor, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <sys_io.h>
#include <pinmux.h>
#include <pinmux/pinmux.h>
#include <pinmux/k64/pinmux.h>
/*
* I/O pin configuration
*/
/*
* Alter this table to change the default pin settings on the NXP Hexiwear
* boards. Specifically, change the PINMUX_* values to represent the
* functionality desired.
*/
static const struct pin_config mux_config[] = {
/* pin, selected mode */
/* RGB */
{ K64_PIN_PTC8, K64_PINMUX_FUNC_GPIO},
{ K64_PIN_PTC9, K64_PINMUX_FUNC_GPIO},
{ K64_PIN_PTD0, K64_PINMUX_FUNC_GPIO},
/* I2C1 - accel/mag, gyro, pressure */
{ K64_PIN_PTC10, (K64_PINMUX_ALT_2 | K64_PINMUX_OPEN_DRN_ENABLE)},
{ K64_PIN_PTC11, (K64_PINMUX_ALT_2 | K64_PINMUX_OPEN_DRN_ENABLE)},
/* FXOS8700 INT1 */
{ K64_PIN_PTC1, K64_PINMUX_FUNC_GPIO},
/* UART4 - BLE */
{ K64_PIN_PTE25, K64_PINMUX_ALT_3 },
{ K64_PIN_PTE24, K64_PINMUX_ALT_3 },
};
static int hexiwear_pin_init(struct device *arg)
{
ARG_UNUSED(arg);
/* configure the pins from the default mapping above */
for (int i = 0; i < ARRAY_SIZE(mux_config); i++) {
_fsl_k64_set_pin(mux_config[i].pin_num, mux_config[i].mode);
}
return 0;
}
SYS_INIT(hexiwear_pin_init, POST_KERNEL, CONFIG_PINMUX_INIT_PRIORITY);

39
drivers/pinmux/pinmux_ksdk.c
View file

@ -1,39 +0,0 @@
/*
* Copyright (c) 2016 Freescale Semiconductor, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <pinmux/pinmux_ksdk.h>
#include <fsl_common.h>
#include <fsl_clock.h>
int pinmux_ksdk_init(void)
{
#ifdef CONFIG_PINMUX_KSDK_PORTA
CLOCK_EnableClock(kCLOCK_PortA);
#endif
#ifdef CONFIG_PINMUX_KSDK_PORTB
CLOCK_EnableClock(kCLOCK_PortB);
#endif
#ifdef CONFIG_PINMUX_KSDK_PORTC
CLOCK_EnableClock(kCLOCK_PortC);
#endif
#ifdef CONFIG_PINMUX_KSDK_PORTD
CLOCK_EnableClock(kCLOCK_PortD);
#endif
#ifdef CONFIG_PINMUX_KSDK_PORTE
CLOCK_EnableClock(kCLOCK_PortE);
#endif
return 0;
}

37
drivers/pinmux/pinmux_ksdk.h
View file

@ -1,37 +0,0 @@
/*
* Copyright (c) 2016 Freescale Semiconductor, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __INCLUDE_PINMUX_KSDK_H
#define __INCLUDE_PINMUX_KSDK_H
#include <device.h>
#include <fsl_port.h>
int pinmux_ksdk_init(void);
static inline int pinmux_ksdk_set(PORT_Type *base, uint32_t pin, uint32_t func)
{
base->PCR[pin] = func;
return 0;
}
static inline int pinmux_ksdk_get(PORT_Type *base, uint32_t pin, uint32_t *func)
{
*func = base->PCR[pin];
return 0;
}
#endif /* __INCLUDE_PINMUX_KSDK_H */

137
drivers/pinmux/pinmux_mcux.c Normal file
View file

@ -0,0 +1,137 @@
/*
* Copyright (c) 2016 Freescale Semiconductor, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <errno.h>
#include <device.h>
#include <pinmux.h>
#include <fsl_common.h>
#include <fsl_clock.h>
struct pinmux_mcux_config {
clock_ip_name_t clock_ip_name;
PORT_Type *base;
};
static int pinmux_mcux_set(struct device *dev, uint32_t pin, uint32_t func)
{
const struct pinmux_mcux_config *config = dev->config->config_info;
PORT_Type *base = config->base;
base->PCR[pin] = func;
return 0;
}
static int pinmux_mcux_get(struct device *dev, uint32_t pin, uint32_t *func)
{
const struct pinmux_mcux_config *config = dev->config->config_info;
PORT_Type *base = config->base;
*func = base->PCR[pin];
return 0;
}
static int pinmux_mcux_pullup(struct device *dev, uint32_t pin, uint8_t func)
{
return -ENOTSUP;
}
static int pinmux_mcux_input(struct device *dev, uint32_t pin, uint8_t func)
{
return -ENOTSUP;
}
static int pinmux_mcux_init(struct device *dev)
{
const struct pinmux_mcux_config *config = dev->config->config_info;
CLOCK_EnableClock(config->clock_ip_name);
return 0;
}
static const struct pinmux_driver_api pinmux_mcux_driver_api = {
.set = pinmux_mcux_set,
.get = pinmux_mcux_get,
.pullup = pinmux_mcux_pullup,
.input = pinmux_mcux_input,
};
#ifdef CONFIG_PINMUX_MCUX_PORTA
static const struct pinmux_mcux_config pinmux_mcux_porta_config = {
.base = PORTA,
.clock_ip_name = kCLOCK_PortA,
};
DEVICE_AND_API_INIT(pinmux_porta, CONFIG_PINMUX_MCUX_PORTA_NAME,
&pinmux_mcux_init,
NULL, &pinmux_mcux_porta_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_mcux_driver_api);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTB
static const struct pinmux_mcux_config pinmux_mcux_portb_config = {
.base = PORTB,
.clock_ip_name = kCLOCK_PortB,
};
DEVICE_AND_API_INIT(pinmux_portb, CONFIG_PINMUX_MCUX_PORTB_NAME,
&pinmux_mcux_init,
NULL, &pinmux_mcux_portb_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_mcux_driver_api);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTC
static const struct pinmux_mcux_config pinmux_mcux_portc_config = {
.base = PORTC,
.clock_ip_name = kCLOCK_PortC,
};
DEVICE_AND_API_INIT(pinmux_portc, CONFIG_PINMUX_MCUX_PORTC_NAME,
&pinmux_mcux_init,
NULL, &pinmux_mcux_portc_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_mcux_driver_api);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTD
static const struct pinmux_mcux_config pinmux_mcux_portd_config = {
.base = PORTD,
.clock_ip_name = kCLOCK_PortD,
};
DEVICE_AND_API_INIT(pinmux_portd, CONFIG_PINMUX_MCUX_PORTD_NAME,
&pinmux_mcux_init,
NULL, &pinmux_mcux_portd_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_mcux_driver_api);
#endif
#ifdef CONFIG_PINMUX_MCUX_PORTE
static const struct pinmux_mcux_config pinmux_mcux_porte_config = {
.base = PORTE,
.clock_ip_name = kCLOCK_PortE,
};
DEVICE_AND_API_INIT(pinmux_porte, CONFIG_PINMUX_MCUX_PORTE_NAME,
&pinmux_mcux_init,
NULL, &pinmux_mcux_porte_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&pinmux_mcux_driver_api);
#endif

2
drivers/random/Kconfig
View file

@ -25,7 +25,7 @@ menuconfig RANDOM_GENERATOR
if RANDOM_GENERATOR
source "drivers/random/Kconfig.ksdk"
source "drivers/random/Kconfig.mcux"
config RANDOM_HAS_DRIVER
bool

8
drivers/random/Kconfig.ksdk → drivers/random/Kconfig.mcux
View file

@ -1,4 +1,4 @@
# Kconfig.ksdk - ksdk random generator driver configuration
# Kconfig.mcux - mcux random generator driver configuration
#
# Copyright (c) 2016 ARM Ltd.
#
@ -14,11 +14,11 @@
# See the License for the specific language governing permissions and
# limitations under the License.
menuconfig RANDOM_KSDK
bool "KSDK Random driver"
menuconfig RANDOM_MCUX
bool "MCUX Random driver"
depends on RANDOM_GENERATOR && HAS_RNGA
default n
select RANDOM_HAS_DRIVER
help
This option enables the random number generator accelerator (RNGA)
driver based on the KSDK RNGA driver.
driver based on the MCUX RNGA driver.

2
drivers/random/Makefile
View file

@ -1,3 +1,3 @@
obj-$(CONFIG_RANDOM_KSDK) += random_ksdk.o
obj-$(CONFIG_RANDOM_MCUX) += random_mcux.o
obj-$(CONFIG_TIMER_RANDOM_GENERATOR) = rand32_timer.o
obj-$(CONFIG_X86_TSC_RANDOM_GENERATOR) += rand32_timestamp.o

22
drivers/random/random_ksdk.c → drivers/random/random_mcux.c
View file

@ -22,7 +22,7 @@
#include "fsl_rnga.h"
static uint8_t random_ksdk_get_uint8(void)
static uint8_t random_mcux_get_uint8(void)
{
uint32_t random;
uint8_t output = 0;
@ -47,7 +47,7 @@ static uint8_t random_ksdk_get_uint8(void)
return output;
}
static int random_ksdk_get_entropy(struct device *dev, uint8_t *buffer,
static int random_mcux_get_entropy(struct device *dev, uint8_t *buffer,
uint16_t length)
{
int i;
@ -55,24 +55,24 @@ static int random_ksdk_get_entropy(struct device *dev, uint8_t *buffer,
ARG_UNUSED(dev);
for (i = 0; i < length; i++) {
buffer[i] = random_ksdk_get_uint8();
buffer[i] = random_mcux_get_uint8();
}
return 0;
}
static const struct random_driver_api random_ksdk_api_funcs = {
.get_entropy = random_ksdk_get_entropy
static const struct random_driver_api random_mcux_api_funcs = {
.get_entropy = random_mcux_get_entropy
};
static int random_ksdk_init(struct device *);
static int random_mcux_init(struct device *);
DEVICE_AND_API_INIT(random_ksdk, CONFIG_RANDOM_NAME,
random_ksdk_init, NULL, NULL,
DEVICE_AND_API_INIT(random_mcux, CONFIG_RANDOM_NAME,
random_mcux_init, NULL, NULL,
PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&random_ksdk_api_funcs);
&random_mcux_api_funcs);
static int random_ksdk_init(struct device *dev)
static int random_mcux_init(struct device *dev)
{
uint32_t seed = sys_cycle_get_32();
@ -96,7 +96,7 @@ uint32_t sys_rand32_get(void)
uint32_t output;
int r;
r = random_ksdk_get_entropy(DEVICE_GET(random_ksdk),
r = random_mcux_get_entropy(DEVICE_GET(random_mcux),
(uint8_t *) &output, sizeof(output));
__ASSERT_NO_MSG(!r);

4
ext/hal/Kbuild
View file

@ -1,4 +1,4 @@
obj-$(CONFIG_HAS_KSDK) += ksdk/
obj-$(CONFIG_HAS_MCUX) += nxp/mcux/
obj-$(CONFIG_QMSI_BUILTIN) += qmsi/
obj-$(CONFIG_HAS_STM32CUBE) += st/stm32cube/
obj-$(CONFIG_CC3200SDK_BUILTIN) += ti/cc3200sdk/
obj-$(CONFIG_HAS_CC3200SDK) += ti/cc3200sdk/

4
ext/hal/Kconfig
View file

@ -22,10 +22,10 @@ menu "HALs"
source "ext/hal/cmsis/Kconfig"
source "ext/hal/ksdk/Kconfig"
source "ext/hal/nordic/mdk/Kconfig"
source "ext/hal/nxp/mcux/Kconfig"
source "ext/hal/qmsi/Kconfig"
source "ext/hal/st/stm32cube/Kconfig"

4
ext/hal/Makefile
View file

@ -2,10 +2,10 @@
include $(srctree)/ext/hal/cmsis/Makefile
include $(srctree)/ext/hal/ksdk/Makefile
include $(srctree)/ext/hal/nordic/mdk/Makefile
include $(srctree)/ext/hal/nxp/mcux/Makefile
include $(srctree)/ext/hal/qmsi/Makefile
include $(srctree)/ext/hal/st/stm32cube/Makefile

6
ext/hal/README
View file

@ -7,10 +7,10 @@ cmsis
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) defines a
set of standard interfaces to ARM Cortex-M SoCs.
ksdk
mcux
-------
The Kinetis Software Development Kit (KSDK) provides device header files and
peripheral drivers for Kinetis SoCs.
The NXP MCUXpresso Software Development Kit (MCUX) provides device header files
and peripheral drivers for Kinetis, LPC, and i.MX SoCs.
nordic
-------

8
ext/hal/ksdk/README
View file

@ -1,8 +0,0 @@
The Kinetis Software Development Kit (KSDK) provides device header files and
peripheral drivers for Kinetis SOCs.
The sources in this directory are imported from kex.nxp.com.
The current version supported in Zephyr is KSDK 2.0. It currently supports the
following SOCs:
- MK64F12 (aka K64F)

5
ext/hal/ksdk/Kconfig → ext/hal/nxp/mcux/Kconfig
View file

@ -1,5 +1,4 @@
# Kconfig - Kinetis SDK
# Kconfig - MCUXpresso SDK
#
# Copyright (c) 2016, Freescale Semiconductor, Inc.
#
@ -16,7 +15,7 @@
# limitations under the License.
#
config HAS_KSDK
config HAS_MCUX
bool
select HAS_CMSIS
depends on SOC_FAMILY_KINETIS

32
ext/hal/ksdk/Makefile → ext/hal/nxp/mcux/Makefile
View file

@ -1,4 +1,4 @@
# Makefile - Kinetis SDK
# Makefile - MCUXpresso SDK
#
# Copyright (c) 2016, Freescale Semiconductor, Inc.
#
@ -15,30 +15,30 @@
# limitations under the License.
#
# Translate the SOC name and part number into the ksdk device and CPU name
# Translate the SoC name and part number into the mcux device and cpu name
# respectively.
KSDK_DEVICE = $(shell echo $(CONFIG_SOC) | tr '[:lower:]' '[:upper:]')
KSDK_CPU = CPU_$(subst $(DQUOTE),,$(CONFIG_SOC_PART_NUMBER))
MCUX_DEVICE = $(shell echo $(CONFIG_SOC) | tr '[:lower:]' '[:upper:]')
MCUX_CPU = CPU_$(subst $(DQUOTE),,$(CONFIG_SOC_PART_NUMBER))
ifdef CONFIG_HAS_KSDK
ifdef CONFIG_ETH_KSDK
ZEPHYRINCLUDE += -I$(srctree)/ext/hal/ksdk/components/phyksz8081
ifdef CONFIG_HAS_MCUX
ifdef CONFIG_ETH_MCUX
ZEPHYRINCLUDE += -I$(srctree)/ext/hal/nxp/mcux/components/phyksz8081
endif
ZEPHYRINCLUDE += -I$(srctree)/ext/hal/ksdk/devices/$(KSDK_DEVICE)
ZEPHYRINCLUDE += -I$(srctree)/ext/hal/ksdk/drivers
ZEPHYRINCLUDE += -I$(srctree)/ext/hal/nxp/mcux/devices/$(MCUX_DEVICE)
ZEPHYRINCLUDE += -I$(srctree)/ext/hal/nxp/mcux/drivers
# The ksdk uses the CPU name to expose SOC-specific features of a given
# The mcux uses the cpu name to expose SoC-specific features of a given
# peripheral. For example, the UART peripheral may be instantiated with/without
# a hardware FIFO, and the size of that FIFO may be different for each instance
# in a given SOC. See fsl_device_registers.h and $(KSDK_DEVICE)_features.h
KBUILD_CFLAGS += -D$(KSDK_CPU)
# in a given SoC. See fsl_device_registers.h and $(MCUX_DEVICE)_features.h
KBUILD_CFLAGS += -D$(MCUX_CPU)
# Build ksdk device-specific objects. Although it is not normal Kbuild
# Build mcux device-specific objects. Although it is not normal Kbuild
# practice, drilling down like this avoids the need for repetitive Makefiles
# for every ksdk device.
obj-y += devices/$(KSDK_DEVICE)/fsl_clock.o
# for every mcux device.
obj-y += devices/$(MCUX_DEVICE)/fsl_clock.o
# Build ksdk drivers that can be used for multiple SoC's.
# Build mcux drivers that can be used for multiple SoC's.
obj-y += components/
obj-y += drivers/

11
ext/hal/nxp/mcux/README Normal file
View file

@ -0,0 +1,11 @@
The NXP MCUXpresso Software Development Kit (MCUX) provides device header files
and peripheral drivers for Kinetis, LPC, and i.MX SoCs.
It was previously called the Kinetis Software Development Kit (KSDK), then
renamed to include support for LPC and i.MX SoCs.
The sources in this directory are imported from mcux.nxp.com.
The current version supported in Zephyr is MCUX 2.0. It currently supports the
following SoCs:
- MK64F12 (aka K64F)

4
ext/hal/ksdk/components/Makefile → ext/hal/nxp/mcux/components/Makefile
View file

@ -1,4 +1,4 @@
# Makefile - Kinetis SDK
# Makefile - MCUXpresso SDK
#
# Copyright (c) 2016, ARM Ltd.
#
@ -15,4 +15,4 @@
# limitations under the License.
#
obj-$(CONFIG_ETH_KSDK) += phyksz8081/fsl_phy.o
obj-$(CONFIG_ETH_MCUX) += phyksz8081/fsl_phy.o

0
ext/hal/ksdk/components/phyksz8081/fsl_phy.c → ext/hal/nxp/mcux/components/phyksz8081/fsl_phy.c
View file

0
ext/hal/ksdk/components/phyksz8081/fsl_phy.h → ext/hal/nxp/mcux/components/phyksz8081/fsl_phy.h
View file

0
ext/hal/ksdk/devices/MK64F12/MK64F12.h → ext/hal/nxp/mcux/devices/MK64F12/MK64F12.h
View file

0
ext/hal/ksdk/devices/MK64F12/MK64F12.svd → ext/hal/nxp/mcux/devices/MK64F12/MK64F12.svd
View file

0
ext/hal/ksdk/devices/MK64F12/MK64F12_features.h → ext/hal/nxp/mcux/devices/MK64F12/MK64F12_features.h
View file

0
ext/hal/ksdk/devices/MK64F12/clock_config.c → ext/hal/nxp/mcux/devices/MK64F12/clock_config.c
View file

0
ext/hal/ksdk/devices/MK64F12/clock_config.h → ext/hal/nxp/mcux/devices/MK64F12/clock_config.h
View file

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