drivers: counter: add Andes atcpit100 counter driver
atcpit100 counter driver support 4 32-bit PIT channel, using channel 3 as the default counter. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng
Carles Cufí
parent
88aa873fbc
commit
a2cc4b702f
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@ -29,3 +29,4 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_XLNX_AXI_TIMER counter_xlnx_axi
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zephyr_library_sources_ifdef(CONFIG_COUNTER_TMR_ESP32 counter_esp32_tmr.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_RTC_ESP32 counter_esp32_rtc.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_MICROCHIP_MCP7940N rtc_mcp7940n.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_ANDES_ATCPIT100 counter_andes_atcpit100.c)
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@ -70,4 +70,6 @@ source "drivers/counter/Kconfig.mcp7940n"
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source "drivers/counter/Kconfig.mcux_ctimer"
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source "drivers/counter/Kconfig.andes_atcpit100"
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endif # COUNTER
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12
drivers/counter/Kconfig.andes_atcpit100
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12
drivers/counter/Kconfig.andes_atcpit100
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@ -0,0 +1,12 @@
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# Kconfig Andes ATCPIT100 configuration option
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#
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# Copyright (c) 2022 Andes Technology Corporation.
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#
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# SPDX-License-Identifier: Apache-2.0
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config COUNTER_ANDES_ATCPIT100
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bool "Andes ATCPIT100 PIT driver"
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default y
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depends on DT_HAS_ANDESTECH_ATCPIT100_ENABLED
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help
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Enable driver for the Andes ATCPIT100 PIT controller.
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507
drivers/counter/counter_andes_atcpit100.c
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507
drivers/counter/counter_andes_atcpit100.c
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@ -0,0 +1,507 @@
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/*
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* Copyright (c) 2022 Andes Technology
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/counter.h>
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#include <string.h>
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#define DT_DRV_COMPAT andestech_atcpit100
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/* register definitions */
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#define REG_IDR 0x00 /* ID and Revision Reg. */
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#define REG_CFG 0x10 /* Configuration Reg. */
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#define REG_INTE 0x14 /* Interrupt Enable Reg. */
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#define REG_ISTA 0x18 /* Interrupt Status Reg. */
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#define REG_CHEN 0x1C /* Channel Enable Reg. */
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#define REG_CTRL0 0x20 /* Channel 0 Control Reg. */
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#define REG_RELD0 0x24 /* Channel 0 Reload Reg. */
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#define REG_CNTR0 0x28 /* Channel 0 Counter Reg. */
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#define REG_CTRL1 0x30 /* Channel 1 Control Reg. */
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#define REG_RELD1 0x34 /* Channel 1 Reload Reg. */
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#define REG_CNTR1 0x38 /* Channel 1 Counter Reg. */
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#define REG_CTRL2 0x40 /* Channel 2 Control Reg. */
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#define REG_RELD2 0x44 /* Channel 2 Reload Reg. */
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#define REG_CNTR2 0x48 /* Channel 2 Counter Reg. */
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#define REG_CTRL3 0x50 /* Channel 3 Control Reg. */
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#define REG_RELD3 0x54 /* Channel 3 Reload Reg. */
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#define REG_CNTR3 0x58 /* Channel 3 Counter Reg. */
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#define PIT_BASE (((const struct atcpit100_config *)(dev)->config)->base)
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#define PIT_INTE(dev) (PIT_BASE + REG_INTE)
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#define PIT_ISTA(dev) (PIT_BASE + REG_ISTA)
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#define PIT_CHEN(dev) (PIT_BASE + REG_CHEN)
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#define PIT_CH_CTRL(dev, ch) (PIT_BASE + REG_CTRL0 + (ch << 4))
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#define PIT_CH_RELD(dev, ch) (PIT_BASE + REG_RELD0 + (ch << 4))
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#define PIT_CH_CNTR(dev, ch) (PIT_BASE + REG_CNTR0 + (ch << 4))
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#define CTRL_CH_SRC_PCLK BIT(3)
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#define CTRL_CH_MODE_32BIT BIT(0)
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#define CHANNEL_NUM (4)
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#define CH_NUM_PER_COUNTER (CHANNEL_NUM - 1)
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#define TIMER0_CHANNEL(ch) BIT(((ch) * CHANNEL_NUM))
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typedef void (*atcpit100_cfg_func_t)(void);
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struct atcpit100_config {
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struct counter_config_info info;
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uint32_t base;
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uint32_t divider;
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uint32_t irq_num;
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atcpit100_cfg_func_t cfg_func;
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};
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struct counter_atcpit100_ch_data {
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counter_alarm_callback_t alarm_callback;
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void *alarm_user_data;
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};
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struct atcpit100_data {
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counter_top_callback_t top_callback;
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void *top_user_data;
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uint32_t guard_period;
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struct k_spinlock lock;
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struct counter_atcpit100_ch_data ch_data[CH_NUM_PER_COUNTER];
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};
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static inline uint32_t get_current_tick(const struct device *dev, uint32_t ch)
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{
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const struct atcpit100_config *config = dev->config;
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uint32_t top, now_cnt;
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/* Preload cycles is reload register + 1 */
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top = sys_read32(PIT_CH_RELD(dev, ch)) + 1;
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now_cnt = top - sys_read32(PIT_CH_CNTR(dev, ch));
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return (now_cnt / config->divider);
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}
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static void atcpit100_irq_handler(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct atcpit100_data *data = dev->data;
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counter_alarm_callback_t cb;
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uint32_t int_status, int_enable, ch_enable, cur_ticks;
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uint8_t i;
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ch_enable = sys_read32(PIT_CHEN(dev));
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int_enable = sys_read32(PIT_INTE(dev));
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int_status = sys_read32(PIT_ISTA(dev));
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if (int_status & TIMER0_CHANNEL(3)) {
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if (data->top_callback) {
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data->top_callback(dev, data->top_user_data);
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}
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}
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for (i = 0; i < CH_NUM_PER_COUNTER; i++) {
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if (int_status & TIMER0_CHANNEL(i)) {
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int_enable &= ~TIMER0_CHANNEL(i);
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ch_enable &= ~TIMER0_CHANNEL(i);
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cb = data->ch_data[i].alarm_callback;
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data->ch_data[i].alarm_callback = NULL;
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cur_ticks = get_current_tick(dev, 3);
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cb(dev, i, cur_ticks, data->ch_data[i].alarm_user_data);
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}
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}
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/* Disable channel and interrupt */
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sys_write32(int_enable, PIT_INTE(dev));
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sys_write32(ch_enable, PIT_CHEN(dev));
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/* Clear interrupt status */
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sys_write32(int_status, PIT_ISTA(dev));
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}
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static int counter_atcpit100_init(const struct device *dev)
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{
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const struct atcpit100_config *config = dev->config;
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uint32_t reg;
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/* Disable all channels */
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sys_write32(0, PIT_CHEN(dev));
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/* Channel 0 ~ 3, 32 bits timer, PCLK source */
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reg = CTRL_CH_MODE_32BIT | CTRL_CH_SRC_PCLK;
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sys_write32(reg, PIT_CH_CTRL(dev, 0));
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sys_write32(reg, PIT_CH_CTRL(dev, 1));
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sys_write32(reg, PIT_CH_CTRL(dev, 2));
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sys_write32(reg, PIT_CH_CTRL(dev, 3));
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/* Disable all interrupt and clear all pending interrupt */
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sys_write32(0, PIT_INTE(dev));
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sys_write32(UINT32_MAX, PIT_ISTA(dev));
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/* Select channel 3 as default counter and set max top value */
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reg = config->info.max_top_value * config->divider;
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/* Set cycle - 1 to reload register */
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sys_write32((reg - 1), PIT_CH_RELD(dev, 3));
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config->cfg_func();
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irq_enable(config->irq_num);
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return 0;
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}
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static int atcpit100_start(const struct device *dev)
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{
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struct atcpit100_data *data = dev->data;
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k_spinlock_key_t key;
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uint32_t reg;
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key = k_spin_lock(&data->lock);
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/* Enable channel */
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reg = sys_read32(PIT_CHEN(dev));
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reg |= TIMER0_CHANNEL(3);
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sys_write32(reg, PIT_CHEN(dev));
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int atcpit100_stop(const struct device *dev)
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{
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struct atcpit100_data *data = dev->data;
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k_spinlock_key_t key;
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uint32_t reg;
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key = k_spin_lock(&data->lock);
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/* Disable channel interrupt */
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reg = sys_read32(PIT_INTE(dev));
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reg &= ~TIMER0_CHANNEL(3);
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sys_write32(reg, PIT_INTE(dev));
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/* Disable channel */
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reg = sys_read32(PIT_CHEN(dev));
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reg &= ~TIMER0_CHANNEL(3);
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sys_write32(reg, PIT_CHEN(dev));
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/* Clear interrupt status */
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sys_write32(TIMER0_CHANNEL(3), PIT_ISTA(dev));
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int atcpit100_get_value(const struct device *dev, uint32_t *ticks)
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{
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struct atcpit100_data *data = dev->data;
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k_spinlock_key_t key;
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key = k_spin_lock(&data->lock);
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*ticks = get_current_tick(dev, 3);
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int atcpit100_set_alarm(const struct device *dev, uint8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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const struct atcpit100_config *config = dev->config;
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struct atcpit100_data *data = dev->data;
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uint32_t top, now_cnt, remain_cnt, alarm_cnt, flags, reg;
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k_spinlock_key_t key;
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int err = 0;
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if (chan_id >= CH_NUM_PER_COUNTER) {
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return -ENOTSUP;
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}
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if (!alarm_cfg->callback) {
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return -EINVAL;
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}
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if (data->ch_data[chan_id].alarm_callback) {
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return -EBUSY;
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}
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key = k_spin_lock(&data->lock);
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/* Preload cycles is reload register + 1 */
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top = sys_read32(PIT_CH_RELD(dev, 3)) + 1;
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remain_cnt = sys_read32(PIT_CH_CNTR(dev, 3));
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alarm_cnt = alarm_cfg->ticks * config->divider;
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if (alarm_cnt > top) {
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err = -EINVAL;
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goto out;
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}
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flags = alarm_cfg->flags;
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data->ch_data[chan_id].alarm_callback = alarm_cfg->callback;
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data->ch_data[chan_id].alarm_user_data = alarm_cfg->user_data;
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if (flags & COUNTER_ALARM_CFG_ABSOLUTE) {
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uint32_t irq_on_late, max_rel_val;
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now_cnt = top - remain_cnt;
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max_rel_val = top - (data->guard_period * config->divider);
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irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
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if (now_cnt < alarm_cnt) {
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/* Absolute alarm is in this round counting */
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reg = alarm_cnt - now_cnt;
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irq_on_late = 0;
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} else {
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/* Absolute alarm is in the next round counting */
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reg = alarm_cnt + remain_cnt;
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}
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if (reg > max_rel_val) {
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/* Absolute alarm is in the guard period */
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err = -ETIME;
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if (!irq_on_late) {
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data->ch_data[chan_id].alarm_callback = NULL;
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goto out;
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}
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}
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if (irq_on_late) {
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/* Trigger interrupt immediately */
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reg = 1;
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}
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} else {
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/* Round up decreasing counter to tick boundary */
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now_cnt = remain_cnt + config->divider - 1;
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now_cnt = (now_cnt / config->divider) * config->divider;
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/* Adjusting relative alarm counter to tick boundary */
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reg = alarm_cnt - (now_cnt - remain_cnt);
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}
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/* Set cycle - 1 to reload register */
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sys_write32((reg - 1), PIT_CH_RELD(dev, chan_id));
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/* Enable channel interrupt */
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reg = sys_read32(PIT_INTE(dev));
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reg |= TIMER0_CHANNEL(chan_id);
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sys_write32(reg, PIT_INTE(dev));
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/* Enable channel */
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reg = sys_read32(PIT_CHEN(dev));
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reg |= TIMER0_CHANNEL(chan_id);
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sys_write32(reg, PIT_CHEN(dev));
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out:
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k_spin_unlock(&data->lock, key);
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return err;
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}
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static int atcpit100_cancel_alarm(const struct device *dev, uint8_t chan_id)
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{
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struct atcpit100_data *data = dev->data;
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k_spinlock_key_t key;
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uint32_t reg;
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if (chan_id >= CH_NUM_PER_COUNTER) {
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return -ENOTSUP;
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}
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key = k_spin_lock(&data->lock);
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/* Disable channel interrupt */
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reg = sys_read32(PIT_INTE(dev));
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reg &= ~TIMER0_CHANNEL(chan_id);
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sys_write32(reg, PIT_INTE(dev));
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/* Disable channel */
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reg = sys_read32(PIT_CHEN(dev));
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reg &= ~TIMER0_CHANNEL(chan_id);
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sys_write32(reg, PIT_CHEN(dev));
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/* Clear interrupt status */
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sys_write32(TIMER0_CHANNEL(chan_id), PIT_ISTA(dev));
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data->ch_data[chan_id].alarm_callback = NULL;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int atcpit100_set_top_value(const struct device *dev,
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const struct counter_top_cfg *cfg)
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{
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const struct atcpit100_config *config = dev->config;
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struct atcpit100_data *data = dev->data;
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uint32_t ticks, reg, reset_counter = 1;
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k_spinlock_key_t key;
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int err = 0;
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uint8_t i;
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for (i = 0; i < counter_get_num_of_channels(dev); i++) {
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if (data->ch_data[i].alarm_callback) {
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return -EBUSY;
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}
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}
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if (cfg->ticks > config->info.max_top_value) {
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return -ENOTSUP;
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}
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key = k_spin_lock(&data->lock);
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if (cfg->callback) {
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/* Disable channel interrupt */
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reg = sys_read32(PIT_INTE(dev));
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reg &= ~TIMER0_CHANNEL(3);
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sys_write32(reg, PIT_INTE(dev));
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data->top_callback = cfg->callback;
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data->top_user_data = cfg->user_data;
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/* Enable channel interrupt */
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reg = sys_read32(PIT_INTE(dev));
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reg |= TIMER0_CHANNEL(3);
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sys_write32(reg, PIT_INTE(dev));
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}
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if (cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
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/* Don't reset counter */
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reset_counter = 0;
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ticks = get_current_tick(dev, 3);
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if (ticks >= cfg->ticks) {
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err = -ETIME;
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if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
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/* Reset counter if current is late */
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reset_counter = 1;
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}
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}
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}
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/* Set cycle - 1 to reload register */
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reg = cfg->ticks * config->divider;
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sys_write32((reg - 1), PIT_CH_RELD(dev, 3));
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if (reset_counter) {
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/* Disable channel */
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reg = sys_read32(PIT_CHEN(dev));
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reg &= ~TIMER0_CHANNEL(3);
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sys_write32(reg, PIT_CHEN(dev));
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/* Clear interrupt status */
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sys_write32(TIMER0_CHANNEL(3), PIT_ISTA(dev));
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/* Enable channel interrupt */
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reg = sys_read32(PIT_INTE(dev));
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reg |= TIMER0_CHANNEL(3);
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sys_write32(reg, PIT_INTE(dev));
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/* Enable channel */
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reg = sys_read32(PIT_CHEN(dev));
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reg |= TIMER0_CHANNEL(3);
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sys_write32(reg, PIT_CHEN(dev));
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}
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k_spin_unlock(&data->lock, key);
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return err;
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}
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static uint32_t atcpit100_get_pending_int(const struct device *dev)
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{
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uint32_t reg = sys_read32(PIT_ISTA(dev));
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reg &= (TIMER0_CHANNEL(0) | TIMER0_CHANNEL(1) |
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TIMER0_CHANNEL(2) | TIMER0_CHANNEL(3));
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return !(!reg);
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}
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static uint32_t atcpit100_get_top_value(const struct device *dev)
|
||||
{
|
||||
const struct atcpit100_config *config = dev->config;
|
||||
uint32_t top = sys_read32(PIT_CH_RELD(dev, 3)) + 1;
|
||||
|
||||
return (top / config->divider);
|
||||
}
|
||||
|
||||
static uint32_t atcpit100_get_guard_period(const struct device *dev,
|
||||
uint32_t flags)
|
||||
{
|
||||
struct atcpit100_data *data = dev->data;
|
||||
|
||||
return data->guard_period;
|
||||
}
|
||||
|
||||
static int atcpit100_set_guard_period(const struct device *dev,
|
||||
uint32_t ticks, uint32_t flags)
|
||||
{
|
||||
const struct atcpit100_config *config = dev->config;
|
||||
struct atcpit100_data *data = dev->data;
|
||||
uint32_t top = sys_read32(PIT_CH_RELD(dev, 3)) + 1;
|
||||
|
||||
if ((ticks * config->divider) > top) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data->guard_period = ticks;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct counter_driver_api atcpit100_driver_api = {
|
||||
.start = atcpit100_start,
|
||||
.stop = atcpit100_stop,
|
||||
.get_value = atcpit100_get_value,
|
||||
.set_alarm = atcpit100_set_alarm,
|
||||
.cancel_alarm = atcpit100_cancel_alarm,
|
||||
.set_top_value = atcpit100_set_top_value,
|
||||
.get_pending_int = atcpit100_get_pending_int,
|
||||
.get_top_value = atcpit100_get_top_value,
|
||||
.get_guard_period = atcpit100_get_guard_period,
|
||||
.set_guard_period = atcpit100_set_guard_period,
|
||||
};
|
||||
|
||||
#define COUNTER_ATCPIT100_INIT(n) \
|
||||
static void counter_atcpit100_cfg_##n(void); \
|
||||
static struct atcpit100_data atcpit100_data_##n; \
|
||||
\
|
||||
static const struct atcpit100_config atcpit100_config_##n = { \
|
||||
.info = { \
|
||||
.max_top_value = \
|
||||
(UINT32_MAX/DT_INST_PROP(n, prescaler)),\
|
||||
.freq = (DT_INST_PROP(n, clock_frequency) / \
|
||||
DT_INST_PROP(n, prescaler)), \
|
||||
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
|
||||
.channels = CH_NUM_PER_COUNTER, \
|
||||
}, \
|
||||
.base = DT_INST_REG_ADDR(n), \
|
||||
.divider = DT_INST_PROP(n, prescaler), \
|
||||
.irq_num = DT_INST_IRQN(n), \
|
||||
.cfg_func = counter_atcpit100_cfg_##n, \
|
||||
}; \
|
||||
\
|
||||
DEVICE_DT_INST_DEFINE(n, \
|
||||
counter_atcpit100_init, \
|
||||
NULL, \
|
||||
&atcpit100_data_##n, \
|
||||
&atcpit100_config_##n, \
|
||||
POST_KERNEL, \
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
|
||||
&atcpit100_driver_api); \
|
||||
\
|
||||
static void counter_atcpit100_cfg_##n(void) \
|
||||
{ \
|
||||
IRQ_CONNECT(DT_INST_IRQN(n), \
|
||||
DT_INST_IRQ(n, priority), \
|
||||
atcpit100_irq_handler, \
|
||||
DEVICE_DT_INST_GET(n), \
|
||||
0); \
|
||||
}
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(COUNTER_ATCPIT100_INIT)
|
||||
Loading…
Reference in a new issue