dts: nxp: Add LPADC clocks properities to SoC dtsi
Add LPADC clock properties to SoC dtsi on adc/lpadc node Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
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/*
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* Copyright (c) 2020 Lemonbeat GmbH
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -280,6 +281,7 @@
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offset-value-a = <10>;
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offset-value-b = <10>;
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#io-channel-cells = <1>;
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clocks = <&syscon MCUX_LPADC1_CLK>;
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};
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usbhs: usbhs@144000 {
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@ -1,5 +1,5 @@
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/*
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* Copyright 2022 NXP
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* Copyright 2022, 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -282,6 +282,7 @@
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dmas = <&dma0 21>, <&dma0 22>;
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dma-names = "adc0-dma0", "adc0-dma1";
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nxp,reference-supply = <&vref0>;
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clocks = <&syscon MCUX_LPADC1_CLK>;
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};
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dac0: dac@b2000 {
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/*
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* Copyright (c) 2020, Linaro Ltd.
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -331,6 +332,7 @@
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offset-value-a = <10>;
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offset-value-b = <10>;
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#io-channel-cells = <1>;
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clocks = <&syscon MCUX_LPADC1_CLK>;
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};
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usbfs: usbfs@84000 {
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@ -1,5 +1,5 @@
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/*
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* Copyright 2021,2023 NXP
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* Copyright 2021,2023-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -867,6 +867,7 @@
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offset-value-a = <10>;
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offset-value-b = <10>;
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#io-channel-cells = <1>;
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clocks = <&ccm IMX_CCM_LPADC1_CLK 0 0>;
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};
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lpadc1: lpadc@40054000 {
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@ -882,6 +883,7 @@
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offset-value-a = <10>;
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offset-value-b = <10>;
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#io-channel-cells = <1>;
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clocks = <&ccm IMX_CCM_LPADC2_CLK 0 0>;
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};
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acmp1: cmp@401a4000 {
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/*
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* Copyright 2022-2023, NXP
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* Copyright 2022-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -542,6 +542,7 @@
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offset-value-a = <10>;
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offset-value-b = <10>;
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#io-channel-cells = <1>;
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clocks = <&clkctl1 MCUX_LPADC1_CLK>;
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};
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smartdma: dma@27020 {
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/*
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* Copyright (c) 2020, NXP
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* Copyright 2020, 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -387,6 +387,7 @@
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offset-value-a = <10>;
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offset-value-b = <10>;
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#io-channel-cells = <1>;
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clocks = <&clkctl1 MCUX_LPADC1_CLK>;
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};
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ctimer0: ctimer@28000 {
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