patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 7 Packages Projects Releases Wiki Activity

soc: xtensa: intel_adsp: ace: set number of cpus at boot

Browse source 
We look at the Intra DSP communications capability register (DFIDCCP)
to determine the number of cores.  There might be a better way to
determine the number of cores, but this works for now.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
This commit is contained in:
Kumar Gala 2022-10-27 09:00:44 -05:00 committed by Anas Nashif
parent 6bdd91e9b1
commit a574957c74
2 changed files with 12 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
soc/xtensa/intel_adsp/ace/Kconfig.series
View file

@ -10,5 +10,6 @@ config SOC_SERIES_INTEL_ACE
select ARCH_HAS_COHERENCE
select SCHED_IPI_SUPPORTED
select DW_ICTL_ACE
select SOC_HAS_RUNTIME_NUM_CPUS
help
Intel ADSP ACE

11
soc/xtensa/intel_adsp/ace/multiprocessing.c
View file

@ -6,6 +6,7 @@
#include <zephyr/kernel.h>
#include <zephyr/sys/check.h>
#include <zephyr/arch/cpu.h>
#include <soc.h>
#include <adsp_boot.h>
@ -40,8 +41,18 @@ static void ipc_isr(void *arg)
#endif
}
#define DFIDCCP 0x2020
#define CAP_INST_SHIFT 24
#define CAP_INST_MASK BIT_MASK(4)
unsigned int soc_num_cpus;
void soc_mp_init(void)
{
/* Need to set soc_num_cpus early to arch_num_cpus() works properly */
soc_num_cpus = ((sys_read32(DFIDCCP) >> CAP_INST_SHIFT) & CAP_INST_MASK) + 1;
soc_num_cpus = MIN(CONFIG_MP_MAX_NUM_CPUS, soc_num_cpus);
IRQ_CONNECT(ACE_IRQ_TO_ZEPHYR(ACE_INTL_IDCA), 0, ipc_isr, 0, 0);
irq_enable(ACE_IRQ_TO_ZEPHYR(ACE_INTL_IDCA));